Nothing Special   »   [go: up one dir, main page]

WO2012115000A1 - Substrat à matrice active, dispositif d'affichage et dispositif de réception de télévision - Google Patents

Substrat à matrice active, dispositif d'affichage et dispositif de réception de télévision Download PDF

Info

Publication number
WO2012115000A1
WO2012115000A1 PCT/JP2012/053797 JP2012053797W WO2012115000A1 WO 2012115000 A1 WO2012115000 A1 WO 2012115000A1 JP 2012053797 W JP2012053797 W JP 2012053797W WO 2012115000 A1 WO2012115000 A1 WO 2012115000A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
active matrix
matrix substrate
gate
pixel
Prior art date
Application number
PCT/JP2012/053797
Other languages
English (en)
Japanese (ja)
Inventor
輝幸 中西
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2012115000A1 publication Critical patent/WO2012115000A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to an active matrix substrate, a display device, and a television receiver.
  • a liquid crystal panel used in a liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between a pair of glass substrates, one of which includes a TFT (Thin Film Transistor) as an active element.
  • An active matrix substrate is used.
  • this active matrix substrate a large number of gate lines and source lines are provided in a lattice pattern in the display area, and a film-like pixel electrode is disposed in an area surrounded by the gate lines and the source lines.
  • a pixel as a display unit is configured.
  • the pixel electrode is provided on the upper layer side relative to a wiring group such as a gate wiring and a source wiring.
  • Such an active matrix substrate active matrix type TFT array
  • Patent Document 1 Such an active matrix substrate (active matrix type TFT array) is disclosed in Patent Document 1, for example.
  • a residual film of the pixel electrode may remain between the adjacent pixel electrodes with the gate wiring or the like interposed therebetween. If such a residual film remains, a short circuit may occur between adjacent pixel electrodes, which may reduce the manufacturing yield.
  • a glass substrate for example, a CF substrate
  • this light-shielding part is provided in the position which overlaps with locations other than the pixel electrode on an active matrix substrate. For this reason, when a short circuit occurs between the pixel electrodes adjacent to each other with the gate wiring or the like interposed therebetween, it is impossible to confirm the presence or absence of the short circuit from the surface side of the liquid crystal panel after the liquid crystal panel is manufactured. Furthermore, since the wiring group such as the gate wiring is formed of a light-shielding material, it is impossible to confirm the presence or absence of a short circuit from the back side of the liquid crystal panel.
  • An object of the present invention is to provide an active matrix substrate in which the presence or absence of a short circuit between adjacent pixel electrodes can be confirmed from the back side.
  • the technology disclosed in this specification includes a light-transmitting substrate, a plurality of pixel electrodes arranged in a matrix on the substrate, a first wiring arranged on the substrate, and the substrate.
  • An active matrix substrate provided with a second wiring, wherein the pixel electrode is provided on an upper layer side relative to the first wiring, and the first wiring is at least adjacent to the pixel electrode.
  • the second wiring is provided between at least the adjacent pixel electrodes, has a relatively smaller width than the first wiring, and intersects the first wiring.
  • the present invention relates to an active matrix substrate that is disposed and has a through-hole that passes through the first wiring in the thickness direction in a part of the first wiring between adjacent pixel electrodes.
  • the above active matrix substrate by providing a through hole on the first wiring, even after another substrate (such as a CF substrate) having a light shielding portion on the surface side of the active matrix substrate is bonded, By applying light from the back surface side of the active matrix substrate, the upper layer side of the first wiring can be seen through the light-transmitting substrate and the through hole. Therefore, when the pixel electrodes adjacent to each other with the first wiring interposed therebetween are short-circuited, the short-circuit portion located on the upper layer side of the first wiring can be visually recognized through the through hole. That is, it is possible to confirm the presence or absence of a short circuit between adjacent pixel electrodes from the back side.
  • the first wiring is formed with a larger width than the second wiring, a through hole can be easily provided on the first wiring.
  • the through hole may be provided in a substantially linear shape along a direction in which the first wiring extends. According to this configuration, since the presence or absence of a short circuit between adjacent pixel electrodes can be confirmed in a wide range, the presence or absence of a short circuit can be effectively confirmed.
  • a plurality of the through holes may be provided in parallel between the adjacent pixel electrodes.
  • a short circuit occurs between the first wiring and the counter electrode. Will occur.
  • the part of the first wiring that contacts the foreign object is trimmed so as to be insulated from the surroundings. By doing so, the short circuit can be corrected.
  • the lengths of the through holes provided in parallel may be equal. According to this configuration, the plurality of through holes can be easily manufactured in the manufacturing process.
  • a through hole having a width smaller than the width of the through hole may be provided at both ends of the through hole.
  • an etching liquid pool may be generated at both ends of the through hole.
  • the through hole may be provided so as to extend to a portion overlapping with the second wiring. According to this configuration, even when a short circuit between the pixel electrodes occurs in a portion overlapping with the second wiring, the presence or absence of the short circuit portion can be confirmed.
  • a switching element having a gate electrode, a source electrode, and a drain electrode, wherein the second wiring is a source wiring connected to the source electrode, and the first wiring is connected to the gate electrode;
  • the capacitor wiring may partially overlap with the pixel electrode, and the gate wiring and the capacitor wiring may be alternately arranged with the pixel electrode interposed therebetween. According to this configuration, it is possible to realize a specific configuration of an active matrix substrate capable of confirming the presence or absence of a short circuit between adjacent pixel electrodes with a gate wiring or a capacitor wiring interposed therebetween.
  • a plurality of pixel regions wherein the pixel electrode is one subpixel, a pair of the subpixels is disposed in one pixel region, and the capacitor wiring is provided between the pair of subpixels, One end of the subpixel may overlap with the capacitor wiring, and the through hole may be provided in a part of the capacitor wiring.
  • an active matrix substrate of a multi-pixel driving method can be realized.
  • the through hole is provided on the capacitor wiring, it is possible to confirm whether there is a short circuit between adjacent pixel electrodes across the capacitor wiring in the multi-pixel driving type active matrix substrate.
  • the technology disclosed in this specification includes the active matrix substrate described above, a lighting device disposed on the back side of the active matrix substrate, and a front surface side of the active matrix substrate. And a display device that performs display using the display panel.
  • a display device in which the above-described display panel is a liquid crystal panel using liquid crystal is also new and useful.
  • a television receiver provided with the above display device is also new and useful.
  • an active matrix substrate capable of confirming a short circuit between adjacent pixel electrodes from the back surface side can be provided.
  • FIG. 1 is an exploded perspective view of a television receiver TV according to Embodiment 1.
  • FIG. An exploded perspective view of the liquid crystal display device 10 is shown.
  • a cross-sectional view of the liquid crystal display device 10 is shown.
  • a cross-sectional view of the liquid crystal panel 11 is shown.
  • a plan view of a part of the active matrix substrate 30 is shown.
  • the top view of TFT37 vicinity is shown.
  • the back view of the slit 40 vicinity is shown.
  • a sectional view of the vicinity of the slit 40 is shown.
  • FIG. 6 shows a back view of the vicinity of a slit 140a of an active matrix substrate 130 according to a modification of the first embodiment.
  • the rear view of slit 240a, 240b vicinity of the active matrix substrate 230 which concerns on Embodiment 2 is shown.
  • Sectional drawing of slit 240a, 240b vicinity is shown.
  • substrate 230 with which the foreign material G mixed is shown.
  • substrate 230 with which the foreign material G mixed was shown.
  • a sectional view in the vicinity of a foreign matter G of a liquid crystal display device is shown.
  • the rear view of slit 340a, 340b vicinity of the active matrix substrate 330 which concerns on Embodiment 3 is shown.
  • the back view of the edge part of slit 340a, 340b is shown.
  • the back view of the edge part of slit 340a, 340b at the time of overetching is shown.
  • Embodiment 1 will be described with reference to the drawings.
  • a part of each drawing shows an X-axis, a Y-axis, and a Z-axis, and each axis direction is drawn in a common direction in each drawing.
  • the Y-axis direction coincides with the vertical direction
  • the X-axis direction coincides with the horizontal direction.
  • FIG. 1 is an exploded perspective view of the television receiver TV according to the first embodiment.
  • the television receiver TV includes a liquid crystal display device 10, front and back cabinets Ca and Cb that are accommodated so as to sandwich the display device D, a power source P, a tuner T, and a stand S.
  • the liquid crystal display device 10 has a horizontally long rectangular shape as a whole and is accommodated in a vertically placed state.
  • FIG. 2 is an exploded perspective view of the liquid crystal display device 10.
  • FIG. 3 shows a cross-sectional configuration of a cross section obtained by cutting the liquid crystal display device 10 in the vertical direction (Y-axis direction).
  • the upper side shown in FIG. 2 is the front side
  • the lower side is the back side.
  • the liquid crystal display device 10 includes a liquid crystal panel 16 that is a display panel and a backlight device 12 that is an external light source, and these are integrally held by a bezel 12 having a frame shape or the like. It is like that.
  • the backlight device 12 is a so-called direct-type backlight in which a light source is arranged directly under the back surface of the liquid crystal panel 11, and has a chassis 14 opened on the front side (light emitting side, liquid crystal panel 11 side), A reflective sheet 15 laid on the optical member 16, an optical member 16 attached to the opening of the chassis 14, a frame 17 for fixing the optical member 16, and a plurality of cold cathodes accommodated in the chassis 14 in parallel.
  • the tube 18 is configured to include a lamp holder 19 that shields light from the end of the cold cathode tube 18 and has light reflectivity.
  • FIG. 4 shows a cross-sectional view of the liquid crystal panel 11.
  • the liquid crystal panel 11 includes a liquid crystal material, which is a substance whose optical characteristics change with application of an electric field, between a pair of transparent (translucent) glass substrates 20 and 30.
  • the liquid crystal layer 24 is enclosed.
  • the two substrates 20, 30 constituting the liquid crystal panel 11 the one disposed on the back side (backlight device 12 side) is the active matrix substrate 30, and is disposed on the front side (light emission side of the active matrix substrate 20).
  • One is a CF substrate 20.
  • alignment films 26 and 28 for facing the liquid crystal layer 24 and aligning liquid crystal molecules contained in the liquid crystal layer 24 are formed on the inner surfaces of both the substrates 20 and 30, respectively.
  • the pretilt angle of the liquid crystal molecules in the liquid crystal layer 24 is controlled by irradiating the alignment films 26 and 28 with ultraviolet rays.
  • a pair of front and back polarizing plates 22 are attached to the outer surfaces of the substrates 20 and 30 (see FIG. 3).
  • a color filter (FIG. 5) composed of colored portions exhibiting R (red), G (green), and B (blue). (Not shown), and a large number of the colored portions are arranged in parallel in a matrix at positions that overlap each pixel electrode 36 on the active matrix substrate 30 side, which will be described later.
  • the light-shielding part black matrix which is not shown in figure which comprises the grid
  • the light shielding portion is arranged so as to overlap with a source wiring 38, a gate wiring 32, and a Cs wiring 34 on the active matrix substrate 30 side, which will be described later, in plan view.
  • a counter electrode (not shown) facing the pixel electrode 36 on the active matrix substrate 30 side is provided on the surface of each colored portion and light shielding portion.
  • the counter electrode is made of a transparent film electrode such as an ITO (Indium Tin Oxide) film, and is formed in a solid shape on the entire surface.
  • An alignment film 26 is formed on the entire surface of the counter electrode in the same manner as the counter electrode.
  • FIG. 5 is a plan view of a part of the active matrix substrate 30 as viewed from the front side.
  • FIG. 6 is a plan view of the vicinity of the TFT 37 of the active matrix substrate 30 as viewed from the front side.
  • the active matrix substrate 30 On the inner surface side of the active matrix substrate 30 (the liquid crystal layer 24 side and the side facing the CF substrate 20), as shown in FIG.
  • a plurality of Cs wirings 34 arranged in parallel with each other while being arranged between the gate wirings 32 and in parallel with the gate wirings 32 are formed in a lattice shape.
  • the vertical direction of the drawing is referred to as the column direction
  • the horizontal direction of the drawing is referred to as the row direction.
  • the gate wiring 32 and the Cs wiring 34 are alternately arranged, and the interval between the adjacent gate wiring 32 and the Cs wiring 34 is set to be approximately equal.
  • the source wiring 38 extends in the column direction along the end of each pixel region PE (the end along the direction orthogonal to the gate wiring 32), and has a relatively small width with respect to the gate wiring 32 and the Cs wiring 34. It is formed with.
  • the Cs wiring 34 extends in the row direction so as to partially overlap the end portions of the two pixel regions PE adjacent in the column direction.
  • the gate wiring 32, the source wiring 38, and the Cs wiring 34 are each made of a metal film patterned on the active matrix substrate 30, and the metal film has a light shielding property.
  • each of these wirings is made of a metal material containing copper (Cu), for example, an alloy made of copper and titanium (Ti).
  • Cu copper
  • Ti titanium
  • a plurality of slits 40 are formed in a part of the Cs wiring 34 along the direction in which the Cs wiring 34 extends. The slit 40 will be described in detail later.
  • the gate wiring 32 and the Cs wiring 34 are provided by the same material in the same process in the manufacturing process of the active matrix substrate 30 and are arranged in the same layer.
  • the gate wiring 32 and the Cs wiring 34 are arranged on the lower layer side relative to the source wiring 38.
  • a gate insulating film 48 is interposed between the source wiring 38, the gate wiring 32, and the Cs wiring 38 that intersect with each other, thereby maintaining an insulating state.
  • an interlayer insulating film (passivation film, protective layer) (not shown) is provided on a further upper layer side of the source wiring 38 relatively disposed on the upper layer side, and the source wiring 38 is protected by this interlayer insulating film. It is illustrated.
  • TFTs 37 serving as switching elements connected to both the wirings 38 and 32 are formed at the intersections of the source wirings 38 and the gate wirings 32, respectively.
  • the TFT 37 is a so-called reverse stagger type (bottom gate type), and is disposed on the gate wiring 32.
  • a part of the gate wiring 32 is a gate electrode 37a.
  • a scanning signal inputted to the gate wiring 32 is supplied to the gate electrode 37a at a predetermined timing.
  • a branch line drawn from the source wiring 38 to the TFT 37 side constitutes a source electrode 37b of the TFT 37 that overlaps the gate electrode 37a via a semiconductor film or the like (not shown).
  • the image signal (data signal) input to the source wiring 38 is supplied.
  • a large number of pixel electrodes 36 having a vertically long rectangular shape are arranged in a matrix.
  • a drain wiring 42 is connected to the pixel electrode 36 through a contact hole 44, and one end side of the drain wiring 42 is drawn to the TFT 37 side and overlapped with a gate electrode 37a via a semiconductor film or the like (not shown). It is an electrode 37c.
  • the pixel electrode 36 is disposed on a further upper layer side of the above-described interlayer insulating film, whereas the drain wiring 42 is provided in the same layer by the same material and in the same process as the source wiring 38 described above. Yes.
  • the drain wiring 42 is provided on the upper layer side relative to the gate wiring 32 and the Cs wiring 34.
  • the end of the pixel electrode 36 on the Cs wiring 34 side is disposed so as to overlap the Cs wiring 34 via the gate insulating film 48 and the interlayer insulating film, thereby forming a capacitance with the Cs wiring 34. (See reference numeral 36a).
  • the pixel electrode 36 is made of a transparent film electrode such as ITO or ZnO (Zinc Oxide).
  • the pixel electrode 36 is formed of an ITO film.
  • the active matrix substrate 30 employs a configuration in which one pixel region PE as a display unit is driven by being divided into two subpixels SP1 and SP2.
  • the two subpixels SP1 and SP2 constituting one pixel region PE are constituted by two pixel electrodes 36 adjacent in the column direction with the gate wiring 32 interposed therebetween.
  • the two pixel electrodes 36 adjacent in the column direction across the Cs wiring 34 are subpixels SP1 and SP2 constituting another pixel region PE. Therefore, each Cs wiring 34 is superimposed on the first subpixel SP1 and the second subpixel SP2 constituting another pixel region PE.
  • the upper pixel electrode 36 across the gate wiring 32 is referred to as a first subpixel SP1
  • the lower pixel electrode 36 is referred to as a second subpixel SP2.
  • the first subpixel SP1 and the second subpixel SP2 have a vertically symmetrical shape with the gate wiring 32 as the axis of symmetry, and are formed in a state of being separated from each other.
  • Two TFTs 37 are formed at the intersections of the gate lines 32 and the source lines 38, and are arranged vertically on the gate lines 32 as shown in FIG.
  • the two TFTs 37 arranged side by side on the gate wiring 32 drive the first subpixel SP1 and the second subpixel SP2 that constitute the same pixel region PE.
  • the first subpixel SP1 and the second subpixel SP2 are adjusted by adjusting the signal input to the Cs wiring 34.
  • the pixel SP2 can be driven with different gradations.
  • the first subpixel SP1 is adjusted by adjusting the signal input to the Cs wiring 34 superimposed on the first subpixel SP1 and the signal input to the Cs wiring 34 different from the above superimposed on the second subpixel SP2.
  • the size obtained by adding the gray level of the second sub-pixel SP2 and the gray level of the second sub-pixel SP2 divided by 2 may be the target gray level of the pixel.
  • a so-called multi-pixel driving method can be performed, and good viewing angle characteristics can be obtained.
  • FIG. 7 is a back view of the vicinity of the Cs wiring 34 of the active matrix substrate 30 as viewed from the back side.
  • FIG. 8 is a cross-sectional view of a portion of the Cs wiring 34 where the slit 40 is formed, and shows a cross-sectional configuration of the AA cross section in FIG.
  • the upper side of the figure is the surface side (upper layer side) of the active matrix substrate 30, and the lower side of the figure is the back side (lower layer side) of the active matrix substrate 30.
  • the slit 40 is provided so as to penetrate the Cs wiring 34 in the thickness direction, and is formed at the substantially center of the Cs wiring 34 in the width direction.
  • the slit 40 is formed in a substantially straight line along the direction in which the Cs wiring 34 extends, and both end portions thereof extend to the vicinity of both end portions in the row direction of the pixel electrode 36.
  • the end portion of the drain wiring 42 located on the Cs wiring 34 side overlaps the Cs wiring 34 with the gate insulating film 48 interposed therebetween.
  • Reference numeral RM in FIG. 7 and FIG. 8 to be described later is an ITO residual film, which is generated by mistake when the ITO residual film RM (pixel electrode 36 is formed) between adjacent pixel electrodes 36 across the Cs wiring 34. This shows the case where the obtained film) remains.
  • the ITO remaining film RM remains in this way, the pixel electrodes 36 and 36 adjacent to each other with the Cs wiring 34 interposed therebetween are short-circuited via the ITO remaining film RM.
  • the vicinity of the slit 40 of the active matrix substrate 30 has a cross-sectional configuration in which a substrate 46, a Cs wiring 34, a gate insulating film 48, and a pixel electrode 36 are laminated in order from the back side of the active matrix substrate 30.
  • substrate 46 comprises flat form, is formed with materials, such as glass, and has translucency.
  • the Cs wiring 34 is formed on a part of the substrate 46 so as to have a substantially trapezoidal shape in a sectional view.
  • the gate insulating film 48 is laminated on the substrate 46 and the Cs wiring 34 with a substantially uniform thickness, is formed of an insulating material such as silicon nitride (SiNx), and has translucency.
  • the pixel electrode 36 is stacked on the gate insulating film 48 with a substantially uniform thickness.
  • the slit 40 has a tapered shape in which a side surface is inclined inward from the upper layer side toward the lower layer side in a cross-sectional view and penetrates the Cs wiring 34 vertically.
  • a concave portion 48 a that opens to the upper layer side is formed in a portion overlapping the slit 40 of the gate insulating film 48. Similar to the cross-sectional shape of the slit 40, the concave portion 48 a has a tapered shape whose side surface is inclined inward from the upper layer side toward the lower layer side in a cross-sectional view.
  • substrate 46 and the gate insulating film 48 have translucency, the upper layer side of Cs wiring 34 can be visually recognized through the slit 40 from the back surface side of the board
  • FIG. . Therefore, if the ITO residual film RM remains between the pixel electrodes 36 adjacent in the column direction and overlapping with the slit 40, the ITO residual film RM is confirmed through the slit 40 from the back side of the substrate 46. It becomes possible.
  • the slit 40 is formed in the manufacturing process of the active matrix substrate 30.
  • the Cs wiring 34 and the gate wiring 32 are patterned on the substrate 46, and the Cs wiring 34 and the gate wiring 32 are formed on the substrate 46.
  • wet etching is performed on a portion of the Cs wiring where the slit 40 is to be formed through a mask having an opening at the portion to form the slit 40. Since the Cs wiring 34 is formed with a width larger than that of the source wiring 38, the Cs wiring 34 has a sufficient width for forming the slit 40.
  • the etching for forming the slit 40 is isotropic etching, the side surface of the etching is inward from the upper layer side (etching start side) to the lower layer side (etching end side) as described above.
  • the taper is inclined.
  • a gate insulating film 48 is then formed on the substrate 46 and the Cs wiring 34.
  • the gate insulating film 48 is formed with a substantially uniform thickness, corresponding to the cross-sectional shape of the slit 40, the gate insulating film 48 is opened to the upper layer side at a portion overlapping the slit 40 of the gate insulating film 48.
  • a concave portion 48a having a tapered side surface is formed.
  • the slit 40 is provided on the Cs wiring 34 so that the liquid crystal layer 24 and the CF substrate 20 including the light shielding portion are bonded to the surface side of the active matrix substrate 30 and the liquid crystal. Even after the display device 10 is manufactured, the upper layer side of the Cs wiring 34 can be seen through the substrate 46 and the slit 40 by applying light from the lower side of the active matrix substrate 30 (the back side of the liquid crystal display device 10). it can.
  • the short-circuit portion (ITO remaining film RM) located on the upper layer side of the Cs wiring 34 can be visually recognized through the slit 40. That is, it is possible to confirm from the back surface side whether or not there is a short circuit between adjacent pixel electrodes 36.
  • the Cs wiring 34 is formed with a large width with respect to the source wiring 28, so that the slit 40 can be provided on the Cs wiring 34.
  • the active matrix substrate 30 according to the present embodiment is configured by a multi-pixel driving method, the two pixel electrodes 36 are provided apart from each other with the Cs wiring 34 interposed therebetween. For this reason, the pixel electrodes 36 and 36 adjacent to each other with the Cs wiring 36 interposed therebetween may be short-circuited due to problems in manufacturing the active matrix substrate 30. Since the active matrix substrate 30 according to the present embodiment has the slit 40 formed on the Cs wiring 30, the multi-pixel in which the two pixel electrodes 36 and 36 are provided with the Cs wiring 34 interposed therebetween as described above. It is suitable for the driving method.
  • the through hole is a slit (substantially linear) 40 provided along the direction in which the Cs wiring 34 extends. For this reason, the presence or absence of a short circuit between adjacent pixel electrodes 36 can be confirmed in a wide range, and the presence or absence of a short circuit can be effectively confirmed.
  • the active matrix substrate 30 is disposed on the upper layer side relative to the Cs wiring 34 and has a light-transmitting gate disposed on the lower layer side relative to the pixel electrode 36.
  • An insulating film 48 is further provided.
  • a concave portion 48a that opens toward the upper layer side of the gate insulating film 48 is provided at a portion that overlaps the slit 40 of the gate insulating film 48, and the side surface of the concave portion 48a is inward from the upper layer side to the lower layer side in a cross-sectional view.
  • the taper is inclined. As a result, disconnection of the gate insulating film 48 in the recess 48a can be suppressed, and good coverage of the gate insulating film 48 can be obtained.
  • FIG. 9 shows a rear view of the vicinity of the slit 140 of the active matrix substrate 130 according to a modification of the first embodiment.
  • the length of the slit 140 is different from that of the first embodiment, and other configurations are the same as those of the first embodiment.
  • part which added the number 100 to the reference symbol of Embodiment 1 is the same as the site
  • the slit 140 is formed to extend to the intersection CR of the Cs wiring 134 and the source wiring 138.
  • a short circuit occurs between the pixel electrodes 136 adjacent in the column direction (or diagonally across the intersection CR) even at the intersection CR of the Cs wiring 134 and the source wiring 138.
  • the active matrix substrate 130 according to the modification even when a short circuit occurs between the adjacent pixel electrodes 136 at the intersection CR of the Cs wiring 134 and the source wiring 138, the presence / absence of the short circuit is determined from the back side. 140 can be confirmed.
  • FIG. 10 is a back view of the vicinity of the slits 240a and 240b of the active matrix substrate 230 according to the second embodiment.
  • FIG. 11 is a cross-sectional view in the vicinity of the slits 240a and 240b, and shows a cross-sectional configuration of the BB cross section in FIG.
  • FIG. 12 shows a back view of the vicinity of the slits 240a and 240b before the correction of the active matrix substrate 230 when the foreign matter G is mixed between the two slits 240a and 240b.
  • FIG. 13 shows a back view of the vicinity of the slits 240a and 240b after correction in such a case.
  • FIG. 14 is a cross-sectional view in the vicinity of the foreign matter G of the liquid crystal display device, and shows a cross-sectional configuration along the line CC in FIG.
  • the second embodiment is different from the first embodiment in the arrangement and number of slits 240a and 240b. Since the other configuration is the same as that of the first embodiment, description of the structure, operation, and effect is omitted. 10, the part where the numeral 200 is added to the reference numeral in FIG. 7 and the part where the numeral 200 is added to the reference numeral in FIG. 8 in FIG. 11 are the same as the parts described in the first embodiment.
  • the CF substrate 220 shown in FIG. 13 will be described.
  • the CF substrate 220 is arranged to face the active matrix substrate 230 on the surface side of the active matrix substrate 230.
  • the CF substrate 220 is provided with a color filter including the colored portions 223 on the inner surface side (the liquid crystal layer side, the surface facing the active matrix substrate 20).
  • a light shielding portion 225 is formed between the colored portions 223 constituting the color filter.
  • a counter electrode 221 that faces the pixel electrode 236 on the active matrix substrate 230 side is provided on the surface of each coloring portion 223 and the light shielding portion 225.
  • the alignment film and the liquid crystal layer disposed between the active matrix substrate 230 and the CF substrate 220 are not shown.
  • two slits 240a and 240b are formed on the Cs wiring 234 between the pixel electrodes 236 adjacent in the column direction.
  • the two slits 240a and 240b are provided in parallel with the same length along the direction in which the Cs wiring 234 extends.
  • the Cs wiring A short circuit occurs between 234 and the counter electrode 221.
  • the location where the foreign matter G is mixed can be confirmed from the back side of the active matrix substrate 230.
  • intersect the slits 240a and 240b are newly formed so that the foreign material G may be enclosed.
  • the Cs wiring 234s to which the foreign matter G adheres becomes a floating island and is insulated from the surrounding Cs wiring 234, so that a short circuit between the Cs wiring 234 and the counter electrode 221 can be corrected.
  • the new slit 240c can be formed by performing laser trimming from the back side of the active matrix substrate 230 even after the liquid crystal display device is manufactured.
  • the two slits 240a and 240b provided in parallel have the same length. Therefore, it is possible to easily form the two slits 240a and 240b in the manufacturing process of the active matrix substrate 230.
  • FIG. 15 is a back view of the vicinity of the slits 340a and 340b of the active matrix substrate 330 according to the third embodiment.
  • FIG. 16 shows a rear view of the ends of the slits 340a and 340b.
  • FIG. 17 shows a rear view of the ends of the slits 340a and 340b when overetching occurs.
  • the shape of both end portions of the slit is different from that of the second embodiment. Since the other configuration is the same as that of the first embodiment, description of the structure, operation, and effect is omitted.
  • a part obtained by adding the numeral 100 to the reference numeral in FIG. 10 is the same as the part described in the first embodiment.
  • extended slits 340a1 and 340b1 having a width smaller than the width of the slits 340a and 340b extend at both ends of the slits 340a and 340b. Is formed.
  • the slits 340a and 340b are formed by wet etching, a pool of etching liquid may be generated at both ends of the slits 340a and 340b.
  • both ends of the slits 340a and 340b may be excessively etched (overetched) due to the liquid pool, and the two slits 340a and 340b may be connected at the both ends.
  • the Cs wiring 334 surrounded by the slit is insulated from the surrounding Cs wiring 334, and thus an unnecessary portion is generated in the Cs wiring 334.
  • the extended slits 340a1 and 340b1 having a smaller width than the slits 340a and 340b are formed at both ends of the slits 340a and 340b. Even if overetching occurs, there is little spread of etching marks due to overetching. For this reason, it can suppress that the both ends of two slits 340a and 340b are connected.
  • the gate wiring 32 and the Cs wirings 34, 134, 234, and 334 are examples of the “first wiring”.
  • the source wiring 38 is an example of a “second wiring”.
  • the slits 40, 140, 240, and 340 are examples of “through holes”.
  • the gate insulating films 48, 248, and 348 are examples of “insulating films”.
  • the TFT 37 is an example of a “switching element”.
  • the Cs wirings 34, 134, 234, and 334 are examples of “capacitance wiring”.
  • the liquid crystal display device 10 is an example of a “display device”.
  • the backlight device 12 is an example of an “illumination device”.
  • the active matrix substrate configured by the multi-pixel driving method is illustrated, but a normal active matrix substrate (without subpixels) may be used.
  • the configuration in which the through hole is a slit (substantially linear) is illustrated, but the shape of the through hole is not limited.
  • a configuration in which a plurality of circular through holes are formed along the extending direction of the Cs wiring and / or the gate wiring may be employed.
  • Embodiment 2 and Embodiment 3 described above the configuration in which two slits are formed in parallel on the Cs wiring is illustrated, but the number of slits is not limited. The configuration may be such that three or more slits are formed in parallel on the Cs wiring.
  • a television receiver provided with a tuner has been exemplified.
  • the present invention can also be applied to a display device that does not include a tuner.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

Un substrat à matrice active (30) comprend : un substrat transparent à la lumière ; une pluralité d'électrodes de pixels (36) agencées en matrice sur le substrat ; un câblage de grille (32) et un câblage Cs (34) situés sur le substrat ; et un câblage de source situé sur le substrat. Les électrodes de pixels (36) sont agencées du côté de la couche supérieure par rapport au câblage de grille (32) et au câblage Cs (34). Le câblage de grille (32) et le câblage Cs (34) sont au moins disposés entre les électrodes de pixels (36) adjacentes les unes aux autres. Le câblage de source est au moins disposé entre les électrodes de pixels (36) qui sont adjacentes les unes aux autres, qui sont relativement plus étroites que le câblage de grille (32) et le câblage Cs (34) et qui sont disposées de manière à définir une intersection avec le câblage de source. Une fente (40) qui traverse le câblage Cs (34) dans le sens de l'épaisseur est située sur une partie du câblage Cs (34) se trouvant entre les électrodes de pixels adjacentes (36).
PCT/JP2012/053797 2011-02-23 2012-02-17 Substrat à matrice active, dispositif d'affichage et dispositif de réception de télévision WO2012115000A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-037334 2011-02-23
JP2011037334 2011-02-23

Publications (1)

Publication Number Publication Date
WO2012115000A1 true WO2012115000A1 (fr) 2012-08-30

Family

ID=46720781

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/053797 WO2012115000A1 (fr) 2011-02-23 2012-02-17 Substrat à matrice active, dispositif d'affichage et dispositif de réception de télévision

Country Status (1)

Country Link
WO (1) WO2012115000A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05216064A (ja) * 1992-02-05 1993-08-27 Hitachi Ltd アクティブマトリクス液晶表示装置及びその製造方法
JP2002040480A (ja) * 2000-07-24 2002-02-06 Matsushita Electric Ind Co Ltd 液晶表示装置
JP2008287290A (ja) * 2004-12-16 2008-11-27 Sharp Corp アクティブマトリクス基板、表示装置、液晶表示装置およびテレビジョン装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05216064A (ja) * 1992-02-05 1993-08-27 Hitachi Ltd アクティブマトリクス液晶表示装置及びその製造方法
JP2002040480A (ja) * 2000-07-24 2002-02-06 Matsushita Electric Ind Co Ltd 液晶表示装置
JP2008287290A (ja) * 2004-12-16 2008-11-27 Sharp Corp アクティブマトリクス基板、表示装置、液晶表示装置およびテレビジョン装置

Similar Documents

Publication Publication Date Title
US10459301B2 (en) Liquid crystal display device and manufacturing method thereof
KR101791578B1 (ko) 액정 표시 장치
JP7305510B2 (ja) 表示装置及び半導体装置
JP5460123B2 (ja) 液晶表示装置
KR20080072173A (ko) 액정 표시 패널
JP2006259725A (ja) 横電界方式の液晶表示素子及びその製造方法
JP4609525B2 (ja) 液晶表示装置
CN109154750B (zh) 液晶显示装置
KR20110042668A (ko) 표시 장치
KR20150146111A (ko) 액정 표시 장치
US9588380B2 (en) Liquid crystal display device including an auxiliary capacitance line with a branch portion
WO2012090788A1 (fr) Élément d'affichage
KR20130018289A (ko) 어레이 기판, 액정 패널 및 디스플레이 장치
JP6220628B2 (ja) 表示装置
JP7269051B2 (ja) 表示装置
US10890815B2 (en) Display apparatus
KR20130102864A (ko) 네로우 베젤 타입 액정표시장치
JP5373182B2 (ja) 液晶表示パネルおよび液晶表示装置
JP5271021B2 (ja) 液晶表示装置
JP2014186135A (ja) 液晶表示装置
JP5292594B2 (ja) 液晶表示パネル
WO2012115000A1 (fr) Substrat à matrice active, dispositif d'affichage et dispositif de réception de télévision
JP2019086684A (ja) 表示装置
US20150042912A1 (en) Liquid crystal display apparatus
KR20080076317A (ko) 표시 패널

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12749366

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12749366

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP