WO2012055232A1

WO2012055232A1 - Power factor correction circuit and control method

Info

Publication number: WO2012055232A1
Application number: PCT/CN2011/074251
Authority: WO
Inventors: 金亮亮; 罗勇
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-10-26
Filing date: 2011-05-18
Publication date: 2012-05-03
Also published as: CN102457174A

Abstract

A power factor correction (PFC) circuit and a control method are provided. According to the commercial-frequency cycle, controlled switch devices (S1, S2) are controlled to turn on and off. During a positive half cycle of commercial frequency, a first controlled switch device (S1) is turned off and a second controlled switch device (S2) is turned on. During a negative half cycle of commercial frequency, the second controlled switch device (S2) is turned off and the first controlled switch device (S1) is turned on. A main power current loop which is conducted continuously is provided by a low-resistance path of the controlled switch devices (S1, S2). The power factor correction (PFC) circuit and the control method replace slow recovery diodes with controlled switch devices, which eliminates the influence of the junction capacitor effect, decreases the reverse current in every switching cycle significantly, reduces the high-frequency line loss, increases the efficiency of the PFC circuit, improves the electromagnetic interference effect, decreases the number of elements in use, and improves the power density.

Description

Power factor correction circuit and control method

Technical field

The present invention relates to the field of power supply technologies, and in particular, to a power factor correction circuit and a control method.

Background technique

Bridge Voltage Rectifier PFC (Power Factor Correction) circuits are widely used in power supply products. As shown in Figure 1, a typical single-phase PFC circuit diagram is shown. The bridge rectification PFC circuit has three switching devices involved in each switching cycle, and the on-state loss is large. To reduce the on-state loss, a bridgeless PFC circuit can be used. As shown in Figure 2, a schematic diagram of a conventional bridgeless PFC circuit is shown. The bridgeless PFC circuit eliminates the rectifier bridge, and only two switching devices participate in each switching cycle, so the on-state loss is reduced, which has outstanding advantages in terms of efficiency. However, the EMI (Electromagnetic Interference) of the bridgeless PFC circuit shown in Figure 2 has severe interference with common mode noise, resulting in various improved bridgeless PFC circuits.

Current improvements in bridgeless PFC topology efficiency and improved bridgeless PFC topology include the following:

The first, bridgeless PFC diode improvement solution

As shown in Figure 3, a schematic diagram of an EMI-improved diode scheme for a bridgeless PFC circuit is shown. The diode improvement scheme short-circuits the low-voltage side of the DC bus and the commercial power N by serially connecting two slow recovery diodes, thereby reducing the interference of EMI common mode noise, and the circuit topology is as shown in FIG. However, only one boost inductor participates in the PFC operation during each switching cycle, and the other inductor is idle, with low inductance utilization and low power density.

Second, the improvement of the Chinese patent application with the application number CN200510134317 is shown in Fig. 4, which bypasses the EMI noise by respectively connecting a filter capacitor on the mains input N and the low voltage side of the DC bus. This improvement scheme has only one boost inductor in each switching cycle to participate in the PFC operation, the other inductor is idle, the inductor utilization is low, and the power density is low.

Third, the improvement scheme of the Chinese patent application with the application number CN200610088683.6 is shown in FIG. 5, and the characteristics of the fast recovery diode and the slow recovery diode are improved in the patent. EMI, using only one PFC inductor, has a high inductance utilization. However, due to the PN junction capacitance characteristics of the slow recovery diode, its PN junction capacitance effect causes a large reverse current in each switching cycle. This reverse current increases the high frequency loss of the line, which is not conducive to efficiency improvement and EMI. A detrimental effect has occurred, and the further improvement proposed in the patent additionally increases the number of switching devices, which is not conducive to increasing the power density.

Fourth, totem-type bridgeless PFC circuit

As shown in Figure 6, in the totem-type bridgeless PFC circuit, the body diode of the MOS transistor is used as the boost diode of the PFC circuit, which is generally suitable for small power applications in intermittent and critical continuous mode. Totem-type bridgeless PFC circuits use fewer devices and have higher power densities, but are difficult to apply in high-power applications.

In view of these problems in the above improvement scheme, a high efficiency, high power density power factor correction (PFC) circuit and control method are needed for reducing or eliminating high frequency generated by slowly recovering the diode PN junction capacitance characteristics. The reverse current reduces the high frequency loss of the circuit and greatly reduces the on-state loss of the power loop, thereby further improving the efficiency of the bridgeless PFC topology.

Summary of the invention

The technical problem to be solved by the present invention is to provide a power factor correction (PFC) circuit and a control method for reducing high frequency loss and on-state loss of a line, improving efficiency and power density, and improving EMI common mode interference.

In order to solve the above problems, the present invention proposes a power factor correction circuit including a live line (L line) and a neutral line (N line) connected by an inductor (L1) and a main switching device (SW) connected in an alternating current power source. a main switch branch between, a parallel branch consisting of a capacitor (C) and a load (R) in parallel, a first switching device (T1), a second switching device (T2), and a first controllable switching device (S1) And a second controllable switching device (S2); during the positive half cycle of the power frequency, when the main switching device (SW) is turned on, current flows from the live line (L line) through the inductor (L1), The main switching device (SW) returns to the neutral line (N line); when the main switching device (SW) is turned off, the inductor (L1), the first switching device (T1), The parallel branch and the second controllable switching device (S2) are sequentially connected in series to form a positive half cycle path, and the positive half cycle path is connected between the live line (L line) and the neutral line (N line); During the negative half cycle of the power frequency, when the main switching device (SW) is turned on, current is returned from the neutral line (N line) to the live line (L line) via the main switching device (SW) and the inductor (L1). When the main switching device (SW) is turned off, the first controllable switching device (S1), the parallel branch, the second switching device (T2), and the inductor (L1) And sequentially forming a negative half cycle path in series, the negative half cycle path being connected between the live line (L line) and the neutral line (N line).

Preferably, the switching frequency of the first controllable switching device (S1) and the second controllable switching device (S2) is a mains frequency.

Preferably, if the mains input is in the positive half cycle of the power frequency, the second controllable switching device (S2) is turned on, and the first controllable switching device (S1) is turned off.

Preferably, if the mains input is in the positive half cycle of the power frequency, the second controllable switching device (S2) is turned on, then the first switching device (T1) is in a pulse width modulation (PWM) state, the second The switching device (T2) is turned off.

Preferably, if the mains input is at a negative frequency of the power frequency, the first controllable switching device (S1) is turned on, and the second controllable switching device (S2) is turned off.

Preferably, if the mains input is in the negative half cycle of the power frequency, the first controllable switching device (S1) is turned on, then the second switching device (T2) is in a pulse width modulation (PWM) state, the first switching device (T1) is off.

Preferably, the first switching device (T1) and the second switching device (T2) are uncontrollable switching devices or controllable switching devices.

Preferably, the main switching device (SW) is a combination of a controllable switching device or a controllable switching device.

The invention also provides a control method of a power factor correction circuit, comprising:

Determining, according to the mains detection signal, that the mains input is in the positive half cycle of the power frequency or the negative half cycle of the power frequency; driving the second controllable switching device (S2) to be turned on in the positive half cycle of the power frequency, the first controllable switching device ( S1) closed;

The first controllable switching device (S1) is turned on during a negative half cycle of the power frequency, and the second controllable switching device (S2) is turned off. Preferably, if the mains input is in the positive half cycle of the power frequency, the second controllable switching device (S2) is turned on, then the first switching device (T1) is in a pulse width modulation (PWM) state, the second The switching device (T2) is turned off; if the mains input is in the negative half cycle of the power frequency, the first controllable switching device (S1) is turned on, then the second switching device (T2) is in a pulse width modulation (PWM) state. The first switching device (T1) is turned off.

The power factor correction (PFC) circuit of the present invention provides a continuously conducting main power current path by using a low impedance path of the controllable switching device S1 or S2, reducing or eliminating high frequency generated by slowly recovering the PN junction capacitance characteristic of the diode Reverse current reduces the high frequency loss of the circuit and greatly reduces the on-state loss of the power loop, thereby further improving the efficiency of the bridgeless PFC topology. This power factor correction (PFC) circuit also overcomes the traditional bridgeless PFC. Topological EMI common mode noise interference is serious, and the same EMI improvement effect as the prior art can be maintained, while reducing the number of components used and increasing the rate density. BRIEF abstract

1 is a schematic diagram of a typical single-phase PFC circuit of the prior art;

2 is a schematic diagram of a conventional bridgeless PFC circuit of the prior art;

3 is a schematic diagram of a prior art scheme for adding an EMI improving diode to a bridgeless PFC circuit; FIG. 4 is a schematic diagram of an improvement of the patent CN200510134317;

Figure 5 is a schematic diagram of an improvement scheme of the patent CN200610088683.6;

6 is a schematic diagram of a prior art totem-type bridgeless PFC circuit;

Figure 7 is a schematic diagram showing the principle of a power factor correction (PFC) circuit of the present invention;

Figure 8 is a schematic view of a first embodiment of the present invention;

9 is a schematic diagram of a control method for the specific embodiment of FIG. 8;

Figure 10 is a schematic view of a second embodiment of the present invention;

Figure 11 is a schematic diagram of a control method for the embodiment of Figure 10. Preferred embodiment of the invention

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings.

In view of the problems existing in existing bridgeless PFC circuits, the present invention proposes a high efficiency, high power density power factor correction (PFC) circuit and control method, which provides continuous use of a low impedance path of the controllable switching device S1 or S2. The turned-on main power current loop reduces or eliminates the high-frequency reverse current generated by the slow recovery diode PN junction capacitance characteristic, reduces the high-frequency loss of the circuit, and greatly reduces the on-state loss of the power loop, thereby further Increased efficiency of bridgeless PFC topologies. At the same time, this circuit also overcomes the serious problem of the traditional bridgeless PFC topology EMI common mode noise interference, while maintaining the same EMI improvement effect as the prior art, the number of components used is reduced, and the rate density is increased.

The principle of the bridgeless PFC circuit of the present invention is as shown in FIG. 7. In the bridgeless PFC circuit, the inductor L1 and the main switching device SW are connected in series to form a main switch branch, and the main switch branch is connected to the AC power supply. Between the live line (L line) and the zero line (N line). In the bridgeless PFC circuit, a parallel branch is formed by capacitor C and load R in parallel.

During the positive half cycle of the power frequency, when the main switching device SW is turned on, the current is returned to the N line by the L line through the inductor L1 and the main switching device SW. When the main switching device SW is turned off, the inductor L1, the first switching device T1, the parallel branch, and the second controllable switching device S2 are sequentially connected in series to form a positive half cycle path, and the positive half cycle path is connected to the live line (L line) and Between the zero line (Ν line).

In the negative half cycle of the power frequency, when the main switching device SW is turned on, the current is returned to the L line by the main switching device (SW) and the inductor (L1); when the main switching device SW is turned off, the first controllable switch is turned on. The device S1, the parallel branch, the second switching device T2, and the inductor L1 are sequentially connected in series to form a negative half-cycle path, and the negative half-cycle path is connected between the live line (L line) and the neutral line (the line).

For the PFC circuit of the present invention, the control method is based on the mains detection signal, determining that the mains input is in the positive half cycle or the negative half cycle of the power frequency, and the power frequency positive half cycle drives S2 to conduct, S1 is closed; the power frequency negative half cycle drives the S1 lead Pass, S2 is closed, to realize the synchronous control of the S1 and S2 driving and the city electrician frequency positive and negative half cycle switching; at the same time, the PFC circuit main switch branch SW is driven by the PWM signal to ensure the normal operation of the PFC circuit.

The following is an example of the operation of the power frequency in the positive half cycle as an example to illustrate the control method of the circuit, in the main switch When the device SW is turned on, the current flows out from the L line, and returns to the N line through the inductor L1 and the main switching device SW; when the main switching device SW is turned off, the current flows out through the L line, passes through the inductor L1, and the first switching device T1 The parallel branch consisting of capacitor C and load R and the second controllable switching device S2 are returned to the N line. At this time, the first controllable switching device S1 is turned off, and the second controllable switching device S2 is turned on. In the same way, the working process of the negative frequency of the power frequency can be analyzed.

The switching frequency of the first controllable switching device S1 and the second controllable switching device S2 is a mains frequency, which can be determined according to the mains detection signal that the mains input is in the positive half cycle or the negative half cycle of the power frequency. When the mains is in the positive half of the power frequency, the S2 is turned on, and S1 is turned off. If the mains is in the negative half of the power frequency, the drive S1 is turned on, and S2 is turned off, so that the driving of S1 and S2 is synchronized with the positive and negative half-cycle of the electrician. . Since the switching frequency of the controllable switching devices S1 and S2 is the mains frequency, the PFC circuit has the characteristics of simple control and high reliability.

The first switching device T1 and the second switching device T2 may be uncontrollable switching devices, such as diodes, or may be controllable switching devices, such as metal oxide semiconductor field effect transistor MOSFETs and insulated gate bipolar transistor IGBTs.

Wherein, the main switching device SW is a controllable switching device or a combination of controllable switching devices, and the pulse width modulation PWM signal can be used to drive the PFC circuit main switch branch SW to ensure the normal operation of the PFC circuit. Wherein, the first controllable switching device S1 and the second controllable switching device S2 are in a positive and negative half cycle of the power frequency, one is turned on and the other is turned off, so that continuous conduction can be respectively provided in the positive and negative half cycles of the power frequency. The path, short-circuiting the DC bus side with the mains input side, improves the effect of the bridgeless PFC topology EMI.

The PFC circuit of the present invention utilizes controllable switching devices S1 and S2 to provide a continuously conducting power current path, reducing high frequency and on-state losses of the line, reducing component count, and reducing EMI interference. The low impedance path of the controllable switching devices S1 and S2 provides a continuously conducting power current loop that reduces or eliminates the high frequency reverse current generated by the slow recovery diode PN junction capacitance characteristic, reducing the high frequency loss of the power loop while reducing The on-state loss of the main power loop improves the efficiency of the bridgeless PFC. Under the premise of the same EMI improvement level, the number of devices used is reduced, which is beneficial to the improvement of the power density of the bridgeless PFC topology. As shown in FIG. 8, a schematic diagram of a first embodiment of the present invention is shown. The first switching device T1 and the second switching device T2 are diodes D1 and D2, wherein D1 and D2 can use a fast recovery diode or the like. Figure 9 is a schematic diagram of a control method corresponding to the embodiment of Figure 8. The following briefly describes the circuit and control method of the specific embodiment.

In the embodiment shown in Fig. 8, the working frequency of the power frequency is positive and negative for half a week, and the positive half cycle of the power frequency is taken as an example for analysis. In the circuit shown in FIG. 8, when the controllable switching device SW is turned on, current flows from the L line, passes through the PFC inductor L1 and the controllable switching device SW, and returns to the N line; when the controllable switching device SW is turned off, The current flows out of the L line, passes through the parallel branch of the PFC inductor L1, the diode D1, the capacitor C and the load R, and then passes through the controllable switching device S2 to return to the N line. During this process, the controllable switching device S1 is turned off. The control switching device S2 is turned on. In the same way, the working process of the negative frequency of the power frequency can be analyzed.

Since S2 is in a continuous conduction state during the positive half cycle of the power frequency (the S1 is in a continuous conduction state during the negative half cycle of the power frequency), the current path is always present, and the DC bus side is eliminated relative to the N line through the continuous path provided by the controllable switching device S2. The high frequency potential floats to improve EMI common mode interference; since the device characteristics of the controllable switching devices S1 and S2 are different from the slow recovery diodes, there is no equivalent junction capacitance effect of the slow recovery diode, thus reducing or eliminating each The reverse current generated by the slow recovery of the diode during the switching cycle reduces the high frequency loss and reduces the large on-state loss due to the slow recovery diode, which improves the efficiency of the bridgeless PFC. When the same EMI improvement effect is maintained, the number of components is reduced, which contributes to an increase in power density.

Figure 10 is a schematic view of a second embodiment of the present invention in which T1 and T2 are controlled switch devices, which may be MOSFETs and IGBTs. Figure 11 is a schematic diagram of a control method corresponding to the embodiment shown in Figure 10. The following briefly describes the circuit and control method of the specific embodiment.

In the embodiment shown in FIG. 10, the working frequency of the power frequency is positive and negative, and the power frequency is positive half cycle as an example. In the circuit shown in FIG. 10, when the controllable switching device SW is turned on, current flows from the L line, passes through the PFC inductor L1 and the controllable switching device SW, and returns to the N line; when the controllable switching device SW is turned off, The current flows out of the L line, passes through the parallel branch of the PFC inductor L1, the controllable switching device Tl, the capacitor C and the load R, and then passes through the controllable switching device S2 to return to the twist line. In this process, the controllable switching device S1 When turned off, the controllable switching device S2 is turned on. In the same way, the working process of the negative frequency of the power frequency can be analyzed. Since S2 is in a continuous conduction state during the positive half cycle of the power frequency (the S1 is in a continuous conduction state during the negative half cycle of the power frequency), the current path is always present, and the DC bus side is eliminated relative to the N line through the continuous path provided by the controllable switching device S2. The high frequency potential floats to improve EMI common mode interference; since the device characteristics of the controllable switching devices S1 and S2 are different from the slow recovery diodes, there is no equivalent junction capacitance effect of the slow recovery diode, thus reducing or eliminating each The reverse current generated by the slow recovery of the diode during the switching cycle reduces the high frequency loss and reduces the large on-state loss due to the slow recovery diode, which improves the efficiency of the bridgeless PFC circuit. Control switching devices T1 and T2, by controlling the device to turn on, using its low-impedance body instead of the original high-on-voltage drop diode path, may further improve the efficiency of the bridgeless PFC circuit; while maintaining the same EMI improvement effect as the prior art , reducing the number of devices, which is conducive to power density increase.

The main switching device SW involved in the present invention may be any controllable semiconductor switching device such as a metal oxide semiconductor field effect transistor MOSFET, an insulated gate bipolar transistor IGBT, or the like, or various combinations of controllable semiconductor switching devices. The drive control signal of the switch is generated by the peripheral control circuit.

One of ordinary skill in the art will appreciate that all or a portion of the above steps may be accomplished by a program instructing the associated hardware, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above embodiment may be implemented in the form of hardware or in the form of a software function module. The invention is not limited to any specific form of combination of hardware and software.

The above is only the embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. All modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the appended claims.

Industrial applicability

The power factor correction (PFC) circuit and the control method provided by the invention provide a continuously conducting main power current loop through a low impedance path of the controllable switching device S1 or S2, eliminating high frequency potential floating of the DC bus side relative to the N line , thereby improving EMI common mode interference; using controllable switching devices For the slow recovery diode, the effect of the junction capacitance effect is eliminated, the reverse current of each switching cycle is significantly reduced, the P strip reduces the high frequency loss of the line, and the efficiency of the PFC circuit is improved; the invention also reduces the used element The number of components increases efficiency and power density.

Claims

Claim

1. A power factor correction circuit comprising a main switch branch connected between a live line (L line) and a neutral line (N line) of an alternating current power source, consisting of an inductor (L1) and a main switching device (SW) connected in series a parallel branch, a first switching device (T1), a second switching device Device (S2); during the positive half cycle of the power frequency, when the main switching device (SW) is turned on, current flows from the live line (L line) through the inductor (L1), the main switching device (SW) Returning to the neutral line (Ν line); when the main switching device (SW) is turned off, by the inductor (L1), the first switching device (T1), the parallel branch and the The second controllable switching device (S2) is sequentially connected in series to form a positive half cycle path, the positive half cycle path being connected between the live line (L line) and the zero line (twist line); When the main switching device (SW) is turned on, current flows from the neutral line (Ν line) through the main switching device (SW), inductor (L1) Returning to the live line (L line); when the main switching device (SW) is turned off, by the first controllable switching device (S1), the parallel branch, the second switching device ( Τ2) and the inductor (L1) are sequentially connected in series to form a negative half-cycle path, and the negative half-cycle path is connected between the live line (L line) and the neutral line (Ν line).

2. The power factor correction circuit of claim 1 wherein:

The switching frequency of the first controllable switching device (S1) and the second controllable switching device (S2) is a mains frequency.

3. The power factor correction circuit of claim 2, wherein:

If the mains input is in the positive half cycle of the power frequency, the second controllable switching device (S2) is turned on, and the first controllable switching device (S1) is turned off.

4. The power factor correction circuit of claim 3, wherein:

If the mains input is in the positive half cycle of the power frequency, and the second controllable switching device (S2) is turned on, the first switching device (T1) is in a pulse width modulation (PWM) state, and the second switching device ( Τ 2 ) Close.

5. The power factor correction circuit of claim 2, wherein:

If the mains input is at a negative frequency of the power frequency, the first controllable switching device (S1) is turned on, and the second controllable switching device (S2) is turned off.

6. The power factor correction circuit of claim 5, wherein:

If the mains input is at a negative frequency of the power frequency, the first controllable switching device (S1) is turned on, then the second switching device (T2) is in a pulse width modulation (PWM) state, and the first switching device (T1) shut down.

7. The power factor correction circuit of claim 1 wherein:

The first switching device (T1) and the second switching device (T2) are uncontrollable switching devices or controllable switching devices.

8. The power factor correction circuit of claim 1 wherein:

The main switching device (SW) is a combination of a controllable switching device or a controllable switching device.

9. A control method for a power factor correction circuit according to claim 1, comprising: determining, according to a mains detection signal, that the mains input is at a power frequency positive half cycle or a power frequency negative half cycle; and driving the second at a power frequency positive half cycle The controllable switching device (S2) is turned on, and the first controllable switching device (S1) is turned off;

The first controllable switching device (S1) is turned on during a negative half cycle of the power frequency, and the second controllable switching device (S2) is turned off.

10. The control method according to claim 9, wherein:

If the mains input is in the positive half cycle of the power frequency, and the second controllable switching device (S2) is turned on, the first switching device (T1) is in a pulse width modulation (PWM) state, and the second switching device ( T2) off;

If the mains input is at a negative frequency of the power frequency, the first controllable switching device (S1) is turned on, then the second switching device (T2) is in a pulse width modulation (PWM) state, and the first switching device ( T1) is off.