WO2011000262A1

WO2011000262A1 - Non-bridge power factor correcting circuit and control method thereof

Info

Publication number: WO2011000262A1
Application number: PCT/CN2010/073983
Authority: WO
Inventors: 金亮亮; 戴彬传
Original assignee: 中兴通讯股份有限公司
Priority date: 2009-07-03
Filing date: 2010-06-13
Publication date: 2011-01-06
Also published as: CN101599695A

Abstract

The present invention provides a non-bridge power factor correcting circuit and a control method thereof. The circuit comprises a first inductor, a second inductor, a first diode, a second diode, a parallel branch of a load and a capacitor, a first controllable switching element, a second controllable switching element, a third controllable switching element, a fourth controllable switching element and a control unit, wherein the control unit controls on and off operation of the third and the fourth controllable switching element, so as to implement the switching thereof to be synchronous with the switching of positive and negative half cycle of a commercial electricity power frequency. The present invention can further improve the efficiency of the non-bridge power factor correcting circuit and reduce common-mode noise from electromagnetic interference of the non-bridge power factor correcting circuit.

Description

Bridgeless power factor correction circuit and control method thereof

The invention relates to the field of electronic automation, in particular to a bridgeless power factor correction (PFC) circuit and a control method thereof. Background technique

With energy shortages and environmental degradation, the efficiency requirements for power products are increasing. Since the bridgeless PFC circuit in the power supply product eliminates the rectifier bridge, only two switching tubes participate in the operation in each switching cycle, and the on-state loss is low, which has outstanding advantages in improving efficiency, as shown in FIG. Bridgeless PFC circuit. However, the common mode noise of EMI (Electromagnetic Interference) of the conventional bridgeless PFC circuit shown in FIG. 1 is serious. Therefore, various improved bridgeless PFC circuits and their control methods have emerged for improvement. The EMI common mode noise of the bridge PFC circuit further improves the efficiency of the bridgeless PFC circuit.

In order to improve the efficiency of the bridgeless PFC circuit and improve the EMI common mode noise of the bridgeless PFC circuit, the prior art provides the following three solutions:

The first type, as shown in Figure 2, the bridgeless PFC circuit, in Figure 2, according to the signal of the mains detection line, the mains is the power frequency positive half cycle or the power frequency negative half cycle, in the positive half cycle of the power frequency, the metal oxide semiconductor (MOS, Metal Oxid Semiconductor) The tube SI is in the PWM (Pulse Width Modulation) state, the MOS transistor S2 is in the on state, and the S2 body diode is replaced by the MOS tube S2 channel; in the negative half cycle of the power frequency, the MOS tube S2 is in the PWM state, and the MOS transistor S1 is in an on state, and the S1 body diode is replaced by the MOSFET S1 channel. The PWM state means that the switching device is turned on and off multiple times in half a power frequency cycle. Since the DC on-resistance RDS(on) of the MOS tube channel is small, the on-state loss of the power current loop is reduced, and the efficiency of the bridgeless PFC circuit is improved. In the first scheme, although the efficiency of the bridgeless PFC circuit can be improved, the common mode noise of the bridgeless PFC circuit is severe, and it is difficult to achieve productization.

Second, as shown in Figure 3, the bridgeless PFC circuit is short-circuited between the low-voltage side of the bus and the mains input L and N lines by connecting two diodes D3 and D4 in series to reduce the EMI common mode noise. . Since the working frequency of the power-frequency positive and negative half-cycle of the bridgeless PFC circuit is symmetrical, the positive half cycle of the power frequency is taken as an example for analysis, and the switches S1 and S2 are synchronously driven. When the switch S1 is turned on, the inductor L1, the switch S1, the diode D4 and the Z21 are connected in parallel to form a power current loop, wherein Z21 is a series branch of the switch S2 channel and the inductor L2; when the switch S1 is turned off, the inductor L1 and the diode Dl, capacitor C and load R, diode D4 and Z22 are connected in parallel to form a power current loop, wherein Z22 is a series branch of the S2 body diode and the inductor L2. Since diode D4 uses a common rectifier diode, the on-state voltage drop is large, and the on-state voltage drop of diode D4 in parallel with Z21 or Z22 is equal to the on-state voltage drop of diode D4, so the on-state loss of this power current loop is large.

In the second scheme, although the EMI common mode noise can be reduced, the efficiency improvement of the bridgeless PFC circuit is not significant.

The third, the bridgeless PFC circuit shown in Figure 4, is input through the mains! ^, N line and the common side of the low voltage side of the bus are respectively connected with a filter capacitor to bypass EMI common mode noise. Since the bridgeless PFC circuit shown in FIG. 4 is symmetric in the positive and negative half cycle of the power frequency, the positive half cycle of the power frequency is taken as an example for analysis, and the high frequency components of the inductor current all flow through the capacitor C2, because the amplitude is small, the capacitance is The loss caused by C2 is small; the inductor current power frequency component flows all the way through the switch S2 and the inductor L2 series branch. This current component not only generates the on-state loss in the switch S2, but also generates the on-state loss in the inductor L2. The on-state loss of such a bridgeless PFC circuit is large, and the efficiency improvement of the bridgeless PFC circuit is not obvious.

In the third scheme, although the EMI common mode noise of the bridgeless PFC circuit can be reduced, the efficiency improvement of the bridgeless PFC circuit is not significant. Summary of the invention

The technical problem to be solved by the present invention is to provide a bridgeless PFC circuit and a control method thereof, which solve the problems of low efficiency and serious EMI common mode noise of the existing bridgeless PFC circuit.

In order to solve the above problems, the present invention provides a bridgeless PFC circuit and a control method thereof, and the specific technical solutions are as follows:

A bridgeless power factor correction circuit comprising:

a first inductor having a first end connected to the live input;

a second inductor having a first end connected to the neutral input;

a first diode having an anode connected to the second end of the first inductor;

a second diode having an anode connected to the second end of the second inductor;

a parallel branch of the load and the capacitor, the high voltage side end of which is connected to the cathode of the first diode and the second diode;

a first controllable switching device having a first end connected to an anode of the first diode and a second end connected to a low voltage side end of the parallel branch of the load and the capacitor;

a second controllable switching device having a first end connected to an anode of the second diode and a second end connected to a low voltage side end of the parallel branch of the load and the capacitor;

a third controllable switching device having a first end connected to the first end of the first inductor and a second end connected to the low voltage side end of the parallel branch of the load and the capacitor;

a fourth controllable switching device having a first end connected to the first end of the second inductor and a second end connected to the low voltage side end of the parallel branch of the load and the capacitor;

a control unit having a first input connected to the live input, a second input coupled to the neutral input, and a first output coupled to the third end of the first controllable switching device, the second The output end is connected to the third end of the second controllable switching device, the third output end is connected to the third end of the third controllable switching device, and the fourth output end is connected to the fourth controllable switching device a third end; or, a first input end thereof is connected to the hot line input end, and a second input end is connected to the a zero line input end, the first output end of which is connected to the third end of the first controllable switching device and the second controllable switching device, and the second output end of which is connected to the third end of the third controllable switching device The third output end is connected to the third end of the fourth controllable switching device;

The control unit is configured to control off and on of the third controllable switching device and the fourth controllable switching device, to achieve the turn-off and conduction and the electrician frequency negative and negative half cycle Switch sync.

Preferably, the third controllable switching device and the fourth controllable switching device are metal oxide semiconductor (MOS) tubes; the first end of the MOS transistor is a drain, and the second end is a source, The three ends are the gates.

Preferably, the third controllable switching device and the fourth controllable switching device are insulated gate bipolar crystal (IGBT) tubes; the first end of the IGBT tube is a collector, and the second end is a emission set The third end is the gate.

Preferably, the third controllable switching device and the fourth controllable switching device are relays; the first end of the relay is a first power contact, the second end is a second power contact, and the third end A control circuit for driving the coil.

Preferably, the first controllable switching device and the second controllable switching device are MOS transistors, or IGBT tubes each having a body diode, or IGBT tubes each having no body diode.

A control method for a bridgeless power factor correction circuit, comprising:

Connecting the first end of the first inductor to the live input, and connecting the first end of the second inductor to the neutral input;

Connecting the anode of the first diode to the second end of the first inductor, and connecting the anode of the second diode to the second end of the second inductor;

Connecting a high voltage side end of the parallel branch of the load and the capacitor to the cathode of the first diode and the second diode;

Connecting the first end of the first controllable switching device to the anode of the first diode, the second end Connecting the low voltage side end of the parallel branch of the load and the capacitor;

Connecting a first end of the second controllable switching device to an anode of the second diode, and connecting a second end to a low voltage side end of the parallel branch of the load and the capacitor;

Connecting a first end of the third controllable switching device to the first end of the first inductor, and a second end connecting the low voltage side end of the parallel branch of the load and the capacitor;

Connecting a first end of the fourth controllable switching device to the first end of the second inductor, and a second end connecting the low voltage side end of the parallel branch of the load and the capacitor;

a first input end of the control unit is connected to the live line input end, a second input end is connected to the zero line input end, and a first output end is connected to the third end of the first controllable switch device, and the second output end Connecting a third end of the second controllable switching device, the third output is connected to the third end of the third controllable switching device, and the fourth output is connected to the third end of the fourth controllable switching device; The control unit controls the turn-off and conduction of the third controllable switching device and the fourth controllable switching device to achieve synchronization of the turn-off and conduction with the switching of the positive and negative half cycles of the electrician.

Preferably, the controlling unit controls the turning off and conducting of the third controllable switching device and the fourth controllable switching device to be:

The control unit controls the third controllable switching device to be in an off state and the fourth controllable switching device to be in an on state during a positive half cycle of the power frequency; switching from a positive half cycle of the power frequency to a negative half cycle of the power frequency a dead time period preset by the control unit at a zero crossing of the mains; controlling the third controllable switching device to be in an on state during the negative half cycle of the power frequency, and the fourth controllable switching device is in a off state In the off state, the turn-off and conduction of the third controllable switching device and the fourth controllable switching device are synchronized with the switching of the positive and negative half cycles of the electrician.

Preferably, the first controllable switching device and the second controllable switching device are both MOS transistors or IGBT tubes each having a body diode, the method further comprising:

The control unit controls the first controllable switching device and the second controllable switching device to be in a pulse width modulation (PWM) state during positive and negative half cycles of the power frequency; or to control the first half of the power frequency a controllable switching device is in a PWM state, the second controllable switching device is in an on state; and in the negative half cycle of the power frequency, controlling the first controllable switching device to be in an on state, the second controllable switching device In the PWM state; or in the positive half cycle of the power frequency, controlling the first controllable switching device to be in a PWM state, the second controllable switching device is in an off state; controlling the first controllable in a negative half cycle of the power frequency The switching device is in an off state, and the second controllable switching device is in a PWM state.

Preferably, the first controllable switching device and the second controllable switching device are IGBT tubes without a body diode, the method further comprising:

The control unit controls, in the positive half cycle of the power frequency, that the first controllable switching device is in a PWM state, and the second controllable switching device is in an off state; in the negative half cycle of the power frequency, controlling the The first controllable switching device is in an off state, the second controllable switching device is in a PWM state; or in the positive half cycle of the power frequency, controlling the first controllable switching device to be in a PWM state, the second controllable switch The device is in an on state; in the negative half cycle of the power frequency, the first controllable switching device is controlled to be in an on state, and the second controllable switching device is in a PWM state.

A control method for a bridgeless power factor correction circuit, comprising:

Connecting a first end of the first controllable switching device to an anode of the first diode, and a second end connecting a low voltage side end of the parallel branch of the load and the capacitor;

Connecting a first end of the second controllable switching device to the anode of the second diode, and a second end connecting the low voltage side end of the parallel branch of the load and the capacitor; Connecting a first end of the third controllable switching device to the first end of the first inductor, and a second end connecting the low voltage side end of the parallel branch of the load and the capacitor;

Connecting a first input end of the control unit to the hot line input end, a second input end connecting the zero line input end, the first output end connecting the first controllable switch device and the second controllable switch device a third end, the second output is connected to the third end of the third controllable switching device, and the third output is connected to the third end of the fourth controllable switching device;

The control unit controls the turn-off and conduction of the third controllable switching device and the fourth controllable switching device to achieve the switching synchronization between the turn-off and the turn-on and the city electrical frequency positive and negative half cycle.

Preferably, the first controllable switching device and the second controllable switching device are both IGBT tubes with body diodes or both MOS tubes, and the method further includes:

The control unit controls the first controllable switching device and the second controllable switching device to be in a PWM state during the positive and negative half cycles of the power frequency.

The technical solution provided by the invention replaces the diode with high on-voltage drop in the bridgeless PFC circuit in the prior art scheme 2 by using the controllable switching device with low on-resistance, thereby reducing the on-state loss of the bridgeless PFC circuit, further Improve the efficiency of bridgeless PFC circuits. At the same time, due to the low busbar A controllable switching device is introduced between the pressure side and the mains input N line, bypassing the EMI common mode noise, so that the potential of the low voltage side of the busbar relative to the N line does not float with the switching frequency, thereby improving the EMI of the bridgeless PFC circuit. Modular noise makes it easier to implement a productized application with higher practical value. DRAWINGS

1 is a structural diagram of a conventional bridgeless PFC circuit;

2 is a structural diagram of a bridgeless PFC circuit provided by the prior art;

3 is a structural diagram of a bridgeless PFC circuit provided by the prior art;

4 is a structural diagram of a bridgeless PFC circuit provided by the prior art;

5 is a schematic diagram of a schematic diagram of a bridgeless PFC circuit according to an embodiment of the present invention; FIG. 6 is a structural diagram of a bridgeless PFC circuit according to an embodiment of the present invention;

7 is a structural diagram of a bridgeless PFC circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another schematic diagram of a bridgeless PFC circuit according to an embodiment of the present invention; FIG. 9 is a flowchart of a method for controlling a bridgeless PFC circuit according to an embodiment of the present invention. detailed description

The core idea of the present invention is that a controllable switching device with a low on-resistance is selected, and the controllable switching device has a high conductivity in the bridgeless PFC circuit of the prior art scheme 2 because the corresponding conduction voltage drop is low. The diode with voltage drop can reduce the on-state loss of the bridgeless PFC circuit and further improve the efficiency of the bridgeless PFC circuit. At the same time, since the controllable switching device is introduced between the low voltage side of the busbar and the mains input L and N lines, the EMI common mode noise is bypassed, so that the potential of the low voltage side of the busbar relative to the N line does not float with the switching frequency, thereby improving The EMI common mode noise of the bridgeless PFC circuit makes it easier to implement the product application and has higher practical value. In addition, since the switching frequency of the controllable switching device is the mains frequency, the dead time setting is flexible and the product reliability is high.

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

FIG. 5 is a schematic diagram of a bridgeless PFC circuit according to a first embodiment of the present invention. Schematic diagram, including:

The inductor L1 has a first end connected to the live input terminal;

Inductor L2, the first end of which is connected to the neutral input;

a diode D1 having an anode connected to the second end of the inductor L1;

a diode D2 having an anode connected to the second end of the inductor L2;

The load R forms a parallel branch with the capacitor C, and the high voltage side end of the parallel branch is connected to the cathode of the diode D1 and the diode D2;

The switch S1 is a first controllable switching device, the first end of which is connected to the anode of the diode D1, and the second end of which is connected to the low-voltage side end of the branch R of the load R and the capacitor C;

The switch S2 is a second controllable switching device, the first end of which is connected to the anode of the diode D2, and the second end of which is connected to the low-voltage side end of the branch R of the load R and the capacitor C;

The switch S3 is a third controllable switching device, the first end of which is connected to the first end of the inductor L1, and the second end thereof is connected to the low-voltage side end of the branch R of the load R and the capacitor C;

The switch S4 is a fourth controllable switching device, the first end of which is connected to the first end of the inductor L2, and the second end of which is connected to the low-voltage side end of the parallel connection of the load R and the capacitor C;

a control unit, the first input end of which is connected to the live line input end, the second input end of which is connected to the neutral line input end, the first output end of which is connected to the third end of the switch S1, and the second output end is connected to the third end of the switch S2, The third output end is connected to the third end of the switch S3, and the fourth output end of the switch S4 is connected to the control unit of the switch S4 to control the off and on of the switch S3 and the switch S4, so as to achieve the turn-off and conduction and the electrician of the city Negative half-cycle switching synchronization.

Further, the control unit is in the positive half cycle of the power frequency, the control switch S3 is in the off state, and the switch S4 is in the on state; when switching from the positive half cycle of the power frequency to the negative half cycle of the power frequency, the power supply zero crossing point is passed through the control unit in advance. Set a dead time; in the negative half cycle of the power frequency, the control switch S3 is in the on state, and the switch S4 is in the off state, so as to realize the switching off and conduction of the switch S3 and the switch S4 Synchronized with the switching of the city's electrician's frequency for half a week.

Optionally, the switch S3 and the switch S4 may be a MOS transistor; wherein the first end of the MOS transistor is a drain, the second end is a source, and the third end is a gate.

Optionally, the switch S3 and the switch S4 may be an IGBT (Insulated Gate Bipolar Transistor) tube; wherein, the first end of the IGBT tube is a collector, the second end is an emitter, and the third end is Gate.

Alternatively, the switch S3 and the switch S4 may be relays; wherein the first end of the relay is a first power contact, the second end is a second power contact, and the third end is a control circuit for driving the coil.

Further, the switch S1 and the switch S2 may be a MOS tube or an IGBT tube, and the IGBT tube is divided into an IGBT tube with a body diode or an IGBT tube with no body diode:

When the switch S1 and the switch S2 are MOS tubes or IGBT tubes with body diodes, the control unit is in the positive and negative half cycles of the power frequency, and the control switch S1 and the switch S2 are both in the PWM state; or the control unit is in the positive half cycle of the power frequency control switch S1 PWM state, switch S2 is in the on state; in the negative half cycle of the power frequency, the control switch S1 is in the on state, the switch S2 is in the PWM state; or the control unit is in the PWM state in the positive half cycle of the power frequency, the switch S2 is in the off state State; In the negative half cycle of the power frequency, the control switch S1 is in the off state, and the switch S2 is in the PWM state.

When the switch S1 and the switch S2 are IGBT tubes without a body diode, the control unit controls the switch S1 to be in the PWM state and the switch S2 is in the off state during the positive half cycle of the power frequency; when the power frequency is negative half cycle, the control switch S1 In the off state, the switch S2 is in the PWM state; or the control unit controls the switch S1 to be in the PWM state during the positive half cycle of the power frequency, and the switch S2 is in the on state; in the negative half cycle of the power frequency, the control switch S1 is in the on state, and the switch S2 is in the PWM status.

Next, a structural diagram of the bridgeless PFC circuit shown in Fig. 6 is taken as a second embodiment of the present invention, and Fig. 5 will be described in detail. In Fig. 6, the switch S1, the switch S2, the switch S3, and the switch S4 are MOS tubes. It should be noted that the switches S3 and S4 may also be IGBT tubes or relays, and the specific working process and the switch S1, the switch S2, the switch S3 and the switch 84 are the working processes of the MOS tube. Similar, it will not be repeated here. Since the working frequency of the power frequency is positive and negative, the working process is symmetrical. Therefore, the positive half cycle of the power frequency is taken as an example for detailed description. At this time, it can be divided into three cases:

First, switches S1 and S2 are in the PWM state. In Figure 6, the control unit puts switch S3 in the off state and switch S4 in the on state. In this case, there are two cases:

(1) The switches S1 and S2 are simultaneously in the on state. At this time, the current passes through the live input terminal, the inductor L1 and the switch S1, and is divided into two paths after the switch S1, one through the switch S2 channel, the inductor L2 to the neutral line At the input, the other channel is channeled to the zero line input via switch S4.

(2) The switches S1 and S2 are simultaneously in the off state. At this time, the current passes through the parallel input of the live input terminal, the inductor L1, the diode D1, the capacitor C and the load R, and is in parallel via the capacitor C and the load R. After splitting into two ways, one way through the switch S2 body diode, the inductor L2 to the zero line input, the other through the switch S4 channel to the zero line input.

Second, the switch S1 is in the PWM state, and the switch S2 is in the on state. At this time, as shown in FIG. 6, it can be divided into two cases:

(2) Switch S1 is in the off state, and switch S2 is in the on state. At this time, the current passes through the parallel input of the live input terminal, the inductor L1, the diode D1, the capacitor C and the load R, and is in the capacitor C and the load R. After the parallel branch is divided into two paths, one through the switch S2 channel, the inductor L2 to the zero line input, and the other through the switch S4 channel to the zero line input.

Third, the switch S1 is in the PWM state, and the switch S2 is in the off state. At this time, as shown in Fig. 6, it can be divided into two cases:

(1) Switch S1 is in the on state, and switch S2 is in the off state. At this time, the current passes through the live input terminal, the inductor L1 and the switch S1, and is divided into two paths after the switch S1, and the switch S2 is diode diode and inductor. L2 to the neutral input, the other via the S4 channel to the neutral input. (2) The switches SI and S2 are simultaneously in the off state. At this time, the current passes through the parallel input of the live input terminal, the inductor L1, the diode D1, the capacitor C and the load R, and is in parallel via the capacitor C and the load R. After splitting into two ways, one way through the switch S2 body diode, the inductor L2 to the zero line input, the other through the switch S4 channel to the zero line input.

As can be seen from the above description, in the positive half cycle of the power frequency, the switch S2 and the inductor L2 are connected in series and connected in parallel with the switch S4 to provide a power current loop. When switching from the positive half cycle of the power frequency to the negative half cycle of the power frequency, the dead time of the power supply zero-crossing point is preset by the control unit, and the dead time is set according to the product efficiency index and reliability. Similarly, at the negative half of the power frequency, switch S1 and inductor L1 are connected in series and in parallel with switch S3 to provide a power current loop. Since the total impedance of the parallel branch is smaller than the impedance value of any one of the branches, that is, the impedance value of the parallel branch is smaller than the RDS(on) of the MOS tube S4 or S3, and the RDS(on) of the general MOS tube is several tens of milliohms. Therefore, the on-state loss caused by the parallel branch is very low, so that the efficiency of the bridgeless PFC circuit is significantly improved. At the same time, due to the low voltage side of the bus and the mains input! The controllable switching device is introduced between ^ and N, bypassing the EMI common mode noise, so that the potential of the low voltage side of the busbar relative to the N line does not float with the switching frequency, thereby improving the EMI common mode noise of the bridgeless PFC circuit, and the easier Achieve productized applications with higher practical value. In addition, since the switching frequency of the controllable switching devices S3 and S4 is the mains frequency, the dead time setting is flexible and the product reliability is high.

Next, a structural diagram of the bridgeless PFC circuit shown in Fig. 7 is taken as a third embodiment of the present invention, and Fig. 5 will be described in detail. In Fig. 7, the switch S1 and the switch S2 are IGBT tubes without a body diode, and the switch S3 and the switch 84 are MOS tubes. It should be noted that the switches S3 and S4 can also be IGBT tubes or relays. The specific working process is similar to the switch S1 and the switch S2 being IGBT tubes without body diodes. The operation of the switches S3 and S4 is similar to that of the MOS tubes. This will not be repeated here. Since the working frequency of the power frequency is positive and negative, the working process is symmetrical. Therefore, the power frequency positive half cycle is taken as an example for detailed description. At this time, the control unit makes the switch S3 in the off state, and the switch S4 is in the conduction state. Here, there are two cases: First, the switch SI is in the PWM state, and the switch S2 is in the off state. At this time, there are two cases:

(1) The switch S1 is in the on state, and the switch S2 is in the off state. At this time, the current passes through the hot line input terminal, the inductor L1, the switch S1, and the switch S4 to the neutral input terminal. There is no current flowing through switch S2.

(2) Switch S1 is in the off state, and switch S2 is in the off state. At this time, the current passes through the input terminal of the live line, the inductor L1, the diode Dl, the parallel branch of the capacitor C and the load R, and the switch S4 to the zero line input terminal. There is no current flowing through switch S2.

In this first case, at the positive half cycle of the power frequency, switches S4 and inductor L1 are connected in series to provide a power current loop.

Second, the switch S1 is in the PWM state, and the switch S2 is in the on state. At this time, there are two cases:

(1) The switches S1 and S2 are in the on state at the same time. At this time, the current passes through the live input terminal, the inductor L1 and the switch S1, and is divided into two paths after the switch S1, one through the switch S2, the inductor L2 to the zero line input end. The other way is through the S4 channel of the switch to the zero line input.

(2) Switch S1 is in the off state, and switch S2 is in the on state. At this time, the current passes through the parallel input of the live input terminal, the inductor L1, the diode D1, the capacitor C and the load R, and is in the capacitor C and the load R. The parallel branch is divided into two paths, one through the switch S2, the inductor L2 to the zero line input, and the other through the switch S4 channel to the zero line input.

In the second case, in the positive half cycle of the power frequency, the switch S2 and the inductor L2 are connected in series and connected in parallel with the switch S4, and then connected in series with the device such as the inductor L1 to provide a power current loop.

When switching from the positive half cycle of the power frequency to the negative half cycle of the power frequency, the dead time of the power supply zero-crossing point is preset by the control unit, and the dead time is set according to the product efficiency index and reliability. Similarly, in the negative half cycle of the power frequency, the control unit makes the switch S3 in the on state, the switch S4 is in the off state, the switch S1 is in the off state, and the switch S2 is in the PWM state. The switch S3 and the inductor L2 are connected in series to provide a power current loop; or, in the negative half cycle of the power frequency, the control unit makes the switch S3 in an on state, the switch S4 is in an off state, the switch S1 is in an on state, and the switch S2 is in a state PWM state, at this time, switch S1 and inductor L1 are connected in series and connected in parallel with switch S3, and then connected in series with device such as inductor L2 to provide power current loop. Since the switches S3 and S4 are controllable switching devices with low on-resistance, the corresponding turn-on voltage drop is low, so that the controllable switching device replaces the diode having a high on-voltage drop in the bridgeless PFC circuit. The on-state loss of the bridgeless PFC circuit can be reduced, and the efficiency of the bridgeless PFC circuit is further improved. Other beneficial effects are the same as those provided by the circuit provided in FIG. 6, and are not described herein again.

In addition, the bridgeless power factor correction circuit shown in FIG. 5 can also be improved. FIG. 8 is a schematic diagram of another bridgeless power factor correction circuit according to an embodiment of the present invention, which is different from FIG. 5. In FIG. 8, the control unit includes three output ends, the first output end is connected to the third end of the switch S1 and the switch S2, the second output end is connected to the third end of the switch S3, and the third output end is connected to the third end of the switch S4. At the three ends, the control unit controls the switch S1 and the switch S2 in the PWM state. In this case, the current flow direction can be referred to in the above embodiment. The descriptions of the switch S1 and the switch S2 are in the PWM state. Let me repeat. Among them, the switch S1 and the switch S2 are IGBT tubes or MOS tubes with body diodes. A further detailed circuit diagram of Fig. 8 can be seen in Fig. 6 and Fig. 7, and will not be described again.

A fourth embodiment of the present invention provides a control method of a bridgeless PFC circuit, wherein the bridgeless PFC circuit includes as shown in FIG. 5:

The inductor L1 has a first end connected to the live input terminal;

Inductor L2, the first end of which is connected to the neutral input;

a diode D1 having an anode connected to the second end of the inductor L1;

a diode D2 having an anode connected to the second end of the inductor L2;

The load R and the capacitor C form a parallel branch, and the high voltage side end of the parallel branch is connected to the cathode of the diode D1 and the diode D2; The switch SI is a first controllable switching device, the first end of which is connected to the anode of the diode D1, and the second end of which is connected to the low-voltage side end of the branch of the load R and the capacitor C;

a control unit, the first input end of which is connected to the live line input end, the second input end of which is connected to the neutral line input end, the first output end of which is connected to the third end of the switch S1, and the second output end is connected to the third end of the switch S2, The third output is connected to the third end of the switch S3, and the fourth output is connected to the switch S4 as shown in FIG. 9. The method includes:

Step 901: When the utility power is switched between positive and negative half cycles of the power frequency, the dead time is set at the zero crossing point of the commercial power. Specifically, the dead time is set based on product efficiency indicators and reliability. Step 902: Detecting that the utility power is in the positive half cycle of the power frequency or the negative half cycle of the power frequency according to the signal of the utility power detecting circuit. If the power frequency is positive half cycle, step 903 is performed; if the power frequency is negative half cycle, step 904 is performed.

In step 903, the control unit controls the switch S3 to be in an off state, and the switch S4 is in an on state. In step 904, the control unit controls the switch S3 to be in an on state, and the switch S4 is in an off state. Further, if the switch S1 and the switch S2 are MOS tubes or IGBT tubes with body diodes, the specific circuit diagram can be seen in FIG. 6. The method further includes:

The control unit controls the switch S1 and the switch S2 to be in the PWM state during the positive and negative half cycles of the power frequency; or the control unit controls the switch S1 to be in the PWM state during the positive half cycle of the power frequency, and the switch S2 is in the on state; in the negative half cycle of the power frequency, the control switch S1 In the on state, switch S2 is in PWM Or the control unit controls the switch SI in the PWM state during the positive half cycle of the power frequency, and the switch S2 is in the off state; in the negative half cycle of the power frequency, the control switch S1 is in the off state, and the switch S2 is in the PWM state.

For the flow of the current under the control of the control unit, reference may be made to the second embodiment of the present invention, and details are not described herein again.

Further, if the switch S1 and the switch S2 are IGBT tubes without a body diode, a specific circuit diagram can be seen in FIG. 7, and the method further includes:

The control unit is in the positive half cycle of the power frequency, the control switch S1 is in the PWM state, and the switch S2 is in the off state; in the negative half cycle of the power frequency, the control switch S1 is in the off state, the switch S2 is in the PWM state; or the control unit is in the positive half cycle of the power frequency The control switch S1 is in the PWM state, and the switch S2 is in the on state; in the negative half cycle of the power frequency, the control switch S1 is in the on state, and the switch S2 is in the PWM state.

For the flow of the current under the control of the control unit, reference may be made to the third embodiment of the present invention, and details are not described herein again.

In addition, according to the circuit schematic diagram shown in FIG. 8, a fifth embodiment of the present invention provides a control method of a bridgeless PFC circuit, in which the control unit controls the switches S1 and S2 to be positively and negatively charged in the city. The half-cycle is in the PWM state. For the specific current flow direction, refer to the above embodiment. The descriptions of the switch S1 and the switch S2 are in the PWM state, and are not described herein again.

In the embodiment of the present invention, the controllable switching device with low on-resistance replaces the diode with high on-voltage drop in the bridgeless PFC circuit in the prior art, thereby reducing the on-state loss of the bridgeless PFC circuit, and further improving The efficiency of a bridgeless PFC circuit. At the same time, since the controllable switching device is introduced between the low voltage side of the busbar and the mains input L and N lines, the EMI common mode noise is bypassed, so that the potential of the low voltage side of the busbar relative to the N line does not float with the switching frequency, thereby improving The EMI common mode noise of the bridgeless PFC circuit makes it easier to implement the product application and has higher practical value. In addition, since the switching frequency of the controllable switching devices S3 and S4 is the mains frequency, the dead time setting is flexible and the product is reliable. High sex.

The solution of the present invention is not limited to the applications listed in the specification and the embodiments. Various modifications and variations can be made in accordance with the present invention, and all such changes and modifications are within the scope of the appended claims.

Claims

Claim

A bridgeless power factor correction circuit, the circuit comprising: a first inductor having a first end connected to a live line input end;

a second inductor having a first end connected to the neutral input;

a control unit having a first input connected to the live input, a second input coupled to the neutral input, and a first output coupled to the third end of the first controllable switching device, the second The output end is connected to the third end of the second controllable switching device, the third output end is connected to the third end of the third controllable switching device, and the fourth output end is connected to the fourth controllable switching device a third end; or a first input connected to the live input, a second input coupled to the neutral input, and a first output coupled to the first controllable switching device and the second a third end of the controllable switching device, the second output end of which is connected to the third end of the third controllable switching device, and the third output end of which is connected to the third end of the fourth controllable switching device;

The control unit is configured to control the third controllable switching device and the fourth The switching device is turned off and on, and the switching off and conducting are synchronized with the switching of the electrician's frequency and the negative half cycle.

2. The bridgeless power factor correction circuit according to claim 1, wherein said third controllable switching device and said fourth controllable switching device are metal oxide semiconductor MOS transistors; said MOS transistor The first end is a drain, the second end is a source, and the third end is a gate.

3. The bridgeless power factor correction circuit according to claim 1, wherein said third controllable switching device and said fourth controllable switching device are insulated gate bipolar crystal IGBT transistors; said IGBT The first end of the tube is a collector, the second end is a emission set, and the third end is a gate.

4. The bridgeless power factor correction circuit of claim 1 wherein: said third controllable switching device and said fourth controllable switching device are relays; said first end of said relay being first The power contact, the second end is a second power contact, and the third end is a control circuit for driving the coil.

The bridgeless power factor correction circuit according to any one of claims 1 to 4, wherein the first controllable switching device and the second controllable switching device are both MOS transistors, or both IGBT tubes with body diodes, or IGBT tubes without body diodes.

A control method for a bridgeless power factor correction circuit, the method comprising: connecting a first end of a first inductor to a live input terminal, and connecting a first end of the second inductor to a zero line input end ;

7. The control method of a bridgeless power factor correction circuit according to claim 6, wherein the control unit controls turn-off and conduction of the third controllable switching device and the fourth controllable switching device The specifics are:

The control method of the bridgeless power factor correction circuit according to claim 6 or 7, wherein the first controllable switching device and the second controllable switching device are both MOS tubes or both The IGBT tube of the body diode, the method further comprising:

The control unit controls the first controllable switching device and the second controllable switching device to be in a pulse width modulation PWM state in a positive and negative half cycle of the power frequency; or to control the first controllable switch in a positive half cycle of the power frequency The device is in a PWM state, and the second controllable switching device is in an on state; Negative half cycle, controlling the first controllable switching device to be in an on state, the second controllable switching device is in a PWM state; or controlling the first controllable switching device to be in a PWM state during a positive half cycle of the power frequency The second controllable switching device is in an off state; in the negative half cycle of the power frequency, the first controllable switching device is controlled to be in an off state, and the second controllable switching device is in a PWM state.

The control method of the bridgeless power factor correction circuit according to claim 6 or 7, wherein the first controllable switching device and the second controllable switching device are IGBT tubes without body diodes The method further includes:

10. A control method for a bridgeless power factor correction circuit, the method comprising:

11. The control method of a bridgeless power factor correction circuit according to claim 10, wherein said control unit controls turn-off and conduction of said third controllable switching device and said fourth controllable switching device The specifics are:

The control method of the bridgeless power factor correction circuit according to claim 10 or 11, wherein the first controllable switching device and the second controllable switching device are both IGBT tubes with body diodes Or both are MOS tubes, and the method further includes: