WO2011027387A1

WO2011027387A1 - Amplifier

Info

Publication number: WO2011027387A1
Application number: PCT/JP2009/004309
Authority: WO
Inventors: 王トウ; 三友敏也
Original assignee: 株式会社東芝
Priority date: 2009-09-02
Filing date: 2009-09-02
Publication date: 2011-03-10

Abstract

Provided is an amplifier including: M amplification circuits which are equipped with transistors having source terminals mutually connected and drain terminals connected to a first power potential and amplify an AC signal to obtain an amplified signal; and N-M amplification circuits which are equipped with transistors having drain terminals mutually connected and also connected to the source terminals of the M amplification circuits and source terminals connected to a second power potential and amplify an AC signal to obtain an amplified signal. The source terminals of the M amplification stages and the drain terminals of the N-M amplification stages are commonly connected.

Description

amplifier

The present invention relates to an amplifier.

A method having a plurality of amplification stages is known as a method for realizing a high output amplifier capable of obtaining a large output signal with respect to an input signal. For example, in the amplifier shown in Patent Document 1, the current flowing through the current adjustment circuit is adjusted so that the amplification operation of the transistor that is the amplification stage is not saturated.

JP 2003-332864 A (page 1-7, Fig. 1)

The above-described amplifier has a problem that a part of the current flowing through the amplification stage flows through the current adjustment circuit, so that the current for signal amplification is wasted. Furthermore, since the total amount of current flowing through each amplification stage increases as the number of amplification stages increases, the amplifier disclosed in Patent Document 1 has a problem that it is difficult to increase the number of amplification stages to three or more.

The present invention has been made to solve this problem, and an object of the present invention is to provide an amplifier that suppresses an increase in power consumption even when the number of amplification stages is increased.

In order to achieve the above object, an amplifier according to the present invention includes a transistor having source terminals connected to each other and a drain terminal connected to a first power supply potential, and amplifies an AC signal to obtain an amplified signal. M amplifier stages and transistors having drain terminals connected to the source terminals of the M amplifier stages and connected to each other, the source terminals connected to the second power supply potential, and an AC signal NM amplification stages that amplify and obtain an amplified signal, wherein the source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common To do.

According to the present invention, it is possible to provide an amplifier that suppresses an increase in power consumption.

1 is a diagram showing an amplifier 1 according to a first embodiment. The figure which shows an example of an amplification stage. The figure which shows an example of an amplification stage. The figure which shows the amplifier 2 which concerns on 1st Example. 1 is a diagram showing an amplifier 3 according to a first embodiment. FIG. 1 is a diagram showing an amplifier 4 according to a first embodiment. FIG. The figure which shows the amplifier 5 which concerns on the modification 2 of 1st Example. The figure which shows the amplifier 6 which concerns on 2nd Example. The figure which shows the amplifier 7 which concerns on 3rd Example. The figure which shows the transmitter 1000 which concerns on 4th Example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in the following embodiments, the same numbered parts are assumed to perform the same operation, and repeated description is omitted.

(First Example)
The amplifier according to the first embodiment of the present invention includes M amplification stages that amplify an AC signal to obtain an amplification signal, and NM amplification stages that amplify the AC signal to obtain an amplification signal. The M amplification stages have transistors whose source terminals are connected to each other and whose drain terminals are connected to the first power supply potential. The NM amplifier stages have transistors having drain terminals connected to the source terminals of the M amplifier stages and connected to each other, and the source terminals connected to the second power supply potential. The source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common. For this reason, the sum total of direct currents flowing through the M amplification stages is equal to the sum of direct currents flowing through the NM amplification stages. Further, of the M and NM amplification stages, the drain terminal of the kth amplification stage (k is an integer of 0 <k <N) is connected to the gate terminal of the (k + 1) th amplification stage, and The k + 1th amplification stage amplifies the amplified signal amplified by the k amplification stage.

Hereinafter, when simply referred to as an amplification stage, it refers to all M and NM amplification stages.

(Example 1 where N = 3, M = 2)
FIG. 1 is a diagram showing an amplifier 1 according to a first embodiment of the present invention when N = 3 and M = 2. The amplifier 1 of FIG. 1 has first to third amplification stages 100-1 to 100-3. In this example, the first and second amplification stages 100-1 and 2 correspond to M (2) amplification stages, and the third amplification stage 100-3 corresponds to NM (3-2 = 1) amplification stages. To do.

The amplification stage has an input terminal A to which an AC signal is input, first and second terminals B and C connected to either the first or second power supply potential, and an output terminal D for outputting the amplified signal. Yes.

The input terminal A of the first amplification stage 100-1 becomes the input terminal of the amplifier 1. The first terminal B of the first amplification stage 100-1 is connected to a first terminal B of the second amplification stage 100-2 and a second terminal C of the third amplification stage 100-3 which will be described later. The second terminal C of the first amplification stage 100-1 is connected to the first power supply potential. Hereinafter, it is assumed that the first power supply potential is Vdd and the second power supply potential is ground.

The input terminal A of the second amplification stage 100-2 is connected to the output terminal D of the first amplification stage 100-1. The first terminal B of the second amplification stage 100-2 is connected to the first terminal B of the first amplification stage 100-1 and the second terminal C of the third amplification stage 100-3. The second terminal C of the second amplification stage 100-2 is connected to Vdd.

The input terminal A of the third amplification stage 100-3 is connected to the output terminal D of the second amplification stage 100-2. The first terminal B of the third amplification stage 100-3 is connected to the ground. The second terminal C of the third amplification stage 100-3 is connected to the first terminal B of the first and second amplification stages 100-1, 2. The output terminal D of the third amplification stage 100-3 becomes the output terminal of the amplifier 1.

The first and second amplification stages 100-1 and 2 are connected in parallel (in terms of DC) in terms of DC current. The first and second amplification stages are collectively referred to as a first amplification group 10. The third amplification stage 100-3 is connected in series with the first amplification group 10 in terms of direct current (in terms of direct current). The third amplification stage 100-3 is referred to as a second amplification group 20. By connecting the first amplification group 10 and the second amplification group 20 in series, the sum of the direct currents flowing through each amplification stage of the first amplification group 10 becomes the direct current flowing through each amplification stage of the second amplification group 20. Is equal to the sum of

Next, an example of the first amplification stage 100-1 will be described with reference to FIG. The second and third amplification stages 100-2 and 3 have the same configuration.

The first amplification stage 100-1 includes a first transistor having a gate terminal connected to the input terminal A, a drain terminal connected to the second terminal C via the inductor element L, and a source terminal connected to the first terminal B. An amplifier circuit 110 having M1 is provided. The output terminal D is connected between the inductor element L and the drain terminal of the first transistor M1 via the capacitor element C1. The first amplification stage 100-1 has one end connected to the input terminal A and the gate terminal of the first transistor M1, and the other end having a resistor R to which a bias voltage Vbias is applied. The first amplification stage 100-1 has a capacitor element C2 having one end connected to the first terminal B and the source terminal of the first transistor M1, and the other end grounded.

The first terminals B of the first and second amplification stages 100-1 and 2 are short-circuited in a direct current and are grounded in an alternating current by being connected to the ground via the capacitor element C2. The second terminal C of the third amplifying stage 100-3 is connected to the first terminal B of the first and second amplifying stages 100-1 and 2 to be grounded in an AC manner.

Subsequently, another example of the first amplification stage 100-1 will be described with reference to FIG. The first amplification stage 100-1 in FIG. 2B is a pseudo-differential amplification stage that includes the second transistor M2 in addition to the first transistor M1, and amplifies an AC signal that is a differential signal. The second and third amplification stages 100-2 and 3 have the same configuration.

The first amplification stage 100-1 includes a first transistor having a gate terminal connected to the input terminal A1, a drain terminal connected to the second terminal C via the inductor element L1, and a source terminal connected to the first terminal B. An amplification having M1, a second transistor M2 having a gate terminal connected to the input terminal A2, a drain terminal connected to the second terminal C via the inductor element L2, and a source terminal connected to the first terminal B. A circuit 111 is provided. The output terminal D1 is connected between the inductor element L1 and the drain terminal of the first transistor M1 via the capacitor C11. The output terminal D2 is connected via the capacitor C12 between the inductor element L2 and the drain terminal of the second transistor M2. The first amplification stage 100-1 has one end connected to the input terminal A1 and the gate terminal of the first transistor M1, the other end connected to the resistor R1 to which the bias voltage Vbias is applied, and one end connected to the input terminal A2 and the second transistor M2. And a resistor R2 to which the bias voltage Vbias is applied at the other end.

Since the first amplification stage 100-1 is a pseudo differential amplification stage, the input terminals A1 and A2 constitute the input terminal A in FIG. 1, and the output terminals D1 and D2 constitute the output terminal D in FIG.

The first terminals B of the first and second amplification stages 100-1 and 2 are grounded in an AC manner by connecting the source terminals of the first and second transistors M1 and M2. The second terminal C of the third amplifying stage 100-3 is connected to the first terminal B of the first and second amplifying stages 100-1 and 2 to be grounded in an AC manner.

Return to Figure 1. The magnitude of the direct current flowing through the amplification stage is the size of the first transistor M1 of the amplification stage and the potential difference between the input terminal A and the first terminal B of the amplification stage, that is, between the gate and source of the first transistor M1. It depends on the voltage. By adjusting the size of the first transistor M1 and the gate-source voltage of the amplification stage, the magnitude of the direct current flowing in the first and second amplification stages 100-1 and 1002, and the third amplification stage 100-3 The magnitude of the flowing direct current can be adjusted.

The operation of amplifier 1 will be described with reference to FIG. First, the flow of an AC signal will be described.

The input signal is input to the input terminal A of the first amplification stage 100-1. The input signal is amplified by the first amplification stage 100-1 and converted into a first amplified signal. The first amplified signal is output from the output terminal D of the first amplification stage 100-1 and input to the input terminal A of the second amplification stage 100-2. The first amplification stage is amplified by the second amplification stage 100-2 and converted into a second amplified signal. The second amplified signal is output from the output terminal D of the second amplification stage 100-2 and input to the input terminal A of the third amplification stage 100-3. The second amplified signal is amplified by the third amplification stage 100-3 and converted into a third amplified signal. The third amplified signal is output as the output signal of the amplifier 1 from the output terminal D of the third amplification stage 100-3. In this embodiment, the input signal and the first to third amplified signals are AC signals having signal information in amplitude or phase, for example. Since the first terminals B of the first and second amplification stages 100-1 and 2 are grounded in an AC manner, no AC signal is output from the first terminal B.

Next, the flow of direct current will be described. In the case of the amplifier 1, a direct current flows from Vdd that is the first power supply potential to the ground that is the second power supply potential. This DC current is a current necessary for the amplification stage to amplify the AC signal.

DC current is input from Vdd to the second terminals C of the first and second amplification stages 100-1 and 2, respectively. The direct currents input to the first and second amplification stages 100-1 and 2 are output from the first terminals B of the first and second amplification stages 100-1 and 2, and are combined to form the third amplification stage 100- Entered in 3. That is, a direct current equal to the sum of direct currents flowing through the first and second amplification stages 100-1 and 2 flows through the third amplification stage 100-3. The direct current input to the third amplification stage 100-3 is output from the first terminal B of the third amplification stage to the ground.

(Example 2 where N = 3, M = 2)
FIG. 3 (a) shows another amplifier 2 according to the present embodiment when N = 3 and M = 2.

The first terminal B of the first amplification stage 100-1 of the amplifier 2 is connected to the second terminal C of the second amplification stage 100-2 and the first terminal B of the third amplification stage 100-3. The first terminal B of the second amplification stage 100-2 is connected to the ground, and the second terminal C is connected to the first terminals B of the first and third amplification stages 100-1 and 3. The first terminal B of the third amplification stage 100-3 is connected to the first terminal B of the first amplification stage 100-1 and the second terminal C of the second amplification stage 100-2, and the second terminal C is connected to Vdd. Yes.

In the amplifier 2, the first and third amplification stages 100-1 and 100-3 are connected in parallel in a direct current, and the first and third amplification stages 100-1, 3 and the second amplification stage 100-2 are connected in a direct current. The configuration is the same as that of the amplifier 1 in FIG. 1 except that the amplifiers are connected in series. In the case of the amplifier 2 in FIG. 3A, the first and third amplification stages 100-1 and 3 are collectively referred to as a first amplification group 10, and the second amplification stage 100-2 is defined as a second amplification group 20.

The flow of the AC signal of the amplifier 2 is the same as that of the amplifier 1, and flows in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The direct current is input from Vdd to the second terminals C of the first and third amplification stages 100-1 and 3, respectively. The direct currents input to the first and third amplification stages 100-1 and 3 are output from the first terminals B of the first and third amplification stages 100-1 and 3, and then combined, and then the second amplification stage. Input to 100-2. That is, a direct current equal to the sum of the currents flowing through the first and third amplification stages 100-1 and 3 flows through the second amplification stage 100-2. The direct current input to the second amplification stage 100-2 is output from the first terminal B of the second amplification stage to the ground.

If the amplification stages included in each amplification group are connected in parallel with each other in DC, and each amplification group is connected in series with DC, the sum of the direct current flowing through the first amplification group 10 and the second amplification group 20 The sum of the flowing DC currents is equal.

(Example of N = 3, M = 1)
Next, FIG. 3 (b) shows an example in the case of N = 3 and M = 1. In this example, the first power supply potential is ground, and the second power supply potential is Vdd. The first terminals B of the first and second amplification stages 100-1 and 2 of the amplifier 3 shown in FIG. 3B are connected to the second terminals C of the third amplification stages 100-2 and 3. The second terminals C of the first and second amplification stages 100-1 and 2 are connected to the ground. The second terminal C of the third amplification stage 100-3 is connected to the first terminal B of the first and second amplification stages 100-1, 2. The first terminal B of the third amplification stage 100-3 is connected to Vdd.

In the amplifier 3, the first and second amplification stages 100-1 and 2 are connected in parallel in a direct current manner, and the first and second amplification stages 100-1 and 100-3 are connected in a direct current manner. Connected in series. In the case of the amplifier 3 in FIG. 3B, the first and second amplification stages 100-1 and 100-2 are defined as the first amplification group 10, and the third amplification stage 100-3 is defined as the second amplification group 20.

The flow of the AC signal of the amplifier 3 is the same as that of the amplifier 1, and flows in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The direct current flows to the third amplification stage 100-3 and then to the first and second amplification stages 100-1 and 2. The direct current flowing through the first and second amplification stages 100-1 and 2 is equal to the sum of the direct current flowing through the third amplification stage 100-3.

(Example of N = 4, M = 2)
FIG. 3 (c) shows an example when N = 4 and M = 2. The first terminal B of the first and second amplification stages 100-1 and 2 of the amplifier 4 shown in FIG. 3 (c) is the second terminal C of the third and fourth amplification stages 100-3,4 and the second terminal C. Is connected to Vdd. The first terminals B of the third and fourth amplification stages 100-3,4 are connected to the ground. The fourth amplification stage 100-4 has the same configuration as the first to third amplification stages 100-1 to 100-3, for example, the stage configuration shown in FIG.

In the amplifier 4, the first and second amplification stages 100-1 and 2 are connected in parallel in a direct current manner. The first and second amplification stages 100-1 and 2 are defined as a first amplification group 10. The third and fourth amplification stages 100-3,4 are connected in parallel in a direct current manner. The third and fourth amplification stages 100-3 and 4 are defined as a second amplification group 20. The first and

second amplification groups

10 and 20 are connected in series in a direct current manner.

The flow of the AC signal input to the amplifier 4 will be described. The AC signal input to the input terminal A of the first amplification stage 100-1 flows in the order of the second amplification stage 100-2, the third amplification stage 100-3, and the fourth amplification stage 100-4. Amplified and output from the output terminal D of the fourth amplification stage 100-4.

Next, the direct current flowing through the amplifier 4 will be described. The direct current flowing from Vdd to the first and second amplification stages 100-1 and 2 flows into the third and fourth amplification stages 100-3,4 and flows to the ground. The sum of direct currents flowing through the first and second amplification stages 100-1 and 2 is equal to the sum of direct currents flowing through the third and third amplification stages 100-3,4.

As described above, in the amplifier according to the first embodiment, M amplifier stages included in the first amplification group (M is an integer satisfying 0 <M <N. In the case of FIG. 1, M = 2). Direct current flowing through the amplification stage can be efficiently utilized by flowing direct current through NM amplification stages (N is an integer of 3 or more. In the case of FIG. 1, N = 3). Further, the number of amplification stages can be increased to three or more, and a high gain and high efficiency amplifier can be provided.

(Modification 1)
When the input AC signal is amplified by the plurality of amplification stages 100-1 to 100-n as in this embodiment, the power of the AC signal that can be output increases as the direct current flowing through the first transistor of the amplification stage increases. Therefore, in order to increase the output power of the amplifier, it is only necessary to increase the current flowing through the first transistor in the subsequent amplification stage than in the previous amplification stage. That is, the k amplification stage 100-k (k is 1 ≦ k <integer n) and DC current I _{k + 1} flowing through the direct current Ik and the k + 1 amplifier stage 100-k + 1 flowing to the I _k ≦ I _{k + 1} is sufficient.

The direct current I _k is determined by the size W _k of the first transistor and the potential difference between the input terminal A and the first terminal B, that is, the gate-source voltage V _{gs-k of} the first transistor M1. Therefore, in order to increase the output power of the amplifier, W _k and V _gs-k may be designed so that I _k ≦ I _{k + 1} .

Further, as in the amplifier 1 shown in FIG. 1, M> NM, M amplification stages are composed of the first to M amplification stages, and NM amplification stages are composed of the M + 1 to N amplification stages. Each size W1s of the first transistors of the NM amplification stages (s is an integer of 1 ≦ s ≦ NM) is each size W2t of the first transistors of the M amplification stages (t is an integer of 1 ≦ t ≦ M) ) Larger than (W1s> W2t). Thus, since M> NM, the sum of the DC currents flowing through the M amplification stages included in the first amplification group 10 is equal to the sum of the DC currents flowing through the NM amplification stages included in the second amplification group 20. can do.

Conversely, if it was W1s <W2T, DC current i _t flowing respectively to the M of the amplification stage is larger than the DC current i _s flows respectively NM number of amplification stages. At this time, the sum Σt = 1Mit of the DC currents flowing in the M amplification stages becomes larger than the sum Σ _{s = 1} ^NM i _{s of the} DC currents flowing in the NM amplification stages, i _t > i _s , M > It is clear from NM.

As described above, in the amplifier 1 of the present modification, the size of the first transistor in the amplification stage is W1s> W2t (s is an integer of 1 ≦ s ≦ N−M, and t is an integer of 1 ≦ t ≦ M). Further, the voltage difference Vgk between the gate terminal and the source terminal of the first transistor of the k-th amplification stage 100-k is set to satisfy Vgk <Vgk + 1. Thereby, the output power of the amplifier can be increased.

The direct current flowing through the first transistors M1 of the first to third amplification stages 100-1 to 100-3 included in the amplifier 1 shown in FIG. 1 satisfies I ₁ <I ₂ <I ₃ and I ₁ + I ₂ = I ₃ . Therefore, the powers P ₁ to P _{3 of the} AC signals output from the first to third amplification stages 100-1 to 100-3 also satisfy P ₁ <P ₂ <P ₃ . The AC signal is input in the order of the first amplification stage 100-1, the second amplification stage 100-2, and the third amplification stage 100-3. The AC signal increases in order as it is input to the amplification stage.

(Modification 2)
A second modification of the first embodiment will be described with reference to FIG. The amplifier 5 according to the modified example 2 further includes a comparison amplifier 120 in addition to the configuration of the amplifier 1 of FIG.

The comparison amplifier 120 compares the voltage at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3 with the reference voltage Vref, and based on the comparison result Thus, a voltage is applied to the input terminal A of the third amplification stage 100-3 via the resistor R3.

When the power of the AC signal input to the amplifier 5 fluctuates, the voltages at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3 also fluctuate. . Due to this fluctuation, the signal output from the amplifier 5 is distorted. Therefore, in this modification, the comparison amplifier 120 is used to suppress fluctuations in the voltage at the first terminal B of the first and second amplification stages 100-1 and 2 and the second terminal C of the third amplification stage 100-3. Thus, distortion of the output signal of the amplifier 5 is suppressed.

Similarly, the amplifiers 2 to 4 shown in FIG. 3 also use a comparison amplifier to compare the voltage of the short-circuited terminal of the amplification stage with the reference voltage Vref, and to compare the voltage based on the comparison result to the second terminal. It is also possible to suppress fluctuations in the DC current flowing through the amplifiers 2 to 4 by performing feedback to one of the amplification stages where C is connected to the ground.

(Second embodiment)
A second embodiment of the present invention will be described with reference to FIG. The circuit shown in FIG. 5 is a circuit having both a frequency conversion function and an amplification function. In this embodiment, it is referred to as an amplifier 6 having a frequency conversion function.

The amplifier 6 includes an adding circuit 131 in addition to the amplifier 1 shown in FIG. The adding circuit 131 and the first amplification stage 100-1 are collectively referred to as a frequency conversion circuit 130. The frequency conversion circuit 130 converts the frequency of the input signal using the LO signal (local signal), and outputs the signal _Sout to the second amplification stage 100-2.

The input signal input to the frequency conversion circuit 130 is first added to the LO signal by the adder circuit 131. Frequency f _{the add} of the sum of the input signal and the LO signal addition signal S _{the add} is the frequency of the input signal f _in, and the frequency of the LO signal and f _lo, satisfy _{_{_{f add = f in ± f lo}}} . The addition signal _Sadd is input to the gate terminal of the first transistor M1 included in the first amplification stage 100-1. The first transistor M1 has a function of amplifying the addition signal _Sadd and simultaneously converting the square of the input voltage into a current. The output signal of the first amplifier stage 100-1, i.e., the frequency fout of the signal S _out output from the frequency conversion stage 130 has a frequency of the sum or difference of f _in and f _LO. Since the operation of the amplifier 6 after the second amplification stage 100-2 is the same as that of the amplifier 1, the description thereof is omitted.

As described above, in the second embodiment, the frequency conversion function can be added to the amplifier 6 by providing the adder circuit 131 in front of the first amplification stage 100-1. The first transistor M1 included in the frequency conversion circuit 130 can share the direct current with the first transistor M1 included in the second and third amplification stages 100-2 and 3 to suppress the power consumption of the amplifier 6.

In addition, it is possible to provide the amplifiers 2 to 3 with a frequency conversion function by providing the adder circuit 131 before the first amplification stage 100-1 of the amplifiers 2 to 3 shown in FIG.

Further, any frequency conversion circuit having a transistor may be used instead of the frequency conversion circuit 130 shown in this embodiment. By sharing the direct current flowing through the transistor included in the frequency conversion circuit and the direct current flowing through the amplification stage, the power consumption of the amplifier 6 having the frequency conversion function can be suppressed.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. The circuit shown in FIG. 6 is a circuit having both an oscillation function and an amplification function. In this embodiment, it is referred to as an amplifier 7 having an oscillation function.

The amplifier 7 has an oscillation circuit 140 instead of the first amplification stage 100-1 of the amplifier 1 of FIG. The oscillation circuit 140 includes transistors M3 and M4 that are cross-coupled to each other, and variable capacitor elements C3 and C3 that are connected to the drain terminals of the transistors M3 and 4 and that are connected in series to each other. ing.

The gate terminal of the transistor M3 is connected to the drain terminal of the transistor M4, the drain terminal is connected to one end of the variable capacitor element C3 and one end of the inductor element L3, and the source terminal is connected to the ground.

The gate terminal of the transistor M4 is connected to the drain terminal of the transistor M3, the drain terminal is connected to one end of the variable capacitor element C4 and one end of the inductor element L4, and the source terminal is connected to the ground.

The variable capacitor element C3 has one end connected to the drain terminal of the transistor M3 and the other end connected to the other end of the variable capacitor element C4. The inductor element L3 has one end connected to the drain terminal of the transistor M3 and the other end connected to the other end of the inductor element L4 and Vdd.

The oscillation signal that is the output signal of the oscillation circuit 140 is output from the drain terminals of the transistors M3 and M4, and is input to the second amplification stage 100-2 via the capacitor elements C31 and C32. Since the oscillation circuit 140 shown in FIG. 6 outputs an oscillation signal that is a differential signal, the second and third amplification stages 100-2 and 3 of the amplifier 7 have pseudo differential amplification stages shown in FIG. Use.

The sum of the direct current flowing through the transistors M3 and M4 and the direct current flowing through the second amplification stage 100-2 is made equal to the direct current flowing through the third amplification stage 100-3.

As described above, in the third embodiment, the amplifier 7 having an oscillation function can be provided by providing the oscillation circuit 140 instead of the first amplification stage 100-1. The sum of the direct current flowing through the transistors M3 and 4 and the direct current flowing through the second amplification stage 100-2 is made equal to the direct current flowing through the third amplification stage 100-3, so that the direct current flowing through the oscillation circuit 140 is reached. Since the current and the direct current flowing through the second and third amplification stages 100-2 and 3 can be shared, the power consumption of the amplifier 7 can be suppressed.

It is obvious that the same effect as in this embodiment can be obtained even if the oscillation circuit 140 is provided instead of the first amplification stage 100-1 of the amplifiers 2 to 3 shown in FIG.

Further, if the oscillation circuit has a transistor, the oscillation circuit 140 shown in this embodiment may be used instead. By sharing the direct current flowing through the transistor included in the oscillation circuit and the direct current flowing through the amplification stage, the power consumption of the amplifier 7 having the oscillation function can be suppressed.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 shows a transmitter 1000 that uses the amplifier 1 as a PA (Power Amplifier).

The transmitter 1000 includes a low-pass filter 1001, a mixer 1002, an amplifier 1, a band-pass filter 1003, and an antenna 1004.

Transmission data to be transmitted to the transmission partner of the transmitter 1000 is subjected to signal processing such as modulation and DA conversion in a signal processing unit (not shown) and converted to an IF signal.

The low pass filter 1001 extracts a signal in a desired band from the IF signal, and outputs the extracted IF signal to the mixer 1002 at the subsequent stage. The mixer 1002 multiplies the IF signal and the LO signal to generate an RF signal. The amplifier 1 is the amplifier shown in FIG. 1 and amplifies an RF signal and outputs an amplified signal. The bandpass filter 1003 extracts a signal in a desired band from the amplified signal and transmits a radio signal via the antenna 1004.

As described above, according to the fourth embodiment, the power consumption of the transmitter 1000 can be suppressed by using it as the PA of the transmitter 1000.

In addition to the amplifier 1 shown in FIG. 1, amplifiers 2 to 6 may be used. In particular, the amplifier 6 has a frequency conversion function, so that the mixer 1002 of the wireless device 1000 can be omitted, and the circuit area of the wireless device can be reduced.

Note that even if the configuration is other than the transmitter shown in FIG. 7, if the transmitter uses a PA, the power consumption of the transmitter can be reduced by using the amplifiers 1 to 6 shown in the first to third embodiments. In addition to the PA of the transmitter, the amplifiers 1 to 6 shown in the first to third embodiments may be used as the amplification means of the receiver.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1-7 amplifier, 100 amplifier stage, 110,111 amplifier circuit, 130 frequency converter circuit, 131 adder circuit, 140 oscillator circuit

Claims

M (M is an integer of 2 or more) amplifier circuits that have transistors whose source terminals are connected to each other and whose drain terminals are connected to the first power supply potential, and that amplify an AC signal and obtain an amplified signal; ,
A drain terminal is connected to the source terminals of the M amplifier circuits and connected to each other, and the source terminal has a transistor connected to the second power supply potential, and an AC signal is amplified to obtain an amplified signal. NM (N is an integer of 3 or more) amplifier circuits,
The amplifier, wherein the source terminals of the M amplification stages and the drain terminals of the NM amplification stages are connected in common.
Of the M and NM amplifier circuits, the drain terminal of the kth amplifier circuit (k is an integer of 0 <k <N) is connected to the gate terminal of the (k + 1) th amplifier circuit, and the kth amplifier circuit. 2. The amplifier according to claim 1, wherein the k + 1-th amplifier circuit amplifies the amplified signal amplified by the amplifier circuit.
3. M> NM, and the M amplifier circuits include first to M amplifier circuits, and the NM amplifier circuits include M + 1 to N amplifier circuits. The described amplifier.
Each size W1s (s is an integer of 1 ≦ s ≦ NM) of the transistors of the NM amplifier circuits is each size W2t of the transistors of the M amplifier circuits (t is an integer of 1 ≦ t ≦ M). 4. The amplifier according to claim 3, wherein the amplifier is larger (W1s> W2t).
The amplifier according to claim 4, wherein the voltage difference Vgk between the gate terminal and the source terminal of the transistor of the kth amplifier circuit satisfies Vgk <Vgk + 1.