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WO2011040313A1 - Semiconductor module, process for production thereof - Google Patents

Semiconductor module, process for production thereof Download PDF

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Publication number
WO2011040313A1
WO2011040313A1 PCT/JP2010/066454 JP2010066454W WO2011040313A1 WO 2011040313 A1 WO2011040313 A1 WO 2011040313A1 JP 2010066454 W JP2010066454 W JP 2010066454W WO 2011040313 A1 WO2011040313 A1 WO 2011040313A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor module
heat sink
insulating substrate
module according
base plate
Prior art date
Application number
PCT/JP2010/066454
Other languages
French (fr)
Japanese (ja)
Inventor
朗 両角
池田　良成
Original Assignee
富士電機システムズ株式会社
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Filing date
Publication date
Application filed by 富士電機システムズ株式会社 filed Critical 富士電機システムズ株式会社
Publication of WO2011040313A1 publication Critical patent/WO2011040313A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0006—Exothermic brazing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/04—Heating appliances
    • B23K3/047—Heating appliances electric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a power semiconductor module for controlling a large current in an electric vehicle, electric railway, machine tool, and the like, and more particularly to a power semiconductor module integrated with a heat sink.
  • FIG. 11 is a cross-sectional view schematically showing a conventional semiconductor module.
  • the power semiconductor module 5 includes a metal base plate 50, and an insulating substrate 60 is joined to the metal base plate 50 with solder 33.
  • the insulating substrate 60 has a configuration in which metal plates 62 and 63 are bonded to both surfaces of an insulating plate 61.
  • the metal plate 62 is selectively provided on the insulating plate 61 as a circuit pattern.
  • the semiconductor chip 40 is joined to the metal plate 62 as a circuit pattern by solder 34.
  • An electrode (not shown) provided on the surface of the semiconductor chip 40 and the metal plate 62 are connected by a bonding wire 81.
  • a resin case 70 in which an external connection terminal 82 that is electrically connected to an external member is insert-molded is mounted on the periphery of the metal base plate 50 so as to surround the semiconductor chip 40 and the like.
  • the inside of the resin case 70 is filled with silicone gel 71 and epoxy resin 72, the semiconductor chip 40 and the like are sealed, and a lid 73 is fixed above it.
  • Such a power semiconductor module 5 is fixed to a heat sink 20 prepared on the user side by means of screws or the like via a heat dissipating grease 90, and is used as a component for controlling a large current in an electric vehicle, an electric railway, a machine tool or the like.
  • the heat dissipating grease 90 fills a gap generated between the power semiconductor module 5 and the heat sink 20 and has a function of suppressing the heat conduction by the air layer formed in the gap, and the heat generated in the semiconductor chip 40 is reduced. This is transmitted to the heat sink 20 (see, for example, Patent Document 1 (FIG. 7)).
  • the metal base plate 50 of the power semiconductor module 5 and the heat sink 20 described above are in contact with the heat radiating grease 90.
  • the metal base plate 50 is made of copper (Cu).
  • the heat sink 20 is made of aluminum (Al).
  • the thermal conductivities of copper and aluminum are about 390 W / (m ⁇ K) and about 220 W / (m ⁇ K), respectively.
  • the thermal conductivity of the heat dissipating grease 90 is about 1.0 W / (m ⁇ K).
  • the thermal conductivity of the heat dissipating grease 90 is lower than that of metals such as copper and aluminum. For this reason, between the metal base board 50 and the heat sink 20, the part of the thermal radiation grease 90 becomes a large thermal resistance.
  • bonding by solder is generally used. Also known is a method of soldering using a flux.
  • a method for bonding bonding materials there is disclosed a method for bonding a semiconductor device to a printed circuit board or the like using a reactive multilayer metal foil (for example, Patent Document 2 (page 22, pages 3 to 8) described below. Line)).
  • wire bonding is performed in a state where the heat sink 20 is bonded to the insulating substrate 60.
  • the transmission of ultrasonic waves may be incomplete, resulting in poor bonding between the silicon chip and the wire or damage to the silicon chip.
  • the present invention has an object to provide a semiconductor module in which a metal base plate and a heat sink are directly joined without using a heat dissipating grease, and a method for manufacturing the same, in order to eliminate the above-described problems caused by the prior art. Moreover, it aims at providing the semiconductor module provided with the outstanding heat dissipation performance, and its manufacturing method. It is another object of the present invention to provide a semiconductor module with a reduced manufacturing cost and a manufacturing method thereof.
  • a semiconductor module includes a heat sink and one of the heat sinks formed by melting or solidifying solder or plating using a reactive metal foil as a heat source. And a member including a semiconductor chip bonded to the main surface.
  • the heat sink and the member including the semiconductor chip are joined together by solder or plating solidified after being instantaneously melted by the heat generated by the reactive metal foil.
  • a semiconductor module according to a second aspect of the present invention is the semiconductor module according to the first aspect, wherein the member is a metal base plate, an insulating substrate joined to one main surface of the metal base plate, and the insulation. And a semiconductor chip bonded to one main surface of the substrate, wherein the heat sink is bonded to the other main surface of the metal base plate.
  • the heat sink and the metal base plate of the member including the semiconductor chip are joined together by solder or plating solidified after being instantaneously melted by the heat generated by the reactive metal foil.
  • a semiconductor module according to a third aspect of the present invention is the semiconductor module according to the first aspect, wherein the member includes an insulating substrate and the semiconductor chip bonded to one main surface of the insulating substrate.
  • the heat sink is bonded to the other main surface of the insulating substrate.
  • the heat sink and the insulating substrate of the member including the semiconductor chip are joined together by solder or plating solidified after being instantaneously melted by the heat generated by the reactive metal foil.
  • the semiconductor module according to the invention of claim 4 is characterized in that, in the invention of claim 1, the reactive metal foil is a laminated film in which nickel and aluminum are alternately laminated.
  • the reactive metal foil in which nickel and aluminum are alternately laminated acts as a heat source for melting solder or plating.
  • the semiconductor module according to the invention of claim 5 is characterized in that, in the invention of claim 4, the reactive metal foil is a laminated film laminated by a physical vapor deposition method.
  • the semiconductor module according to the invention of claim 6 is characterized in that, in the invention of claim 4, the thickness of the reactive metal foil is 0.05 mm or more and 0.1 mm or less.
  • the reactive metal foil having a thickness of 0.05 mm or more and 0.1 mm or less acts as a heat source for melting the solder or plating, and joins the heat sink and the member including the semiconductor chip. A bonding layer is formed.
  • the semiconductor module according to the second aspect wherein the insulating substrate includes an insulating plate and metal plates respectively bonded to both surfaces of the insulating plate. To do.
  • the semiconductor module according to the invention of claim 8 is characterized in that, in the invention of claim 7, the thickness of the insulating plate is 0.2 mm or more and 1.0 mm or less.
  • the semiconductor module according to the invention of claim 9 is characterized in that, in the invention of claim 7, the insulating plate is alumina, alumina, silicon nitride or aluminum nitride to which alumina or zirconia is added.
  • the insulating substrate includes an insulating plate and metal plates respectively bonded to both surfaces of the insulating plate. To do.
  • the semiconductor module according to the invention of claim 11 is characterized in that, in the invention of claim 10, the thickness of the insulating plate is 0.2 mm or more and 1.0 mm or less.
  • the semiconductor module according to a twelfth aspect of the invention is characterized in that, in the invention according to the tenth aspect, the insulating plate is alumina, silicon nitride or aluminum nitride to which alumina or zirconia is added.
  • a semiconductor module according to a thirteenth aspect of the present invention is the semiconductor module according to any one of the seventh to twelfth aspects, wherein the metal plate is copper, a copper alloy, aluminum, or an aluminum alloy. .
  • the semiconductor module according to claim 14 is the semiconductor module according to claim 1, wherein the heat sink is copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum, or aluminum-silicon carbide. To do.
  • the semiconductor module according to the invention of claim 15 is characterized in that, in the invention of claim 14, the surface of the heat sink is subjected to nickel plating, gold plating or tin plating.
  • the metal base plate is made of copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum alloy, iron or iron alloy. It is characterized by.
  • the semiconductor module according to the invention of claim 17 is characterized in that, in the invention of claim 16, the surface of the metal base plate is subjected to nickel plating, gold plating or tin plating.
  • the semiconductor chip and the insulating substrate, and the insulating substrate and the metal base plate are respectively joined by solder. .
  • the semiconductor module according to the invention of claim 19 is characterized in that, in the invention of claim 3, the semiconductor chip and the insulating substrate are joined by solder.
  • the semiconductor module according to claim 20 is the semiconductor module according to claim 18 or 19, wherein the solder for joining the insulating substrate and another member is melted and solidified using a reactive metal foil as a heat source. It is characterized by being solder.
  • the semiconductor module according to claim 21 is the semiconductor module according to claim 18 or 19, wherein the main component of the solder is tin-lead alloy, tin-silver alloy, tin-bismuth alloy, tin-antimony alloy. And a tin-copper alloy or a tin-indium alloy.
  • a semiconductor module manufacturing method includes a first step of bonding a semiconductor chip to one main surface of an insulating substrate. After the second step of bonding a wire or a lead frame to the semiconductor chip, and after the first step and the second step, the solder or plating is melted and solidified using a reactive metal foil as a heat source, and the insulation is performed. And a third step of bonding a heat sink to the other main surface side of the substrate.
  • the heat sink is formed on the other main surface side of the insulating substrate in the third step. Can be joined.
  • a method for manufacturing a semiconductor module according to the twenty-second aspect of the present invention wherein, in the first step, a metal base plate is joined to the other main surface of the insulating substrate. In step 3, the heat sink is bonded to the metal base plate.
  • the metal base plate is bonded to the insulating substrate.
  • the insulating substrate is bonded to the heat sink through the metal base plate by solder or plating melted using the reactive metal foil as a heat source.
  • the semiconductor module manufacturing method according to the invention of claim 24 is characterized in that, in the invention of claim 22, in the third step, the heat sink is joined to the insulating substrate.
  • the insulating substrate is directly joined to the heat sink by molten solder or plating using the reactive metal foil as a heat source.
  • a reactive metal foil that itself becomes a heat source is used for joining the heat sink and the member including the semiconductor chip.
  • the heat sink and the member including the semiconductor chip can be bonded instantaneously at room temperature without heating from the outside.
  • the heat sink and the member including the semiconductor chip are joined by solder or plating solidified after being melted using the reactive metal foil as a heat source.
  • the thermal resistance between the heat sink and the member including the semiconductor chip can be reduced. For this reason, the heat sink integrated power semiconductor module excellent in heat dissipation can be provided efficiently.
  • yield rate It is possible to provide a method for manufacturing a power semiconductor module with a high heat sink.
  • the semiconductor module and the manufacturing method thereof according to the present invention there is an effect that the metal base plate and the heat sink can be directly joined without using the heat radiating grease. Moreover, there exists an effect that heat dissipation performance can be improved. Moreover, there exists an effect that cost can be reduced.
  • FIG. 1 is a cross-sectional view schematically showing a main part of the semiconductor module according to the first embodiment.
  • FIG. 2 is a flowchart of the semiconductor module manufacturing method according to the first embodiment.
  • FIG. 3 is a cross-sectional view schematically showing a main part of the semiconductor module according to the second embodiment.
  • FIG. 4 is a cross-sectional view schematically showing a main part of the semiconductor module according to the third embodiment.
  • FIG. 5 is a cross-sectional view schematically showing a main part of the semiconductor module according to the fourth embodiment.
  • FIG. 6 is an explanatory diagram showing the relationship between solder thickness, bondability, and protrusion.
  • FIG. 7 is a cross-sectional view schematically showing a state where the insulating substrate and the metal base plate are warped.
  • FIG. 8 is a characteristic diagram showing the relationship between the thickness of the insulating substrate and the amount of gap between the metal base plate and the heat sink.
  • FIG. 9 is a characteristic diagram showing the relationship between the amount of the gap between the metal base plate and the heat sink and the thickness of the solder.
  • FIG. 10 is a characteristic diagram showing the relationship between heat sink thermal conductivity and thermal resistance.
  • FIG. 11 is a cross-sectional view schematically showing a conventional semiconductor module.
  • the best mode for carrying out the present invention is to use the reactive metal foil as a heat source in a state where the reactive metal foil and the solder plate are inserted between the semiconductor device and the heat sink after the electrical property test is completed. It is to solidify after melting a solder plate by igniting, for example, instantly joining at room temperature.
  • the electrical characteristic test is performed on a semiconductor device in which at least an electrode provided on the surface of the semiconductor chip and a circuit pattern formed on the insulating substrate are connected by a bonding wire.
  • FIG. 1 is a cross-sectional view schematically showing a main part of the semiconductor module according to the first embodiment.
  • the heat sink integrated power semiconductor module 1 according to the first embodiment mainly includes a semiconductor device 10 and a heat sink 20.
  • the semiconductor device 10 is a member including the semiconductor chip 40.
  • the semiconductor device 10 is joined to one main surface of the heat sink 20 by solders 31 and 32 that are solidified after being melted using the reactive metal foil 30 as a heat source.
  • the reactive metal foil 30 is a metal foil that self-ignites when a stimulus is applied, for example, by passing an electric current.
  • the semiconductor device 10 and the heat sink 20 are joined as follows.
  • the semiconductor device 10 includes a semiconductor chip 40, an insulating substrate 60, and a metal base plate 50.
  • the semiconductor chip 40 is bonded to one main surface of the insulating substrate 60 by solder 34.
  • the insulating substrate 60 has a configuration in which metal plates 62 and 63 are bonded to both surfaces of the insulating plate 61.
  • the metal plate 62 is selectively provided on the insulating plate 61 as a circuit pattern.
  • the semiconductor chip 40 is joined to a metal plate 62 as a circuit pattern by solder 34.
  • the insulating substrate 60 is joined to one main surface of the metal base plate 50 by solder 33.
  • the metal plate 63 bonded to the other main surface of the insulating substrate 60 is bonded to the metal base plate 50 by the solder 33.
  • the heat sink 20 is bonded to the main surface (the other main surface) of the metal base plate 50 opposite to the main surface (one main surface) to which the insulating substrate 60 is bonded by solders 31 and 32. .
  • a reactive metal foil 30 is sandwiched between the solder 31 and the solder 32 as a heat source for the solders 31 and 32.
  • the power semiconductor module 1 including the semiconductor device 10 and the heat sink 20 includes the heat sink 20, the solder 31, the reactive metal foil 30, the solder 32, the metal base plate 50, the solder 33, the insulating substrate 60 (the metal plate 63) from the heat sink 20 side.
  • the insulating plate 61 and the metal plate 62 are joined in this order), the solder 34 and the semiconductor chip 40 are joined in this order.
  • the power semiconductor module 1 is electrically connected to an external member and a bonding wire 81 that electrically connects an electrode (not shown) provided on the surface of the semiconductor chip 40 and a metal plate (circuit pattern) 62.
  • a resin case 70 that surrounds the external connection terminal 82, the semiconductor chip 40, etc. and is fixed to the periphery of the metal base plate 50, a silicone gel 71 filled in the resin case 70, and an upper portion of the silicone gel 71
  • the epoxy resin 72 and the lid 73 are provided.
  • the metal plate 62 and the external connection terminal 82 are connected by a bonding wire 81.
  • a silicone gel 71 Inside the resin case 70, the semiconductor chip 40, the metal plate 62, the bonding wire 81, and the like are sealed with a silicone gel 71.
  • the epoxy resin 72 covers the silicone gel 71. Further, the end portion of the epoxy resin 72 is in contact with the resin case 70.
  • the lid 73 is provided on the silicone gel 71 and the epoxy resin 72 and fixes the silicone gel 71 and the epoxy resin 72.
  • the cross-sectional shape of the resin case 70 may be, for example, an L shape.
  • the cross-sectional shape of the external connection terminal 82 may be L-shaped, for example.
  • the semiconductor chip 40 includes an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode) that circulates an induced current generated when the IGBT chip is turned off. Etc. may be formed.
  • IGBT Insulated Gate Bipolar Transistor
  • FWD Free Wheeling Diode
  • the insulating substrate 60 is configured, for example, by bonding the metal plates 62 and 63 to the main surface of the ceramic insulating plate 61 on the semiconductor chip 40 side and the main surface (both surfaces) of the metal base plate 50, respectively. ing.
  • the insulating substrate 60 is a DCB (Direct Copper Bonding) substrate.
  • the metal plate 62 formed on one main surface of the insulating plate 61 is subjected to circuit pattern processing.
  • the thickness of the insulating substrate 60 is 0.6 mm or more and 2.0 mm or less.
  • the material of the insulating plate 61 is various ceramics, preferably alumina (Al 2 O 3 ), alumina to which zirconia (ZrO 2 ) is added, silicon nitride (Si 3 N 4 ), or aluminum nitride (AlN).
  • the thickness of the insulating plate 61 is not less than 0.2 mm and not more than 1.0 mm, preferably not less than 0.2 mm and not more than 0.6 mm.
  • the metal plates 62 and 63 may be copper, a copper alloy, aluminum, or an aluminum alloy.
  • the metal base plate 50 is made of copper, copper alloy, pure aluminum, aluminum alloy, copper-molybdenum (Mo) alloy, pure iron (Fe), or iron alloy. Further, the surface of the metal base plate 50 is preferably subjected to nickel (Ni) plating, gold (Au) plating, or tin (Sn) plating.
  • the heat sink 20 is made of, for example, copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum, or aluminum-silicon carbide (SiC). Furthermore, the surface of the heat sink 20 is preferably subjected to nickel plating, gold plating or tin plating.
  • the heat sink 20 may include fins (not shown) having a shape that increases the surface area of the heat sink 20. The shape of the fin may be any shape such as a plate shape, a wave shape, and a culgate.
  • Solder 31, 32, 33, 34 are tin-lead (Pb) alloy, tin-silver (Ag) alloy, tin-bismuth (Bi) alloy, tin-antimony (Sb) alloy, tin-copper alloy, tin-indium (In)
  • Pb tin-lead
  • the solders 31 and 32 that join the semiconductor device 10 and the heat sink 20 are preferably Sn—Sb alloys.
  • the thickness of the solders 31 and 32 is preferably 0.2 mm or more and 0.5 mm or less. The reason will be described later.
  • the reactive metal foil 30 is a laminated film in which nickel layers and aluminum layers are alternately laminated by a physical vapor deposition method (PVD: Physical Vapor Deposition) such as vacuum vapor deposition or sputtering.
  • PVD Physical Vapor Deposition
  • a metal foil provided by Reactive Nano Technologies, Inc. under the trade name NanoFoil (registered trademark) may be used.
  • the thickness of the reactive metal foil 30 is preferably 0.05 mm or more and 0.1 mm or less.
  • the solders 31 and 32 are instantaneously melted by the reactive metal foil 30 that self-ignites.
  • the melted solder 31 is solidified at the interface between the heat sink 20 and the solder 31 so that the heat sink 20 is metal-bonded and integrated.
  • the melted solder 32 is solidified to be metal-bonded and integrated with the metal base plate 50.
  • the heat sink 20 and the metal base plate 50 are joined by a three-layer joining layer of the solder 31, the reactive metal foil 30, and the solder 32.
  • the reactive metal foil 30 that has acted as a heat source becomes an aluminum-nickel alloy bonding layer, for example, when it is a laminate of a nickel film and an aluminum film.
  • FIG. 2 is a flowchart of the method for manufacturing the power semiconductor module according to the first embodiment.
  • the main surface on the metal plate 63 side (the other main surface) of the insulating substrate 60 composed of the insulating plate 61 and the metal plates 62 and 63 is joined to one main surface of the metal base plate 50 by the solder 33.
  • the semiconductor chip 40 is joined to the metal plate 62 on one main surface of the insulating substrate 60 by the solder 34 (step S1).
  • joining (fixing) of the metal base plate 50 and the semiconductor chip 40 with the solders 33 and 34 is performed simultaneously. That is, the solder 33, the insulating substrate 60, the solder 34, and the semiconductor chip 40 are stacked in this order on the upper surface of the metal base plate 50, and these are heated in an atmosphere reduced with nitrogen (N 2 ) or hydrogen (H 2 ) gas. To do. When the solders 33 and 34 are melted, evacuation is performed to remove bubbles remaining in the solder layer. Then, after a predetermined time, the stacked members are cooled to resolidify the solders 33 and 34. As a result, the metal base plate 50, the insulating substrate 60, and the semiconductor chip 40 are joined in a state of overlapping in this order.
  • N 2 nitrogen
  • H 2 hydrogen
  • step S2 the resin case 70 and the metal base plate 50 are bonded (step S2). Specifically, the resin case 70 (envelope) in which the external connection terminals 82 are insert-molded or outsert-molded is fitted and fixed to the periphery of the metal base plate 50 using an adhesive.
  • the surface electrode, the metal plate 62 and the external connection terminal 82 formed on the semiconductor chip 40 are electrically connected by the bonding wire 81 or the lead frame.
  • other electrodes are electrically connected to form a predetermined circuit.
  • the emitter electrode, the collector electrode, and the gate electrode are electrically connected to form a predetermined circuit.
  • the silicone gel 71 is filled in the resin case 70. Then, the upper part of the silicone gel 71 is covered with an epoxy resin 72. Further, a lid 73 is provided on the silicone gel 71 and the epoxy resin 72 to fix the silicone gel 71 and the epoxy resin 72 (step S3).
  • step S4 the electrical characteristics and the operation characteristics test of the circuit configured in the semiconductor device 10 are performed as necessary.
  • the heat sink 20 is prepared, and the solder 31, the reactive metal foil 30 and the solder 32 are stacked in this order on one main surface of the heat sink 20, and the metal base plate 50 of the semiconductor device 10 is placed on the solder 32.
  • the semiconductor devices 10 are stacked so that the other main surface is on the heat sink 20 side.
  • the stacked members are pressed from the semiconductor device 10 side and the heat sink 20 side so that pressure is uniformly applied to the entire solders 31 and 32.
  • an electric current is passed through the reactive metal foil 30 to cause irritation and self-ignition, thereby melting the solders 31 and 32.
  • the metal base plate 50 of the semiconductor device 10 is joined to the heat sink 20 on the other main surface side of the insulating substrate 60, and the heat semiconductor integrated power semiconductor module 1 is completed (step S5).
  • the reactive metal foil 30 that itself becomes a heat source is used for joining the heat sink 20 and the semiconductor device 10.
  • the heat sink 20 and the semiconductor device 10 can be instantaneously bonded at room temperature without heating from the outside.
  • the heat sink 20 and the semiconductor device 10 are joined by the solders 31 and 32 that are solidified after being melted using the reactive metal foil 30 as a heat source.
  • the thermal resistance between the heat sink 20 and the semiconductor device 10 can be reduced. For this reason, the heat semiconductor integrated power semiconductor module 1 excellent in heat dissipation can be provided efficiently.
  • the reactive metal foil 30 it is possible to join only the non-defective product to the heat sink 20 after selecting the plurality of semiconductor devices 10 by the electrical characteristic test. Therefore, it is possible to provide the heat semiconductor integrated power semiconductor module 1 with a high non-defective rate and excellent heat dissipation.
  • a process of joining the heat sink 20 and the semiconductor device 10 using the reactive metal foil 30 that itself becomes a heat source is performed separately from this process. For this reason, it is not necessary to heat the entire heat sink 20 from the outside for bonding, and the manufacturing process can be simplified and made more efficient. Further, since no grease or the like is used, a method for manufacturing the heat semiconductor integrated power semiconductor module 1 with excellent heat dissipation can be provided. Furthermore, after performing the process of testing the electrical characteristics of the semiconductor device 10, a process for bonding using the reactive metal foil 30 is performed, thereby providing a method for manufacturing a power semiconductor integrated power semiconductor module with a high yield rate. can do.
  • FIG. 3 is a cross-sectional view schematically showing a main part of the semiconductor module according to the second embodiment.
  • a power semiconductor module 2 according to the second embodiment is a modification of the first embodiment.
  • platings 35 and 36 respectively applied to the opposing surfaces of the heat sink 20 and the metal base plate 50 may be used as a bonding material.
  • plating 36 is applied to the main surface (other main surface) of the metal base plate 50 on the side where the heat sink 20 is joined.
  • the main surface (one main surface) of the heat sink 20 on the side to which the metal base plate 50 is joined is plated 35.
  • a reactive metal foil 30 serving as a heat source for the platings 35 and 36 is sandwiched between the surface of the metal base plate 50 that is plated 36 and the surface of the heat sink 20 that is plated 35. That is, no solder is sandwiched between the metal base plate 50 and the heat sink 20.
  • the reactive metal foil 30 as a heat source, the metal base plate 50 and the heat sink 20 are bonded together by a bonding layer that solidifies after the platings 35 and 36 are melted.
  • the platings 35 and 36 are preferably platings mainly composed of tin. The reason is that the tin plating itself is melted by the ignition and heat generation of the reactive metal foil 30 and becomes a bonding material for bonding the heat sink 20 and the metal base plate 50.
  • the platings 35 and 36 may be nickel plating or the like. In this case, solder is required as a bonding material in addition to the reactive metal foil 30.
  • the thickness of the platings 35 and 36 may be such that the heat sink 20 and the metal base plate 50 can be joined, and preferably 0.005 mm or more and 0.05 mm or less. Other configurations and manufacturing methods are the same as those in the first embodiment.
  • the platings 35 and 36 are thinner than the solders 31 and 32, and the metal base plate 50 may warp when the semiconductor device 11 and the heat sink 20 are joined using the platings 35 and 36. For this reason, when joining the semiconductor device 11 and the heat sink 20 using the plating 35 and 36, it is desirable that the gap between the metal base plate 50 and the heat sink 20 is as small as possible. Therefore, after the assembly of the semiconductor device 11 is completed (see step S3 in FIG. 2), the metal base plate 50 is flattened before the semiconductor device 11 and the heat sink 20 are joined (see step S5 in FIG. 2). Is preferred. Furthermore, in order to reduce the gap between the metal base plate 50 and the heat sink 20, it is particularly preferable that the planar size of the metal base plate 50 is 70 mm ⁇ 70 mm or less.
  • FIG. 4 is a cross-sectional view schematically showing a main part of the semiconductor module according to the third embodiment.
  • the power semiconductor module 3 according to the third embodiment is a modification of the first embodiment.
  • the insulating substrate 60 and the heat sink 20 may be directly joined without using the metal base plate 50.
  • the semiconductor device 12 does not include the metal base plate 50.
  • the solder which uses the reactive metal foil 30 as a heat source is provided on the main surface (the other main surface) opposite to the main surface (one main surface) to which the semiconductor chip 40 is bonded.
  • the heat sink 20 is joined via 31 and 32.
  • Other configurations are the same as those in the first embodiment.
  • step S1 the joining of the metal base plate 50 and the insulating substrate 60 is omitted in step S1 of the first embodiment (step S1 '). That is, in step S ⁇ b> 1 ′, only the semiconductor chip 40 and the insulating substrate 60 are bonded.
  • step S2 the resin case 70 is fitted and fixed to the periphery of the insulating substrate 60 using an adhesive (step S2 ').
  • step S ⁇ b> 5 the solder 31, the reactive metal foil 30 and the solder 32 are stacked in this order on one main surface of the heat sink 20, and the other main surface of the insulating substrate 60 of the semiconductor device 12 is placed on the solder 32.
  • the semiconductor device 12 is overlaid so that is on the heat sink 20 side.
  • these stacked members are pressurized from, for example, the semiconductor device 12 side and the heat sink 20 side (step S5 ').
  • the other manufacturing methods are the same as those in the first embodiment.
  • the same effect as in the first embodiment can be obtained.
  • the thermal resistance between the semiconductor chip 40 and the heat sink 20 can be reduced.
  • the metal base plate 50 it is possible to avoid warping that occurs in the semiconductor device when the metal base plate 50 and the insulating substrate 60 are joined.
  • the insulating substrate 60 is cracked as compared with a case where grease is sandwiched between the insulating substrate 60 and the heat sink 20 and fixed by screwing. In addition, cracking can be prevented.
  • plating may be used as a bonding material.
  • tin plating is applied to the surface of the metal plate 63 of the insulating substrate 60 and one main surface of the heat sink 20, and the semiconductor device 12 and the heat sink 20 are bonded using tin plating as a bonding material.
  • the metal base plate 50 since the metal base plate 50 is not used, the bottom surface of the insulating substrate 60 is flat. For this reason, the semiconductor device 12 and the heat sink 20 can be joined without performing the flat processing of the insulating substrate 60.
  • FIG. 5 is a cross-sectional view schematically showing a main part of the semiconductor module according to the fourth embodiment.
  • the power semiconductor module 4 according to the fourth embodiment is a modification of the third embodiment.
  • the insulating substrate 60 and the semiconductor chip 40 may be joined by solder solidified after being melted using the reactive metal foil 30 as a heat source.
  • the insulating substrate 60 and the semiconductor chip 40 are joined by the reactive metal foil 130 that is a heat source of the solder 131 and 132 and the solder 131 and 132.
  • the configuration and conditions of the reactive metal foil 130 and the solders 131 and 132 that join the insulating substrate 60 and the semiconductor chip 40 are the same as the reactive metal foil 30 and the solders 31 and 32 that join the insulating substrate 60 and the heat sink 20. is there.
  • the power semiconductor module 4 is stacked from the heat sink 20 side in the order of the heat sink 20, solder 31, reactive metal foil 30, solder 32, insulating substrate 60, solder 131, reactive metal foil 130, solder 132, and semiconductor chip 40. Are joined together.
  • Other configurations are the same as those in the third embodiment.
  • the solder 131, the reactive metal foil 130, the solder 132, and the semiconductor chip 40 are stacked on one main surface of the insulating substrate 60. Then, these stacked members are pressurized from, for example, the semiconductor chip 40 side. In this state, the reactive metal foil 130 is stimulated to self-ignite, and after the solders 131 and 132 are melted and solidified, the insulating substrate 60 and the semiconductor chip 40 are joined (step S1 ′′). The insulating substrate 60 and the semiconductor chip 40 are joined by the solders 131 and 132. Other conditions and the manufacturing method are the same as those in the third embodiment.
  • the same effect as in the third embodiment can be obtained. Further, the reflow process can be omitted in the method for manufacturing the power semiconductor module 4 by bonding the insulating substrate 60 and the semiconductor chip 40 using the reactive metal foil 130.
  • Example 1 The preferred range of the thicknesses of the solders 31 and 32 for joining the heat sink 20 and the metal base plate 50 in the present invention was verified.
  • FIG. 6 is an explanatory diagram showing the relationship between solder thickness, bondability, and protrusion.
  • the power semiconductor module 1 (refer FIG. 1) was produced. Specifically, the semiconductor device 10 in which nickel plating is applied to the surface of the metal base plate 50 and the heat sink 20 in which nickel plating is applied to the joint surface between the metal base plate 50 were prepared. A laminated film in which nickel and aluminum were alternately laminated as the reactive metal foil 30 and Sn—Sb solder plates as the solders 31 and 32 were inserted between the metal base plate 50 and the heat sink 20, respectively.
  • the thickness of the reactive metal foil 30 was 0.05 mm. Next, these stacked members were pressed from the metal base plate 50 side and the heat sink 20 side. In this state, an electric current was passed through the reactive metal foil 30 to ignite, and the solders 31 and 32 were melted and then solidified to join the metal base plate 50 and the heat sink 20. Thereafter, the void state (joinability) of the solder and the presence or absence of protrusion were examined. The thickness of the Sn—Sb solder plate used as the solders 31 and 32 was variously changed, and the above verification was repeated. The thickness of the Sn—Sb solder plate (the thickness of the solder in FIG. 6) was changed from 0.1 mm to 0.7 mm. The result is shown in FIG.
  • the thickness of the Sn—Sb solder plate is preferably 0.2 mm or more and 0.5 mm or less in the joining of the nickel-plated metal base plate 50 and the heat sink 20. Note that there was almost no change in the thickness of the Sn—Sb solder plate and the thickness of the solders 31 and 32 before and after the joining of the metal base plate 50 and the heat sink 20.
  • FIG. 7 is a cross-sectional view schematically showing a state where the insulating substrate and the metal base plate are warped.
  • the thermal expansion coefficient differs between the metal base plate 50 and the insulating substrate 60 made of ceramics. For this reason, when the metal base plate 50 and the insulating substrate 60 are joined by solder, the metal base plate 50 warps in a convex shape toward the insulating substrate 60 due to a difference in thermal expansion coefficient. Therefore, when the metal base plate 50 is placed on the heat sink 20, a gap (hereinafter referred to as a metal base plate gap amount t) is generated between the metal base plate 50 and the heat sink 20. For this reason, when joining the metal base plate 50 and the heat sink 20, solder having a thickness sufficient to fill this gap is required.
  • FIG. 8 is a characteristic diagram showing the relationship between the thickness of the insulating substrate and the gap amount between the metal base plate and the heat sink.
  • the warp (metal base plate gap amount t) of the metal base plate 50 is that of the insulating plate 61 made of ceramics soldered to the surface opposite to the surface to which the heat sink 20 is bonded (upper side of the paper surface in FIG. 7). It is also affected by the thickness.
  • the optimum thickness of the insulating plate 61 is preferably 0.2 mm or more and 0.6 mm or less as described above.
  • the relationship between the metal base plate gap amount t As is apparent from the results shown in FIG. 8, it was found that the warp (metal base plate gap amount t) of the metal base plate 50 increases in proportion to the thickness of the insulating plate 61.
  • FIG. 9 is a characteristic diagram showing the relationship between the amount of the gap between the metal base plate and the heat sink and the thickness of the solder.
  • the relationship between the metal base plate gap amount t and the thicknesses of the solders 31 and 32 necessary to satisfactorily join the metal base plate 50 and the heat sink 20 was examined.
  • a reactive metal foil 30 and solders 31 and 32 for joining the metal base plate 50 and the heat sink 20 were used, and these stacked members were pressed from the metal base plate 50 side and the heat sink 20 side. .
  • the thickness of the insulating plate 61 is not less than 0.2 mm and not more than 0.6 mm
  • the thicknesses of the solders 31 and 32 required to join the metal base plate 50 and the heat sink 20 (Sn ⁇ The thickness of the Sb solder plate was found to be about 0.2 mm or more and 0.5 mm or less. This is consistent with the result of Example 1.
  • the metal base plate gap amount t can be filled and the bondability between the metal base plate 50 and the heat sink 20 can be improved. And it turns out that the protrusion of the solder by pressurization can be decreased.
  • Example 3 Next, the thermal resistance in the power semiconductor module 2 (see FIG. 3) described in the second embodiment was verified.
  • a heat semiconductor integrated power semiconductor module 2 was produced. Specifically, plating 35 and 36 (hereinafter referred to as tin plating) containing tin as a main component is applied to each joint surface of the heat sink 20 and the metal base plate 50. The thickness of the tin plating was 0.05 mm or less. Moreover, the thickness of the reactive metal foil 30 was 0.06 mm. Other configurations are the same as those in the first embodiment.
  • the solders 31 and 32 are necessary as the joining material in addition to the reactive metal foil 30, but in the joining between the tin platings 35 and 36, only the reactive metal foil 30 is used. Thus, it was found that the heat sink 20 and the metal base plate 50 can be joined. The reason is presumed that the tin plating itself is melted by the ignition and heat generation of the reactive metal foil 30 and works as a bonding material.
  • FIG. 10 is a characteristic diagram showing the relationship between heat sink thermal conductivity and thermal resistance.
  • a power semiconductor module integrated with a heat sink was manufactured without using the metal base plate 50 (hereinafter referred to as an example).
  • the heat sink 20 and the insulating substrate 60 are directly joined by plating 35 and 36 without using solder.
  • a power semiconductor module having a conventional structure in which a screw is tightened between a metal base plate and a heat sink via heat-dissipating grease was prepared (see FIG. 11, hereinafter referred to as a conventional structure).
  • FIG. 10 shows the results of evaluating the heat dissipation of the example and the conventional structure in the heat conductivity of the heat sink under these four conditions.
  • the horizontal axis of FIG. 10 is the heat conductivity [W / (m ⁇ K)] of the heat sink, and the vertical axis is the thermal resistance Rth (jw) [K between the semiconductor chip and the heat sink (junction-refrigerant question). / W].
  • the example is superior in heat dissipation compared with the conventional structure.
  • the heat dissipation can be greatly improved by directly bonding the insulating substrate and the heat sink with a metal material without using the metal base plate and the heat dissipation grease.
  • the thermal resistance of the conventional structure is smaller than that of the embodiment.
  • the heat conductivity of the heat sink is preferably 138 W / (m ⁇ K) or more.
  • a power semiconductor module including a semiconductor chip sealed in a state of being connected to a circuit pattern on an insulating substrate with a bonding wire has been described as an example, but not limited to the above-described embodiment, The present invention can be applied to circuits having various configurations. Further, the present invention can be applied to a semiconductor module having lower current performance and voltage performance than a power semiconductor module.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor module for controlling a large current in an electric vehicle, an electric railway, a machine tool, and the like.
  • Power semiconductor module 10 Member (semiconductor device) containing a semiconductor chip 20 heat sink 30 reactive metal foil 31, 32, 33, 34 solder 40 semiconductor chip 50 metal base plate 60 insulating substrate 61 insulating plate 62, 63 metal plate 70 resin case 71 silicone gel 72 epoxy resin 73 lid 81 bonding wire 82 external connection Terminal

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Abstract

A semiconductor chip (40) is bound to one main surface of an insulating substrate (60). A metal base plate (50) is bound to the other main surface of the insulating substrate (60). Subsequently, a resin case is fixed to the peripheral part of the metal base plate (50) in a member containing the semiconductor chip (40). Subsequently, a surface electrode formed on the semiconductor chip (40) is connected to an external connection terminal of the resin case through a bonding wire (81), thereby sealing the semiconductor chip (40). In this manner, a semiconductor device (10) is assembled. In the assembled semiconductor device (10), a solder (31) (32) and a reactive metal foil (30) that acts as a heat source are inserted between the metal base plate (50) and a heat sink (20), the resulting product is pressurized, an electric current is applied to the reactive metal foil (30) to cause ignition to occur, thereby melting the solder (31) (32), and the molten solder (31) (32) is solidified. In this manner, the metal base plate (50) and the heat sink (20) are bound to each other instantly at room temperature.

Description

半導体モジュールおよびその製造方法Semiconductor module and manufacturing method thereof
　本発明は、電気自動車、電鉄、工作機械などにおいて大電流を制御するためのパワー半導体モジュールに関し、特にヒートシンクと一体化したパワー半導体モジュールに関する。 The present invention relates to a power semiconductor module for controlling a large current in an electric vehicle, electric railway, machine tool, and the like, and more particularly to a power semiconductor module integrated with a heat sink.
　図１１は、従来の半導体モジュールを模式的に示す断面図である。ここで、パワー半導体モジュール５は金属ベース板５０を備え、金属ベース板５０上にははんだ３３で絶縁基板６０が接合されている。絶縁基板６０は、絶縁板６１の両面に金属板６２，６３が接合された構成となっている。金属板６２は、回路パターンとして絶縁板６１上に選択的に設けられている。回路パターンとしての金属板６２には、半導体チップ４０がはんだ３４で接合されている。半導体チップ４０の表面に設けられた図示しない電極と金属板６２とはボンディングワイヤ８１で接続されている。また、金属ベース板５０の周縁には、半導体チップ４０等を囲むように、外部の部材に電気的に接続される外部接続端子８２がインサート成型された樹脂ケース７０が装着されている。樹脂ケース７０の内側には、シリコーンゲル７１およびエポキシ樹脂７２が充填され、半導体チップ４０等が封止されており、その上方には蓋７３が固定されている。 FIG. 11 is a cross-sectional view schematically showing a conventional semiconductor module. Here, the power semiconductor module 5 includes a metal base plate 50, and an insulating substrate 60 is joined to the metal base plate 50 with solder 33. The insulating substrate 60 has a configuration in which metal plates 62 and 63 are bonded to both surfaces of an insulating plate 61. The metal plate 62 is selectively provided on the insulating plate 61 as a circuit pattern. The semiconductor chip 40 is joined to the metal plate 62 as a circuit pattern by solder 34. An electrode (not shown) provided on the surface of the semiconductor chip 40 and the metal plate 62 are connected by a bonding wire 81. A resin case 70 in which an external connection terminal 82 that is electrically connected to an external member is insert-molded is mounted on the periphery of the metal base plate 50 so as to surround the semiconductor chip 40 and the like. The inside of the resin case 70 is filled with silicone gel 71 and epoxy resin 72, the semiconductor chip 40 and the like are sealed, and a lid 73 is fixed above it.
　このようなパワー半導体モジュール５は、ユーザー側で用意されるヒートシンク２０に放熱グリース９０を介してネジなどにより固定され、電気自動車、電鉄、工作機械などにおいて大電流を制御する部品として使用されている。放熱グリース９０は、パワー半導体モジュール５とヒートシンク２０との間に生じる隙間を埋め、この隙間に形成される空気層による熱伝導の妨げを抑制する機能を有し、半導体チップ４０で発生した熱をヒートシンク２０に伝えている（例えば、特許文献１（第７図）参照）。 Such a power semiconductor module 5 is fixed to a heat sink 20 prepared on the user side by means of screws or the like via a heat dissipating grease 90, and is used as a component for controlling a large current in an electric vehicle, an electric railway, a machine tool or the like. . The heat dissipating grease 90 fills a gap generated between the power semiconductor module 5 and the heat sink 20 and has a function of suppressing the heat conduction by the air layer formed in the gap, and the heat generated in the semiconductor chip 40 is reduced. This is transmitted to the heat sink 20 (see, for example, Patent Document 1 (FIG. 7)).
　しかしながら、パワー半導体モジュール５とヒートシンク２０との間に生じる隙間を放熱グリース９０で埋めることにより、次のような問題が生じる。この放熱グリース９０に接しているのは、パワー半導体モジュール５の金属ベース板５０と前述のヒートシンク２０である。一般的に、金属ベース板５０は銅（Ｃｕ）で形成されている。また、ヒートシンク２０はアルミニウム（Ａｌ）で形成されている。銅およびアルミニウムの熱伝導率はそれぞれ約３９０Ｗ／（ｍ・Ｋ）および約２２０Ｗ／（ｍ・Ｋ）である。これに対して、放熱グリース９０の熱伝導率は約１．０Ｗ／（ｍ・Ｋ）である。このように、放熱グリース９０の熱伝導率は、銅やアルミニウムなどの金属に比べて低い。このため、金属ベース板５０とヒートシンク２０との間において、放熱グリース９０の部分が大きな熱抵抗となる。 However, filling the gap formed between the power semiconductor module 5 and the heat sink 20 with the heat radiation grease 90 causes the following problems. The metal base plate 50 of the power semiconductor module 5 and the heat sink 20 described above are in contact with the heat radiating grease 90. In general, the metal base plate 50 is made of copper (Cu). The heat sink 20 is made of aluminum (Al). The thermal conductivities of copper and aluminum are about 390 W / (m · K) and about 220 W / (m · K), respectively. On the other hand, the thermal conductivity of the heat dissipating grease 90 is about 1.0 W / (m · K). Thus, the thermal conductivity of the heat dissipating grease 90 is lower than that of metals such as copper and aluminum. For this reason, between the metal base board 50 and the heat sink 20, the part of the thermal radiation grease 90 becomes a large thermal resistance.
　昨今、省エネやクリーンエネルギーが注目されており、風力発電や電気自動車が市場の牽引役となりつつある。これらの用途に使用されるパワー半導体モジュール５では大電流を制御し、半導体チップ４０が高温となるため、半導体チップ４０で発生した熱を効率良くヒートシンクに伝え、ヒートシンクを通してパワー半導体モジュール５の系外に放熱する必要がある。そのため、特に電気自動車用途においては、冷却方式として水冷却が採用されており、熱抵抗となる放熱グリース９０を省くため、ヒートシンク２０上に絶縁基板６０をはんだなどにより直接接合する構造がとられつつある（例えば、下記特許文献１（第１図）参照）。 Recently, energy saving and clean energy are attracting attention, and wind power generation and electric vehicles are becoming the market leader. In the power semiconductor module 5 used for these applications, since a large current is controlled and the semiconductor chip 40 becomes high temperature, the heat generated in the semiconductor chip 40 is efficiently transmitted to the heat sink, and the power semiconductor module 5 outside the system is transmitted through the heat sink. It is necessary to dissipate heat. Therefore, particularly in electric vehicle applications, water cooling is adopted as a cooling method, and a structure in which the insulating substrate 60 is directly joined to the heat sink 20 by solder or the like is being taken in order to omit the heat-dissipating grease 90 serving as heat resistance. (For example, see Patent Document 1 (FIG. 1) below).
　絶縁基板６０とヒートシンク２０とを直接接合する方法としては、例えばはんだによる接合が一般的である。また、フラックスを用いてはんだ付けをおこなう方法も公知である。 As a method for directly bonding the insulating substrate 60 and the heat sink 20, for example, bonding by solder is generally used. Also known is a method of soldering using a flux.
　また、接合材料どうしを接合する方法として、反応性多層金属箔を使用して半導体デバイスをプリント基板等に接合する方法が開示されている（例えば、下記特許文献２（第２２頁第３～８行）参照）。 Further, as a method for bonding bonding materials, there is disclosed a method for bonding a semiconductor device to a printed circuit board or the like using a reactive multilayer metal foil (for example, Patent Document 2 (page 22, pages 3 to 8) described below. Line)).
特開平９－２７５１７０号公報JP-A-9-275170 国際公開第０１／８３１８２号International Publication No. 01/83182
　しかしながら、絶縁基板６０とヒートシンク２０とを直接接合する場合、はんだ付けに際して、熱容量の大きいヒートシンク２０をはんだが溶融する温度以上（２５０～３５０℃程度）に加熱する必要がある。このため、はんだ付け時間が長くなり、生産効率が低下する。また、フラックスを用いてはんだ付けする場合、はんだ付け後に、体積の大きいヒートシンク２０の洗浄が必要となり、作業効率が低下する。 However, when the insulating substrate 60 and the heat sink 20 are directly joined, it is necessary to heat the heat sink 20 having a large heat capacity to a temperature higher than the temperature at which the solder melts (about 250 to 350 ° C.). For this reason, soldering time becomes long and production efficiency falls. Moreover, when soldering using a flux, after the soldering, it is necessary to clean the heat sink 20 having a large volume, and work efficiency is reduced.
　さらに、絶縁基板６０とヒートシンク２０とをはんだ付けした後にワイヤボンディングによりモジュール内の回路配線を実施する場合、ヒートシンク２０が絶縁基板６０に接合された状態でワイヤボンディングすることになる。この場合、例えば超音波を用いたワイヤボンディングでは、超音波の伝わりが不完全になり、シリコンチップとワイヤとの接合不良やシリコンチップへのダメージを引き起こすことが懸念される。 Further, when circuit wiring in the module is performed by wire bonding after the insulating substrate 60 and the heat sink 20 are soldered, wire bonding is performed in a state where the heat sink 20 is bonded to the insulating substrate 60. In this case, for example, in wire bonding using ultrasonic waves, there is a concern that the transmission of ultrasonic waves may be incomplete, resulting in poor bonding between the silicon chip and the wire or damage to the silicon chip.
　このように、パワー半導体モジュールの製造において、工程の初期段階で絶縁基板とヒートシンクとを接合し、続く工程でこのヒートシンクと一体となったモジュールを加工する場合、放熱性が悪くなるなど良品率の低下や製造コストの増大などを引き起こすという問題が生じる。 In this way, in the manufacture of power semiconductor modules, when the insulating substrate and the heat sink are joined at the initial stage of the process, and the module integrated with the heat sink is processed in the subsequent process, the heat dissipation becomes poor and the yield rate is good. There arises a problem of causing a decrease and an increase in manufacturing cost.
　本発明は、上述した従来技術による問題点を解消するため、放熱グリースを用いずに、金属ベース板とヒートシンクとを直接接合した半導体モジュールおよびその製造方法を提供することを目的とする。また、優れた放熱性能を備えた半導体モジュールおよびその製造方法を提供することを目的とする。また、製造コストを低減した半導体モジュールおよびその製造方法を提供することを目的とする。 The present invention has an object to provide a semiconductor module in which a metal base plate and a heat sink are directly joined without using a heat dissipating grease, and a method for manufacturing the same, in order to eliminate the above-described problems caused by the prior art. Moreover, it aims at providing the semiconductor module provided with the outstanding heat dissipation performance, and its manufacturing method. It is another object of the present invention to provide a semiconductor module with a reduced manufacturing cost and a manufacturing method thereof.
　上記の課題を解決し、本発明の目的を達成するため、請求項１の発明にかかる半導体モジュールは、ヒートシンクと、反応性金属箔を熱源として溶融、凝固したはんだ又はめっきにより前記ヒートシンクの一の主面に接合された半導体チップを含む部材と、を備えることを特徴とする。 In order to solve the above-described problems and achieve the object of the present invention, a semiconductor module according to the first aspect of the present invention includes a heat sink and one of the heat sinks formed by melting or solidifying solder or plating using a reactive metal foil as a heat source. And a member including a semiconductor chip bonded to the main surface.
　この請求項１の発明によれば、反応性金属箔の発する熱により瞬時に溶融された後に凝固したはんだ又はめっきによって、ヒートシンクと半導体チップを含む部材とが接合されている。 According to the first aspect of the present invention, the heat sink and the member including the semiconductor chip are joined together by solder or plating solidified after being instantaneously melted by the heat generated by the reactive metal foil.
　また、請求項２の発明にかかる半導体モジュールは、請求項１に記載の発明において、前記部材が、金属ベース板と、前記金属ベース板の一の主面に接合された絶縁基板と、前記絶縁基板の一の主面に接合された前記半導体チップと、を備え、前記金属ベース板の他の主面に前記ヒートシンクが接合されていることを特徴とする。 A semiconductor module according to a second aspect of the present invention is the semiconductor module according to the first aspect, wherein the member is a metal base plate, an insulating substrate joined to one main surface of the metal base plate, and the insulation. And a semiconductor chip bonded to one main surface of the substrate, wherein the heat sink is bonded to the other main surface of the metal base plate.
　この請求項２の発明によれば、反応性金属箔の発する熱により瞬時に溶融された後に凝固したはんだ又はめっきによって、ヒートシンクと半導体チップを含む部材の金属ベース板とが接合されている。 According to the second aspect of the present invention, the heat sink and the metal base plate of the member including the semiconductor chip are joined together by solder or plating solidified after being instantaneously melted by the heat generated by the reactive metal foil.
　また、請求項３の発明にかかる半導体モジュールは、請求項１に記載の発明において、前記部材が、絶縁基板と、前記絶縁基板の一の主面に接合された前記半導体チップと、を備え、前記絶縁基板の他の主面に前記ヒートシンクが接合されていることを特徴とする。 A semiconductor module according to a third aspect of the present invention is the semiconductor module according to the first aspect, wherein the member includes an insulating substrate and the semiconductor chip bonded to one main surface of the insulating substrate. The heat sink is bonded to the other main surface of the insulating substrate.
　この請求項３の発明によれば、反応性金属箔の発する熱により瞬時に溶融された後に凝固したはんだ又はめっきによって、ヒートシンクと半導体チップを含む部材の絶縁基板とが接合されている。 According to the third aspect of the present invention, the heat sink and the insulating substrate of the member including the semiconductor chip are joined together by solder or plating solidified after being instantaneously melted by the heat generated by the reactive metal foil.
　また、請求項４の発明にかかる半導体モジュールは、請求項１に記載の発明において、前記反応性金属箔は、ニッケルとアルミニウムが交互に積層されてなる積層膜であることを特徴とする。 Further, the semiconductor module according to the invention of claim 4 is characterized in that, in the invention of claim 1, the reactive metal foil is a laminated film in which nickel and aluminum are alternately laminated.
　この請求項４の発明によれば、ニッケルとアルミニウムが交互に積層されてなる反応性金属箔は、はんだ又はめっきを溶融する熱源として作用する。 According to the invention of claim 4, the reactive metal foil in which nickel and aluminum are alternately laminated acts as a heat source for melting solder or plating.
　また、請求項５の発明にかかる半導体モジュールは、請求項４に記載の発明において、前記反応性金属箔は、物理蒸着法によって積層された積層膜であることを特徴とする。 The semiconductor module according to the invention of claim 5 is characterized in that, in the invention of claim 4, the reactive metal foil is a laminated film laminated by a physical vapor deposition method.
　また、請求項６の発明にかかる半導体モジュールは、請求項４に記載の発明において、前記反応性金属箔の厚さが、０．０５ｍｍ以上０．１ｍｍ以下であることを特徴とする。 Further, the semiconductor module according to the invention of claim 6 is characterized in that, in the invention of claim 4, the thickness of the reactive metal foil is 0.05 mm or more and 0.1 mm or less.
　この請求項６の発明によれば、厚さが０．０５ｍｍ以上０．１ｍｍ以下である反応性金属箔は、はんだ又はめっきを溶融する熱源として作用し、ヒートシンクと半導体チップを含む部材とを接合する接合層を形成する。 According to the invention of claim 6, the reactive metal foil having a thickness of 0.05 mm or more and 0.1 mm or less acts as a heat source for melting the solder or plating, and joins the heat sink and the member including the semiconductor chip. A bonding layer is formed.
　また、請求項７の発明にかかる半導体モジュールは、請求項２に記載の発明において、前記絶縁基板は、絶縁板と、前記絶縁板の両面にそれぞれ接合された金属板とからなることを特徴とする。 According to a seventh aspect of the present invention, there is provided the semiconductor module according to the second aspect, wherein the insulating substrate includes an insulating plate and metal plates respectively bonded to both surfaces of the insulating plate. To do.
　また、請求項８の発明にかかる半導体モジュールは、請求項７に記載の発明において、前記絶縁板の厚さは、０．２ｍｍ以上１．０ｍｍ以下であることを特徴とする。 Further, the semiconductor module according to the invention of claim 8 is characterized in that, in the invention of claim 7, the thickness of the insulating plate is 0.2 mm or more and 1.0 mm or less.
　また、請求項９の発明にかかる半導体モジュールは、請求項７に記載の発明において、前記絶縁板は、アルミナ、ジルコニアが添加されたアルミナ、窒化珪素または窒化アルミニウムであることを特徴とする。 Further, the semiconductor module according to the invention of claim 9 is characterized in that, in the invention of claim 7, the insulating plate is alumina, alumina, silicon nitride or aluminum nitride to which alumina or zirconia is added.
　また、請求項１０の発明にかかる半導体モジュールは、請求項３に記載の発明において、前記絶縁基板は、絶縁板と、前記絶縁板の両面にそれぞれ接合された金属板とからなることを特徴とする。 According to a tenth aspect of the present invention, in the semiconductor module according to the third aspect, the insulating substrate includes an insulating plate and metal plates respectively bonded to both surfaces of the insulating plate. To do.
　また、請求項１１の発明にかかる半導体モジュールは、請求項１０に記載の発明において、前記絶縁板の厚さは、０．２ｍｍ以上１．０ｍｍ以下であることを特徴とする。 Further, the semiconductor module according to the invention of claim 11 is characterized in that, in the invention of claim 10, the thickness of the insulating plate is 0.2 mm or more and 1.0 mm or less.
　また、請求項１２の発明にかかる半導体モジュールは、請求項１０に記載の発明において、前記絶縁板は、アルミナ、ジルコニアが添加されたアルミナ、窒化珪素または窒化アルミニウムであることを特徴とする。 The semiconductor module according to a twelfth aspect of the invention is characterized in that, in the invention according to the tenth aspect, the insulating plate is alumina, silicon nitride or aluminum nitride to which alumina or zirconia is added.
　また、請求項１３の発明にかかる半導体モジュールは、請求項７～１２のいずれか一つに記載の発明において、前記金属板は、銅、銅合金、アルミニウムまたはアルミニウム合金であることを特徴とする。 A semiconductor module according to a thirteenth aspect of the present invention is the semiconductor module according to any one of the seventh to twelfth aspects, wherein the metal plate is copper, a copper alloy, aluminum, or an aluminum alloy. .
　また、請求項１４の発明にかかる半導体モジュールは、請求項１に記載の発明において、前記ヒートシンクは、銅、銅合金、アルミニウム、アルミニウム合金、銅－モリブデンまたはアルミニウム－炭化珪素であることを特徴とする。 The semiconductor module according to claim 14 is the semiconductor module according to claim 1, wherein the heat sink is copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum, or aluminum-silicon carbide. To do.
　また、請求項１５の発明にかかる半導体モジュールは、請求項１４に記載の発明において、前記ヒートシンクの表面は、ニッケルめっき、金めっき又はスズめっきが施されることを特徴とする。 Further, the semiconductor module according to the invention of claim 15 is characterized in that, in the invention of claim 14, the surface of the heat sink is subjected to nickel plating, gold plating or tin plating.
　また、請求項１６の発明にかかる半導体モジュールは、請求項２に記載の発明において、前記金属ベース板は、銅、銅合金、アルミニウム、アルミニウム合金、銅－モリブデン合金、鉄または鉄合金であることを特徴とする。 According to a sixteenth aspect of the present invention, in the semiconductor module according to the second aspect, the metal base plate is made of copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum alloy, iron or iron alloy. It is characterized by.
　また、請求項１７の発明にかかる半導体モジュールは、請求項１６に記載の発明において、前記金属ベース板の表面は、ニッケルめっき、金めっき又はスズめっきが施されていることを特徴とする。 The semiconductor module according to the invention of claim 17 is characterized in that, in the invention of claim 16, the surface of the metal base plate is subjected to nickel plating, gold plating or tin plating.
　また、請求項１８の発明にかかる半導体モジュールは、請求項２に記載の発明において、前記半導体チップと絶縁基板、および絶縁基板と金属ベース板は、それぞれはんだにより接合されていることを特徴とする。 According to an eighteenth aspect of the present invention, in the semiconductor module according to the second aspect, the semiconductor chip and the insulating substrate, and the insulating substrate and the metal base plate are respectively joined by solder. .
　また、請求項１９の発明にかかる半導体モジュールは、請求項３に記載の発明において、前記半導体チップと絶縁基板は、はんだにより接合されていることを特徴とする。 Further, the semiconductor module according to the invention of claim 19 is characterized in that, in the invention of claim 3, the semiconductor chip and the insulating substrate are joined by solder.
　また、請求項２０の発明にかかる半導体モジュールは、請求項１８または１９に記載の発明において、前記絶縁基板と他の部材とを接合する前記はんだは、反応性金属箔を熱源として溶融、凝固したはんだであることを特徴とする。 The semiconductor module according to claim 20 is the semiconductor module according to claim 18 or 19, wherein the solder for joining the insulating substrate and another member is melted and solidified using a reactive metal foil as a heat source. It is characterized by being solder.
　また、請求項２１の発明にかかる半導体モジュールは、請求項１８または１９に記載の発明において、前記はんだの主成分は、スズ－鉛合金、スズ－銀合金、スズ－ビスマス合金、スズ－アンチモン合金、スズ－銅合金またはスズ－インジウム合金であることを特徴とする。 The semiconductor module according to claim 21 is the semiconductor module according to claim 18 or 19, wherein the main component of the solder is tin-lead alloy, tin-silver alloy, tin-bismuth alloy, tin-antimony alloy. And a tin-copper alloy or a tin-indium alloy.
　また、上記の課題を解決し、本発明の目的を達成するため、請求項２２の発明にかかる半導体モジュールの製造方法は、絶縁基板の一の主面に半導体チップを接合する第１の工程と、前記半導体チップにワイヤもしくはリードフレームを接合する第２の工程と、前記第１の工程および前記第２の工程の後、反応性金属箔を熱源としてはんだ又はめっきを溶融、凝固させ、前記絶縁基板の他の主面側にヒートシンクを接合する第３の工程と、を備えることを特徴とする。 In order to solve the above problems and achieve the object of the present invention, a semiconductor module manufacturing method according to the invention of claim 22 includes a first step of bonding a semiconductor chip to one main surface of an insulating substrate. After the second step of bonding a wire or a lead frame to the semiconductor chip, and after the first step and the second step, the solder or plating is melted and solidified using a reactive metal foil as a heat source, and the insulation is performed. And a third step of bonding a heat sink to the other main surface side of the substrate.
　この請求項２２の発明によれば、反応性金属箔を熱源として用いることにより、第１の工程および第２の工程が終了した後、第３の工程において絶縁基板の他の主面側にヒートシンクを接合することができる。 According to the twenty-second aspect of the present invention, by using the reactive metal foil as a heat source, after the first step and the second step are finished, the heat sink is formed on the other main surface side of the insulating substrate in the third step. Can be joined.
　また、請求項２３の発明にかかる半導体モジュールの製造方法は、請求項２２に記載の発明において、前記第１の工程において、前記絶縁基板の他の主面に金属ベース板を接合し、前記第３の工程において、前記金属ベース板に前記ヒートシンクを接合することを特徴とする。 According to a twenty-third aspect of the present invention, there is provided a method for manufacturing a semiconductor module according to the twenty-second aspect of the present invention, wherein, in the first step, a metal base plate is joined to the other main surface of the insulating substrate. In step 3, the heat sink is bonded to the metal base plate.
　この請求項２３の発明によれば、第１の工程において、絶縁基板には金属ベース板が接合される。そして、第３の工程において、絶縁基板は、反応性金属箔を熱源として溶融されたはんだ又はめっきにより、金属ベース板を介してヒートシンクに接合される。 According to the invention of claim 23, in the first step, the metal base plate is bonded to the insulating substrate. In the third step, the insulating substrate is bonded to the heat sink through the metal base plate by solder or plating melted using the reactive metal foil as a heat source.
　また、請求項２４の発明にかかる半導体モジュールの製造方法は、請求項２２に記載の発明において、前記第３の工程において、前記絶縁基板に前記ヒートシンクを接合することを特徴とする。 Further, the semiconductor module manufacturing method according to the invention of claim 24 is characterized in that, in the invention of claim 22, in the third step, the heat sink is joined to the insulating substrate.
　この請求項２４の発明によれば、第３の工程において、絶縁基板は、反応性金属箔を熱源として溶融されたはんだ又はめっきにより、ヒートシンクに直接接合される。 According to the invention of claim 24, in the third step, the insulating substrate is directly joined to the heat sink by molten solder or plating using the reactive metal foil as a heat source.
　上述した請求項１～２１の発明によれば、ヒートシンクと半導体チップを含む部材との接合に、それ自体が熱源（イグナイタ）となる反応性金属箔を用いる。これにより、ヒートシンクと半導体チップを含む部材とを外部から加熱等することなく、室温で瞬時に接合することができる。また、グリース等を用いずに、反応性金属箔を熱源として溶融された後に凝固したはんだ又はめっきにより、ヒートシンクと半導体チップを含む部材とを接合する。これにより、ヒートシンクと半導体チップを含む部材との間の熱抵抗を小さくできる。このため、効率的に、放熱性に優れたヒートシンク一体型パワー半導体モジュールを提供することができる。さらに、反応性金属箔を用いることにより、複数の半導体チップを含む部材を電気特性試験によって選別した後、良品のみをヒートシンクと接合することも可能となる。このため、良品率が高く、かつ放熱性に優れたヒートシンク一体型パワー半導体モジュールを提供することができる。 According to the inventions of claims 1 to 21 described above, a reactive metal foil that itself becomes a heat source (igniter) is used for joining the heat sink and the member including the semiconductor chip. Thus, the heat sink and the member including the semiconductor chip can be bonded instantaneously at room temperature without heating from the outside. Further, without using grease or the like, the heat sink and the member including the semiconductor chip are joined by solder or plating solidified after being melted using the reactive metal foil as a heat source. Thereby, the thermal resistance between the heat sink and the member including the semiconductor chip can be reduced. For this reason, the heat sink integrated power semiconductor module excellent in heat dissipation can be provided efficiently. Furthermore, by using a reactive metal foil, it becomes possible to join only non-defective products to the heat sink after selecting a member including a plurality of semiconductor chips by an electrical characteristic test. For this reason, a heat sink integrated power semiconductor module having a high non-defective rate and excellent heat dissipation can be provided.
　また、上述した請求項２２～２４の発明によれば、半導体チップを含む部材を組み立てる第１の工程および第２の工程の後、この工程とは別に、それ自体が熱源となる反応性金属箔を用いてヒートシンクと半導体チップを含む部材を接合する第３の工程をおこなう。このため、接合のためにヒートシンク全体を外部から加熱する必要がなく、製造工程の簡素化、効率化を実現することができる。また、グリース等を用いないので、放熱性に優れたヒートシンク一体型パワー半導体モジュールの製造方法を提供することができる。さらに、第１の工程および第２の工程により作製された半導体装置の電気特性を試験する工程をおこなった後に、反応性金属箔を用いて接合する第３の工程を実施することにより、良品率が高いヒートシンク一体型パワー半導体モジュールの製造方法を提供することができる。 Further, according to the inventions of claims 22 to 24 described above, after the first step and the second step of assembling the member including the semiconductor chip, separately from this step, the reactive metal foil which itself becomes a heat source A third step of joining the heat sink and the member including the semiconductor chip is performed by using. For this reason, it is not necessary to heat the whole heat sink from the outside for joining, and the simplification and efficiency of the manufacturing process can be realized. Further, since no grease or the like is used, it is possible to provide a method for manufacturing a heat sink integrated power semiconductor module having excellent heat dissipation. Furthermore, after performing the process which tests the electrical property of the semiconductor device produced by the 1st process and the 2nd process, and performing the 3rd process joined using reactive metal foil, yield rate It is possible to provide a method for manufacturing a power semiconductor module with a high heat sink.
　本発明にかかる半導体モジュールおよびその製造方法によれば、放熱グリースを用いずに、金属ベース板とヒートシンクとを直接接合することができるという効果を奏する。また、放熱性能を高めることができるという効果を奏する。また、コストを低減することができるという効果を奏する。 According to the semiconductor module and the manufacturing method thereof according to the present invention, there is an effect that the metal base plate and the heat sink can be directly joined without using the heat radiating grease. Moreover, there exists an effect that heat dissipation performance can be improved. Moreover, there exists an effect that cost can be reduced.
図１は、実施の形態１にかかる半導体モジュールの要部を模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing a main part of the semiconductor module according to the first embodiment. 図２は、実施の形態１にかかる半導体モジュールの製造方法を示すフローチャートである。FIG. 2 is a flowchart of the semiconductor module manufacturing method according to the first embodiment. 図３は、実施の形態２にかかる半導体モジュールの要部を模式的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing a main part of the semiconductor module according to the second embodiment. 図４は、実施の形態３にかかる半導体モジュールの要部を模式的に示す断面図である。FIG. 4 is a cross-sectional view schematically showing a main part of the semiconductor module according to the third embodiment. 図５は、実施の形態４にかかる半導体モジュールの要部を模式的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a main part of the semiconductor module according to the fourth embodiment. 図６は、はんだの厚さと接合性およびはみ出しの関係を示す説明図である。FIG. 6 is an explanatory diagram showing the relationship between solder thickness, bondability, and protrusion. 図７は、絶縁基板および金属ベース板が反った状態を模式的に示す断面図である。FIG. 7 is a cross-sectional view schematically showing a state where the insulating substrate and the metal base plate are warped. 図８は、絶縁基板の厚さと金属ベース板－ヒートシンク間の隙間量との関係を示す特性図である。FIG. 8 is a characteristic diagram showing the relationship between the thickness of the insulating substrate and the amount of gap between the metal base plate and the heat sink. 図９は、金属ベース板－ヒートシンク間の隙間量とはんだの厚さとの関係を示す特性図である。FIG. 9 is a characteristic diagram showing the relationship between the amount of the gap between the metal base plate and the heat sink and the thickness of the solder. 図１０は、ヒートシンク熱伝導率と熱抵抗との関係を示す特性図である。FIG. 10 is a characteristic diagram showing the relationship between heat sink thermal conductivity and thermal resistance. 図１１は、従来の半導体モジュールを模式的に示す断面図である。FIG. 11 is a cross-sectional view schematically showing a conventional semiconductor module.
　以下に添付図面を参照して、この発明にかかるヒートシンク一体型の電力変換用パワー半導体モジュールおよびその製造方法の好適な実施の形態を詳細に説明する。なお、以下の実施の形態の説明および添付図面において、同じ機能を有する部材および同様の構成には同一の符号を付し、重複する説明を省略する。 DETAILED DESCRIPTION Exemplary embodiments of a heat sink integrated power semiconductor module for power conversion and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, members having the same function and similar configurations are denoted by the same reference numerals, and redundant description is omitted.
　また、本発明を実施するための最良の形態は、電気特性試験を終了した半導体装置とヒートシンクとの間に反応性金属箔とはんだ板を重ねて挿入した状態で、反応性金属箔を熱源として発火させることによりはんだ板を溶融させた後に凝固させ、例えば室温で瞬時に接合させることである。ここで、電気特性試験は、少なくとも半導体チップの表面に設けられた電極と、絶縁基板上に形成された回路パターンとがボンディングワイヤで接続された半導体装置に対して行われる。 The best mode for carrying out the present invention is to use the reactive metal foil as a heat source in a state where the reactive metal foil and the solder plate are inserted between the semiconductor device and the heat sink after the electrical property test is completed. It is to solidify after melting a solder plate by igniting, for example, instantly joining at room temperature. Here, the electrical characteristic test is performed on a semiconductor device in which at least an electrode provided on the surface of the semiconductor chip and a circuit pattern formed on the insulating substrate are connected by a bonding wire.
（実施の形態１）
　図１は、実施の形態１にかかる半導体モジュールの要部を模式的に示す断面図である。実施の形態１にかかるヒートシンク一体型のパワー半導体モジュール１は、主に、半導体装置１０と、ヒートシンク２０とからなる。半導体装置１０は、半導体チップ４０を含む部材である。半導体装置１０は、ヒートシンク２０の一方の主面に、反応性金属箔３０を熱源として溶融された後に凝固したはんだ３１，３２により接合されている。反応性金属箔３０とは、例えば電流を流すなどにより刺激を与えたときに自己発火する金属箔である。 (Embodiment 1)
FIG. 1 is a cross-sectional view schematically showing a main part of the semiconductor module according to the first embodiment. The heat sink integrated power semiconductor module 1 according to the first embodiment mainly includes a semiconductor device 10 and a heat sink 20. The semiconductor device 10 is a member including the semiconductor chip 40. The semiconductor device 10 is joined to one main surface of the heat sink 20 by solders 31 and 32 that are solidified after being melted using the reactive metal foil 30 as a heat source. The reactive metal foil 30 is a metal foil that self-ignites when a stimulus is applied, for example, by passing an electric current.
　具体的には、半導体装置１０およびヒートシンク２０は、次のように接合されている。半導体装置１０は、半導体チップ４０と、絶縁基板６０と、金属ベース板５０とを備える。半導体チップ４０は、はんだ３４により絶縁基板６０の一方の主面に接合されている。詳細には、絶縁基板６０は、絶縁板６１の両面に金属板６２，６３が接合された構成となっている。金属板６２は、回路パターンとして絶縁板６１上に選択的に設けられている。そして、半導体チップ４０は、はんだ３４により、回路パターンとしての金属板６２に接合されている。 Specifically, the semiconductor device 10 and the heat sink 20 are joined as follows. The semiconductor device 10 includes a semiconductor chip 40, an insulating substrate 60, and a metal base plate 50. The semiconductor chip 40 is bonded to one main surface of the insulating substrate 60 by solder 34. Specifically, the insulating substrate 60 has a configuration in which metal plates 62 and 63 are bonded to both surfaces of the insulating plate 61. The metal plate 62 is selectively provided on the insulating plate 61 as a circuit pattern. The semiconductor chip 40 is joined to a metal plate 62 as a circuit pattern by solder 34.
　絶縁基板６０は、はんだ３３により金属ベース板５０の一方の主面に接合されている。詳細には、絶縁基板６０の他方の主面に接合された金属板６３は、はんだ３３により金属ベース板５０に接合されている。ヒートシンク２０は、金属ベース板５０の、絶縁基板６０が接合された主面（一の主面）に対して反対側の主面（他の主面）に、はんだ３１，３２により接合されている。はんだ３１とはんだ３２の間には、はんだ３１，３２の熱源として、反応性金属箔３０が挟まれている。 The insulating substrate 60 is joined to one main surface of the metal base plate 50 by solder 33. Specifically, the metal plate 63 bonded to the other main surface of the insulating substrate 60 is bonded to the metal base plate 50 by the solder 33. The heat sink 20 is bonded to the main surface (the other main surface) of the metal base plate 50 opposite to the main surface (one main surface) to which the insulating substrate 60 is bonded by solders 31 and 32. . A reactive metal foil 30 is sandwiched between the solder 31 and the solder 32 as a heat source for the solders 31 and 32.
　つまり、半導体装置１０およびヒートシンク２０からなるパワー半導体モジュール１は、ヒートシンク２０側からヒートシンク２０、はんだ３１、反応性金属箔３０、はんだ３２、金属ベース板５０、はんだ３３、絶縁基板６０（金属板６３、絶縁板６１および金属板６２の順に接合）、はんだ３４および半導体チップ４０の順に重ねられた状態で接合されている。 That is, the power semiconductor module 1 including the semiconductor device 10 and the heat sink 20 includes the heat sink 20, the solder 31, the reactive metal foil 30, the solder 32, the metal base plate 50, the solder 33, the insulating substrate 60 (the metal plate 63) from the heat sink 20 side. , The insulating plate 61 and the metal plate 62 are joined in this order), the solder 34 and the semiconductor chip 40 are joined in this order.
　また、パワー半導体モジュール１は、半導体チップ４０の表面に設けられた図示しない電極と金属板（回路パターン）６２とを電気的に接続するボンディングワイヤ８１と、外部の部材に電気的に接続される外部接続端子８２と、半導体チップ４０等を囲み、かつ金属ベース板５０の周縁に固定された樹脂ケース７０と、樹脂ケース７０内に充填されたシリコーンゲル７１と、シリコーンゲル７１の上部に注入されたエポキシ樹脂７２と、蓋７３と、を備える。 In addition, the power semiconductor module 1 is electrically connected to an external member and a bonding wire 81 that electrically connects an electrode (not shown) provided on the surface of the semiconductor chip 40 and a metal plate (circuit pattern) 62. A resin case 70 that surrounds the external connection terminal 82, the semiconductor chip 40, etc. and is fixed to the periphery of the metal base plate 50, a silicone gel 71 filled in the resin case 70, and an upper portion of the silicone gel 71 The epoxy resin 72 and the lid 73 are provided.
　金属板６２と外部接続端子８２は、ボンディングワイヤ８１により接続されている。樹脂ケース７０内側において、半導体チップ４０、金属板６２およびボンディングワイヤ８１などは、シリコーンゲル７１により封止されている。エポキシ樹脂７２は、シリコーンゲル７１を覆う。また、エポキシ樹脂７２の端部は、樹脂ケース７０に接している。蓋７３は、シリコーンゲル７１およびエポキシ樹脂７２の上に設けられ、シリコーンゲル７１およびエポキシ樹脂７２を固定する。樹脂ケース７０の断面形状は、例えばＬ字形状であってもよい。外部接続端子８２の断面形状は、例えばＬ字形状であってもよい。 The metal plate 62 and the external connection terminal 82 are connected by a bonding wire 81. Inside the resin case 70, the semiconductor chip 40, the metal plate 62, the bonding wire 81, and the like are sealed with a silicone gel 71. The epoxy resin 72 covers the silicone gel 71. Further, the end portion of the epoxy resin 72 is in contact with the resin case 70. The lid 73 is provided on the silicone gel 71 and the epoxy resin 72 and fixes the silicone gel 71 and the epoxy resin 72. The cross-sectional shape of the resin case 70 may be, for example, an L shape. The cross-sectional shape of the external connection terminal 82 may be L-shaped, for example.
　ここで、半導体チップ４０には、例えば、大電力を有し、かつ高速スイッチングを可能とするパワー半導体素子が形成されている。具体的には、半導体チップ４０には、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ：Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）や、ＩＧＢＴチップのオフ動作時に発生する誘起電流を環流させるＦＷＤ（フリーホイーリングダイオード：Ｆｒｅｅ　Ｗｈｅｅｌｉｎｇ　Ｄｉｏｄｅ）などが形成されていてもよい。 Here, for example, a power semiconductor element having a large electric power and capable of high-speed switching is formed on the semiconductor chip 40. Specifically, the semiconductor chip 40 includes an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode) that circulates an induced current generated when the IGBT chip is turned off. Etc. may be formed.
　絶縁基板６０は、上述したように、例えばセラミック製の絶縁板６１の半導体チップ４０側の主面と金属ベース板５０の主面（両面）に、それぞれ金属板６２，６３を接合して構成されている。例えば、絶縁基板６０は、ＤＣＢ（Ｄｉｒｅｃｔ　Ｃｏｐｐｅｒ　Ｂｏｎｄｉｎｇ）基板である。 As described above, the insulating substrate 60 is configured, for example, by bonding the metal plates 62 and 63 to the main surface of the ceramic insulating plate 61 on the semiconductor chip 40 side and the main surface (both surfaces) of the metal base plate 50, respectively. ing. For example, the insulating substrate 60 is a DCB (Direct Copper Bonding) substrate.
　絶縁板６１の一方の主面に形成された金属板６２には、回路パターン加工が施されている。絶縁基板６０の厚さは０．６ｍｍ以上２．０ｍｍ以下である。絶縁板６１の材質は、各種セラミックス、好ましくは、アルミナ（Ａｌ2Ｏ3）、ジルコニア（ＺｒＯ2）が添加されたアルミナ、窒化珪素（Ｓｉ3Ｎ4）または窒化アルミニウム（ＡｌＮ）である。また、絶縁板６１の厚さは、０．２ｍｍ以上１．０ｍｍ以下であり、好ましくは０．２ｍｍ以上０．６ｍｍ以下であるのがよい。金属板６２，６３は、銅、銅合金、アルミニウムまたはアルミニウム合金であってもよい。 The metal plate 62 formed on one main surface of the insulating plate 61 is subjected to circuit pattern processing. The thickness of the insulating substrate 60 is 0.6 mm or more and 2.0 mm or less. The material of the insulating plate 61 is various ceramics, preferably alumina (Al 2 O 3 ), alumina to which zirconia (ZrO 2 ) is added, silicon nitride (Si 3 N 4 ), or aluminum nitride (AlN). The thickness of the insulating plate 61 is not less than 0.2 mm and not more than 1.0 mm, preferably not less than 0.2 mm and not more than 0.6 mm. The metal plates 62 and 63 may be copper, a copper alloy, aluminum, or an aluminum alloy.
　金属ベース板５０は、銅、銅合金、純アルミニウム、アルミニウム合金、銅－モリブデン（Ｍｏ）合金、純鉄（Ｆｅ）または鉄合金からなる。さらに、金属ベース板５０の表面は、ニッケル（Ｎｉ）めっき、金（Ａｕ）めっきまたはスズ（Ｓｎ）めっきが施されているのが好ましい。 The metal base plate 50 is made of copper, copper alloy, pure aluminum, aluminum alloy, copper-molybdenum (Mo) alloy, pure iron (Fe), or iron alloy. Further, the surface of the metal base plate 50 is preferably subjected to nickel (Ni) plating, gold (Au) plating, or tin (Sn) plating.
　ヒートシンク２０は、例えば銅、銅合金、アルミニウム、アルミニウム合金、銅－モリブデンまたはアルミニウム－炭化珪素（ＳｉＣ）のいずれかからなる。さらに、ヒートシンク２０の表面は、ニッケルめっき、金めっきまたはスズめっきが施されているのが好ましい。また、ヒートシンク２０は、ヒートシンク２０の表面積を広くする形状を有するフィン（不図示）を備えていてもよい。フィンの形状は、例えば、板状、波状、カルゲート等いずれの形状であってもよい。 The heat sink 20 is made of, for example, copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum, or aluminum-silicon carbide (SiC). Furthermore, the surface of the heat sink 20 is preferably subjected to nickel plating, gold plating or tin plating. The heat sink 20 may include fins (not shown) having a shape that increases the surface area of the heat sink 20. The shape of the fin may be any shape such as a plate shape, a wave shape, and a culgate.
　はんだ３１，３２，３３，３４は、スズ－鉛（Ｐｂ）合金、スズ－銀（Ａｇ）合金、スズ－ビスマス（Ｂｉ）合金、スズ－アンチモン（Ｓｂ）合金、スズ－銅合金、スズ－インジウム（Iｎ）合金のいずれかを主成分として含み、かつ添加剤や不可避的な不純物を含む。半導体装置１０とヒートシンク２０を接合するはんだ３１，３２は、Ｓｎ－Ｓｂ合金であるのが好ましい。はんだ３１，３２の厚さは０．２ｍｍ以上０．５ｍｍ以下が好ましい。その理由は、後述する。 Solder 31, 32, 33, 34 are tin-lead (Pb) alloy, tin-silver (Ag) alloy, tin-bismuth (Bi) alloy, tin-antimony (Sb) alloy, tin-copper alloy, tin-indium (In) One of the alloys is included as a main component, and an additive or an unavoidable impurity is included. The solders 31 and 32 that join the semiconductor device 10 and the heat sink 20 are preferably Sn—Sb alloys. The thickness of the solders 31 and 32 is preferably 0.2 mm or more and 0.5 mm or less. The reason will be described later.
　反応性金属箔３０は、ニッケル層とアルミニウム層を真空蒸着やスパッタリング等の物理蒸着法（ＰＶＤ：Ｐｈｙｓｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）により交互に積層した積層膜である。反応性金属箔３０として、例えば、ＮａｎｏＦｏｉｌ（登録商標）の商品名でＲｅａｃｔｉｖｅ　ＮａｎｏＴｅｃｈｎｏｌｏｇｉｅｓ社より提供されている金属箔を用いてもよい。反応性金属箔３０の厚さは、好ましくは０．０５ｍｍ以上０．１ｍｍ以下である。 The reactive metal foil 30 is a laminated film in which nickel layers and aluminum layers are alternately laminated by a physical vapor deposition method (PVD: Physical Vapor Deposition) such as vacuum vapor deposition or sputtering. As the reactive metal foil 30, for example, a metal foil provided by Reactive Nano Technologies, Inc. under the trade name NanoFoil (registered trademark) may be used. The thickness of the reactive metal foil 30 is preferably 0.05 mm or more and 0.1 mm or less.
　反応性金属箔３０を熱源として用いることで、自己発火する反応性金属箔３０によりはんだ３１，３２が瞬時に溶融される。そして、ヒートシンク２０とはんだ３１の界面では、溶解されたはんだ３１が凝固することで、ヒートシンク２０と金属接合され一体化する。はんだ３２と金属ベース板５０の界面では、溶解されたはんだ３２が凝固することで、金属ベース板５０と金属接合され一体化する。この結果、ヒートシンク２０と金属ベース板５０は、はんだ３１、反応性金属箔３０、はんだ３２の３層構造の接合層で接合される。なお、熱源として作用した反応性金属箔３０は、例えばそれがニッケル膜とアルミニウム膜を積層したものである場合は、アルミニウム－ニッケル合金の接合層となる。 By using the reactive metal foil 30 as a heat source, the solders 31 and 32 are instantaneously melted by the reactive metal foil 30 that self-ignites. The melted solder 31 is solidified at the interface between the heat sink 20 and the solder 31 so that the heat sink 20 is metal-bonded and integrated. At the interface between the solder 32 and the metal base plate 50, the melted solder 32 is solidified to be metal-bonded and integrated with the metal base plate 50. As a result, the heat sink 20 and the metal base plate 50 are joined by a three-layer joining layer of the solder 31, the reactive metal foil 30, and the solder 32. Note that the reactive metal foil 30 that has acted as a heat source becomes an aluminum-nickel alloy bonding layer, for example, when it is a laminate of a nickel film and an aluminum film.
　次に、上述したパワー半導体モジュール１の製造方法について説明する。図２は、実施の形態１にかかるパワー半導体モジュールの製造方法を示すフローチャートである。まず、金属ベース板５０の一方の主面に、絶縁板６１および金属板６２，６３からなる絶縁基板６０の金属板６３側の主面（他方の主面）をはんだ３３により接合する。さらに、絶縁基板６０の一方の主面の金属板６２上に半導体チップ４０をはんだ３４により接合する（ステップＳ１）。 Next, a method for manufacturing the power semiconductor module 1 described above will be described. FIG. 2 is a flowchart of the method for manufacturing the power semiconductor module according to the first embodiment. First, the main surface on the metal plate 63 side (the other main surface) of the insulating substrate 60 composed of the insulating plate 61 and the metal plates 62 and 63 is joined to one main surface of the metal base plate 50 by the solder 33. Further, the semiconductor chip 40 is joined to the metal plate 62 on one main surface of the insulating substrate 60 by the solder 34 (step S1).
　通常、はんだ３３，３４による金属ベース板５０と半導体チップ４０との接合（固着）は同時に行われる。すなわち、金属ベース板５０の上面に、はんだ３３、絶縁基板６０、はんだ３４および半導体チップ４０をこの順に重ね、これらを窒素（Ｎ2）又は水素（Ｈ2）ガスで還元された雰囲気中で加熱する。はんだ３３，３４が溶融したら真空引きをおこない、はんだ層中に残存する気泡を除去する。そして、所定時間後、上記重ね合わせた部材を冷却してはんだ３３，３４を再凝固する。これにより、金属ベース板５０、絶縁基板６０および半導体チップ４０がこの順に重なった状態で接合される。 Usually, joining (fixing) of the metal base plate 50 and the semiconductor chip 40 with the solders 33 and 34 is performed simultaneously. That is, the solder 33, the insulating substrate 60, the solder 34, and the semiconductor chip 40 are stacked in this order on the upper surface of the metal base plate 50, and these are heated in an atmosphere reduced with nitrogen (N 2 ) or hydrogen (H 2 ) gas. To do. When the solders 33 and 34 are melted, evacuation is performed to remove bubbles remaining in the solder layer. Then, after a predetermined time, the stacked members are cooled to resolidify the solders 33 and 34. As a result, the metal base plate 50, the insulating substrate 60, and the semiconductor chip 40 are joined in a state of overlapping in this order.
　次に、樹脂ケース７０と金属ベース板５０を接着する（ステップＳ２）。具体的には、外部接続端子８２がインサート成型またはアウトサート成型された樹脂ケース７０（外囲器）を、接着剤を用いて金属ベース板５０の周縁に嵌合して固定する。 Next, the resin case 70 and the metal base plate 50 are bonded (step S2). Specifically, the resin case 70 (envelope) in which the external connection terminals 82 are insert-molded or outsert-molded is fitted and fixed to the periphery of the metal base plate 50 using an adhesive.
　次に、半導体チップ４０上に形成された表面電極、金属板６２および外部接続端子８２をボンディングワイヤ８１またはリードフレームによって電気的に接続する。また、その他の電極、所定の回路を構成するように電気的に接続する。例えば、半導体チップ４０上にＩＧＢＴが形成されている場合、エミッタ電極、コレクタ電極およびゲート電極を、所定の回路を構成するように電気的に接続する。 Next, the surface electrode, the metal plate 62 and the external connection terminal 82 formed on the semiconductor chip 40 are electrically connected by the bonding wire 81 or the lead frame. In addition, other electrodes are electrically connected to form a predetermined circuit. For example, when an IGBT is formed on the semiconductor chip 40, the emitter electrode, the collector electrode, and the gate electrode are electrically connected to form a predetermined circuit.
　その後、樹脂ケース７０内にシリコーンゲル７１を充填する。そして、シリコーンゲル７１の上部をエポキシ樹脂７２で覆う。さらに、シリコーンゲル７１およびエポキシ樹脂７２の上に蓋７３を設けて、シリコーンゲル７１およびエポキシ樹脂７２を固定する（ステップＳ３）。 Thereafter, the silicone gel 71 is filled in the resin case 70. Then, the upper part of the silicone gel 71 is covered with an epoxy resin 72. Further, a lid 73 is provided on the silicone gel 71 and the epoxy resin 72 to fix the silicone gel 71 and the epoxy resin 72 (step S3).
　これにより、半導体チップ４０が実装された半導体装置１０が完成する。半導体装置１０の組み立てが終了したら、必要に応じて、半導体装置１０に構成された回路の電気的特性や、動作特性試験をおこなう（ステップＳ４）。 Thereby, the semiconductor device 10 on which the semiconductor chip 40 is mounted is completed. When the assembly of the semiconductor device 10 is completed, the electrical characteristics and the operation characteristics test of the circuit configured in the semiconductor device 10 are performed as necessary (step S4).
　最後に、ヒートシンク２０を用意し、このヒートシンク２０の一方の主面に、はんだ３１、反応性金属箔３０およびはんだ３２をこの順に重ね、はんだ３２の上に、半導体装置１０の金属ベース板５０の他方の主面がヒートシンク２０側になるように半導体装置１０を重ねる。そして、例えば、はんだ３１，３２の全体に均等に圧力が加わるように、これら積み重ねた部材の半導体装置１０側およびヒートシンク２０側から加圧する。この状態で反応性金属箔３０に電流を流し、刺激を与えて自己発火させることにより、はんだ３１，３２を溶融させる。これにより、絶縁基板６０の他方の主面側において、半導体装置１０の金属ベース板５０がヒートシンク２０に接合され、ヒートシンク一体型のパワー半導体モジュール１が完成する（ステップＳ５）。 Finally, the heat sink 20 is prepared, and the solder 31, the reactive metal foil 30 and the solder 32 are stacked in this order on one main surface of the heat sink 20, and the metal base plate 50 of the semiconductor device 10 is placed on the solder 32. The semiconductor devices 10 are stacked so that the other main surface is on the heat sink 20 side. Then, for example, the stacked members are pressed from the semiconductor device 10 side and the heat sink 20 side so that pressure is uniformly applied to the entire solders 31 and 32. In this state, an electric current is passed through the reactive metal foil 30 to cause irritation and self-ignition, thereby melting the solders 31 and 32. Thereby, the metal base plate 50 of the semiconductor device 10 is joined to the heat sink 20 on the other main surface side of the insulating substrate 60, and the heat semiconductor integrated power semiconductor module 1 is completed (step S5).
　以上、説明したように、実施の形態１によれば、ヒートシンク２０と半導体装置１０との接合に、それ自体が熱源（イグナイタ）となる反応性金属箔３０を用いる。これにより、ヒートシンク２０と半導体装置１０とを外部から加熱等することなく、室温で瞬時に接合することができる。また、グリース等を用いずに、反応性金属箔３０を熱源として溶融された後に凝固したはんだ３１，３２によりヒートシンク２０と半導体装置１０とを接合する。これにより、ヒートシンク２０と半導体装置１０との間の熱抵抗を小さくできる。このため、効率的に、放熱性に優れたヒートシンク一体型のパワー半導体モジュール１を提供することができる。さらに、反応性金属箔３０を用いることにより、複数の半導体装置１０を電気特性試験によって選別した後、良品のみをヒートシンク２０と接合することも可能となる。このため、良品率が高く、かつ放熱性に優れたヒートシンク一体型のパワー半導体モジュール１を提供することができる。 As described above, according to the first embodiment, the reactive metal foil 30 that itself becomes a heat source (igniter) is used for joining the heat sink 20 and the semiconductor device 10. Thereby, the heat sink 20 and the semiconductor device 10 can be instantaneously bonded at room temperature without heating from the outside. Further, without using grease or the like, the heat sink 20 and the semiconductor device 10 are joined by the solders 31 and 32 that are solidified after being melted using the reactive metal foil 30 as a heat source. Thereby, the thermal resistance between the heat sink 20 and the semiconductor device 10 can be reduced. For this reason, the heat semiconductor integrated power semiconductor module 1 excellent in heat dissipation can be provided efficiently. Further, by using the reactive metal foil 30, it is possible to join only the non-defective product to the heat sink 20 after selecting the plurality of semiconductor devices 10 by the electrical characteristic test. Therefore, it is possible to provide the heat semiconductor integrated power semiconductor module 1 with a high non-defective rate and excellent heat dissipation.
　また、半導体装置１０を組み立てる工程の後、この工程とは別に、それ自体が熱源となる反応性金属箔３０を用いてヒートシンク２０と半導体装置１０を接合する工程をおこなう。このため、接合のためにヒートシンク２０全体を外部から加熱する必要がなく、製造工程の簡素化、効率化を実現することができる。また、グリース等を用いないので、放熱性に優れたヒートシンク一体型のパワー半導体モジュール１の製造方法を提供することができる。さらに、半導体装置１０の電気特性を試験する工程をおこなった後に、反応性金属箔３０を用いて接合する工程を実施することにより、良品率が高いヒートシンク一体型のパワー半導体モジュールの製造方法を提供することができる。 In addition, after the process of assembling the semiconductor device 10, a process of joining the heat sink 20 and the semiconductor device 10 using the reactive metal foil 30 that itself becomes a heat source is performed separately from this process. For this reason, it is not necessary to heat the entire heat sink 20 from the outside for bonding, and the manufacturing process can be simplified and made more efficient. Further, since no grease or the like is used, a method for manufacturing the heat semiconductor integrated power semiconductor module 1 with excellent heat dissipation can be provided. Furthermore, after performing the process of testing the electrical characteristics of the semiconductor device 10, a process for bonding using the reactive metal foil 30 is performed, thereby providing a method for manufacturing a power semiconductor integrated power semiconductor module with a high yield rate. can do.
（実施の形態２）
　図３は、実施の形態２にかかる半導体モジュールの要部を模式的に示す断面図である。実施の形態２にかかるパワー半導体モジュール２は、実施の形態１の変形例である。はんだ３１，３２に代えて、ヒートシンク２０と金属ベース板５０の対向する面にそれぞれ施されためっき３５，３６を接合材として用いてもよい。 (Embodiment 2)
FIG. 3 is a cross-sectional view schematically showing a main part of the semiconductor module according to the second embodiment. A power semiconductor module 2 according to the second embodiment is a modification of the first embodiment. Instead of the solders 31 and 32, platings 35 and 36 respectively applied to the opposing surfaces of the heat sink 20 and the metal base plate 50 may be used as a bonding material.
　実施の形態２では、金属ベース板５０の、ヒートシンク２０を接合する側の主面（他の主面）に、めっき３６が施されている。ヒートシンク２０の、金属ベース板５０を接合する側の主面（一の主面）には、めっき３５が施されている。金属ベース板５０のめっき３６が施された面と、ヒートシンク２０のめっき３５が施された面との間には、めっき３５，３６の熱源となる反応性金属箔３０が挟まれている。つまり、金属ベース板５０とヒートシンク２０との間に、はんだは挟まれていない。反応性金属箔３０を熱源として、めっき３５，３６が溶融された後に凝固した接合層により、金属ベース板５０とヒートシンク２０は接合されている。 In the second embodiment, plating 36 is applied to the main surface (other main surface) of the metal base plate 50 on the side where the heat sink 20 is joined. The main surface (one main surface) of the heat sink 20 on the side to which the metal base plate 50 is joined is plated 35. A reactive metal foil 30 serving as a heat source for the platings 35 and 36 is sandwiched between the surface of the metal base plate 50 that is plated 36 and the surface of the heat sink 20 that is plated 35. That is, no solder is sandwiched between the metal base plate 50 and the heat sink 20. Using the reactive metal foil 30 as a heat source, the metal base plate 50 and the heat sink 20 are bonded together by a bonding layer that solidifies after the platings 35 and 36 are melted.
　めっき３５，３６は、スズを主成分とするめっきであるのが好ましい。その理由は、反応性金属箔３０の発火・発熱によりスズめっき自身が溶融して、ヒートシンク２０と金属ベース板５０とを接合する接合材となるからである。また、めっき３５，３６は、ニッケルめっき等であってもよい。この場合、反応性金属箔３０の他に接合材としてはんだが必要である。めっき３５，３６の厚さは、スズめっきの場合、ヒートシンク２０と金属ベース板５０を接合できる程度であれば良く、好ましくは０．００５ｍｍ以上０．０５ｍｍ以下であるのがよい。それ以外の構成および製造方法は、実施の形態１と同様である。 The platings 35 and 36 are preferably platings mainly composed of tin. The reason is that the tin plating itself is melted by the ignition and heat generation of the reactive metal foil 30 and becomes a bonding material for bonding the heat sink 20 and the metal base plate 50. The platings 35 and 36 may be nickel plating or the like. In this case, solder is required as a bonding material in addition to the reactive metal foil 30. In the case of tin plating, the thickness of the platings 35 and 36 may be such that the heat sink 20 and the metal base plate 50 can be joined, and preferably 0.005 mm or more and 0.05 mm or less. Other configurations and manufacturing methods are the same as those in the first embodiment.
　また、めっき３５，３６は、はんだ３１，３２に比べて薄く、めっき３５，３６を用いて半導体装置１１とヒートシンク２０を接合すると、金属ベース板５０が反る場合がある。このため、めっき３５，３６を用いて半導体装置１１とヒートシンク２０を接合する場合、金属ベース板５０とヒートシンク２０間の隙間はできるかぎり小さいのが望ましい。したがって、半導体装置１１の組み立てが終了した後（図２のステップＳ３参照）、半導体装置１１とヒートシンク２０を接合する前に（図２のステップＳ５参照）、金属ベース板５０に平坦加工を施すことが好ましい。さらに、金属ベース板５０とヒートシンク２０間の隙間を小さくするため、金属ベース板５０の平面寸法を７０ｍｍ×７０ｍｍ以下とすることが特に好ましい。 Also, the platings 35 and 36 are thinner than the solders 31 and 32, and the metal base plate 50 may warp when the semiconductor device 11 and the heat sink 20 are joined using the platings 35 and 36. For this reason, when joining the semiconductor device 11 and the heat sink 20 using the plating 35 and 36, it is desirable that the gap between the metal base plate 50 and the heat sink 20 is as small as possible. Therefore, after the assembly of the semiconductor device 11 is completed (see step S3 in FIG. 2), the metal base plate 50 is flattened before the semiconductor device 11 and the heat sink 20 are joined (see step S5 in FIG. 2). Is preferred. Furthermore, in order to reduce the gap between the metal base plate 50 and the heat sink 20, it is particularly preferable that the planar size of the metal base plate 50 is 70 mm × 70 mm or less.
　以上、説明したように、実施の形態２によれば、実施の形態１と同様の効果を得ることができる。 As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained.
（実施の形態３）
　図４は、実施の形態３にかかる半導体モジュールの要部を模式的に示す断面図である。実施の形態３にかかるパワー半導体モジュール３は実施の形態１の変形例である。金属ベース板５０を用いずに、絶縁基板６０とヒートシンク２０とを直接接合してもよい。 (Embodiment 3)
FIG. 4 is a cross-sectional view schematically showing a main part of the semiconductor module according to the third embodiment. The power semiconductor module 3 according to the third embodiment is a modification of the first embodiment. The insulating substrate 60 and the heat sink 20 may be directly joined without using the metal base plate 50.
　実施の形態３では、半導体装置１２は、金属ベース板５０を備えていない。そして、絶縁基板６０の、半導体チップ４０が接合されている主面（一の主面）に対して反対側の主面（他方の主面）には、反応性金属箔３０を熱源とするはんだ３１，３２を介してヒートシンク２０が接合されている。それ以外の構成は、実施の形態１と同様である。 In the third embodiment, the semiconductor device 12 does not include the metal base plate 50. And the solder which uses the reactive metal foil 30 as a heat source is provided on the main surface (the other main surface) opposite to the main surface (one main surface) to which the semiconductor chip 40 is bonded. The heat sink 20 is joined via 31 and 32. Other configurations are the same as those in the first embodiment.
　次に、実施の形態３のパワー半導体モジュール３の製造方法について説明する。実施の形態３では、実施の形態１のステップＳ１において、金属ベース板５０と絶縁基板６０の接合を省略している（ステップＳ１’）。つまり、ステップＳ１’では、半導体チップ４０と絶縁基板６０の接合のみをおこなう。次に、ステップＳ２において、接着剤を用いて樹脂ケース７０を絶縁基板６０の周縁に嵌合して固定する（ステップＳ２’）。 Next, a method for manufacturing the power semiconductor module 3 according to the third embodiment will be described. In the third embodiment, the joining of the metal base plate 50 and the insulating substrate 60 is omitted in step S1 of the first embodiment (step S1 '). That is, in step S <b> 1 ′, only the semiconductor chip 40 and the insulating substrate 60 are bonded. Next, in step S2, the resin case 70 is fitted and fixed to the periphery of the insulating substrate 60 using an adhesive (step S2 ').
　次に、ステップＳ５において、ヒートシンク２０の一方の主面に、はんだ３１、反応性金属箔３０およびはんだ３２をこの順に重ね、はんだ３２の上に、半導体装置１２の絶縁基板６０の他の主面がヒートシンク２０側になるように半導体装置１２を重ねる。そして、実施の形態１と同様に、これら積み重ねた部材を例えば半導体装置１２側およびヒートシンク２０側から加圧する（ステップＳ５’）。それ以外の製造方法は、実施の形態１と同様である。 Next, in step S <b> 5, the solder 31, the reactive metal foil 30 and the solder 32 are stacked in this order on one main surface of the heat sink 20, and the other main surface of the insulating substrate 60 of the semiconductor device 12 is placed on the solder 32. The semiconductor device 12 is overlaid so that is on the heat sink 20 side. Then, similarly to the first embodiment, these stacked members are pressurized from, for example, the semiconductor device 12 side and the heat sink 20 side (step S5 '). The other manufacturing methods are the same as those in the first embodiment.
　以上、説明したように、実施の形態３によれば、実施の形態１と同様の効果を得ることができる。また、金属ベース板５０およびはんだ３３を省略した構成により、半導体チップ４０とヒートシンク２０の間の熱抵抗を低減できる。また、金属ベース板５０を用いないことにより、金属ベース板５０および絶縁基板６０を接合した際に半導体装置に生じる反りを回避することができる。また、反応性金属箔３０を用いて絶縁基板６０とヒートシンク２０を接合することにより、絶縁基板６０とヒートシンク２０との間にグリースを挟みネジ止めにより固定する場合に比べて、絶縁基板６０のクラックや、割れを防止することができる。 As described above, according to the third embodiment, the same effect as in the first embodiment can be obtained. In addition, with the configuration in which the metal base plate 50 and the solder 33 are omitted, the thermal resistance between the semiconductor chip 40 and the heat sink 20 can be reduced. Further, by not using the metal base plate 50, it is possible to avoid warping that occurs in the semiconductor device when the metal base plate 50 and the insulating substrate 60 are joined. In addition, by bonding the insulating substrate 60 and the heat sink 20 using the reactive metal foil 30, the insulating substrate 60 is cracked as compared with a case where grease is sandwiched between the insulating substrate 60 and the heat sink 20 and fixed by screwing. In addition, cracking can be prevented.
　また、実施の形態３において、はんだ３１，３２に代えて、めっきを接合材として用いてもよい。この場合、実施の形態２と同様に、絶縁基板６０の金属板６３の表面、およびヒートシンク２０の一の主面にスズめっきを施し、スズめっきを接合材として半導体装置１２とヒートシンク２０を接合する。実施の形態３では、上述したように、金属ベース板５０を用いないので、絶縁基板６０の底面が平坦である。このため、絶縁基板６０の平坦加工を施すことなく、半導体装置１２とヒートシンク２０を接合することができる。 Further, in the third embodiment, instead of the solders 31 and 32, plating may be used as a bonding material. In this case, as in the second embodiment, tin plating is applied to the surface of the metal plate 63 of the insulating substrate 60 and one main surface of the heat sink 20, and the semiconductor device 12 and the heat sink 20 are bonded using tin plating as a bonding material. . In the third embodiment, as described above, since the metal base plate 50 is not used, the bottom surface of the insulating substrate 60 is flat. For this reason, the semiconductor device 12 and the heat sink 20 can be joined without performing the flat processing of the insulating substrate 60.
（実施の形態４）
　図５は、実施の形態４にかかる半導体モジュールの要部を模式的に示す断面図である。実施の形態４にかかるパワー半導体モジュール４は実施の形態３の変形例である。絶縁基板６０と半導体チップ４０とを、反応性金属箔３０を熱源として溶融された後に凝固したはんだによって接合してもよい。 (Embodiment 4)
FIG. 5 is a cross-sectional view schematically showing a main part of the semiconductor module according to the fourth embodiment. The power semiconductor module 4 according to the fourth embodiment is a modification of the third embodiment. The insulating substrate 60 and the semiconductor chip 40 may be joined by solder solidified after being melted using the reactive metal foil 30 as a heat source.
　実施の形態４では、絶縁基板６０と半導体チップ４０は、はんだ１３１，１３２の熱源である反応性金属箔１３０、およびはんだ１３１，１３２により接合されている。絶縁基板６０と半導体チップ４０とを接合する反応性金属箔１３０およびはんだ１３１，１３２の構成および条件は、絶縁基板６０とヒートシンク２０とを接合する反応性金属箔３０およびはんだ３１，３２と同様である。 In the fourth embodiment, the insulating substrate 60 and the semiconductor chip 40 are joined by the reactive metal foil 130 that is a heat source of the solder 131 and 132 and the solder 131 and 132. The configuration and conditions of the reactive metal foil 130 and the solders 131 and 132 that join the insulating substrate 60 and the semiconductor chip 40 are the same as the reactive metal foil 30 and the solders 31 and 32 that join the insulating substrate 60 and the heat sink 20. is there.
　つまり、パワー半導体モジュール４は、ヒートシンク２０側からヒートシンク２０、はんだ３１、反応性金属箔３０、はんだ３２、絶縁基板６０、はんだ１３１、反応性金属箔１３０、はんだ１３２および半導体チップ４０の順に重ねられた状態で接合されている。それ以外の構成は、実施の形態３と同様である。 That is, the power semiconductor module 4 is stacked from the heat sink 20 side in the order of the heat sink 20, solder 31, reactive metal foil 30, solder 32, insulating substrate 60, solder 131, reactive metal foil 130, solder 132, and semiconductor chip 40. Are joined together. Other configurations are the same as those in the third embodiment.
　次に、実施の形態４のパワー半導体モジュール４の製造方法について説明する。実施の形態４では、リフロー工程（図２のステップＳ１参照）に代えて、絶縁基板６０の一方の主面にはんだ１３１、反応性金属箔１３０、はんだ１３２および半導体チップ４０を重ねる。そして、これら積み重ねた部材を例えば半導体チップ４０側から加圧する。この状態で反応性金属箔１３０に刺激を与えて自己発火させ、はんだ１３１，１３２を溶融させた後に凝固させることで、絶縁基板６０と半導体チップ４０とを接合する（ステップＳ１”）。これにより、絶縁基板６０と半導体チップ４０とが、はんだ１３１，１３２によって接合される。それ以外の条件および製造方法は、実施の形態３と同様である。 Next, a method for manufacturing the power semiconductor module 4 of the fourth embodiment will be described. In the fourth embodiment, instead of the reflow process (see step S1 in FIG. 2), the solder 131, the reactive metal foil 130, the solder 132, and the semiconductor chip 40 are stacked on one main surface of the insulating substrate 60. Then, these stacked members are pressurized from, for example, the semiconductor chip 40 side. In this state, the reactive metal foil 130 is stimulated to self-ignite, and after the solders 131 and 132 are melted and solidified, the insulating substrate 60 and the semiconductor chip 40 are joined (step S1 ″). The insulating substrate 60 and the semiconductor chip 40 are joined by the solders 131 and 132. Other conditions and the manufacturing method are the same as those in the third embodiment.
　以上、説明したように、実施の形態４によれば、実施の形態３と同様の効果を得ることができる。また、絶縁基板６０と半導体チップ４０とを反応性金属箔１３０を用いて接合することにより、パワー半導体モジュール４の製造方法においてリフロー工程を省略することができる。 As described above, according to the fourth embodiment, the same effect as in the third embodiment can be obtained. Further, the reflow process can be omitted in the method for manufacturing the power semiconductor module 4 by bonding the insulating substrate 60 and the semiconductor chip 40 using the reactive metal foil 130.
　以下、実施例により本発明をさらに説明するが、本発明はこれらの実施例に限定されるものではない。 Hereinafter, the present invention will be further described with reference to examples, but the present invention is not limited to these examples.
（実施例１）
　本発明における、ヒートシンク２０と金属ベース板５０を接合するはんだ３１，３２の厚さの好適な範囲を検証した。図６は、はんだの厚さと接合性およびはみ出しの関係を示す説明図である。まず、実施の形態１に従い、パワー半導体モジュール１（図１参照）を作製した。詳細には、金属ベース板５０の表面にニッケルめっきが施された半導体装置１０と、金属ベース板５０との接合面にニッケルめっきが施されたヒートシンク２０を用意した。そして、金属ベース板５０とヒートシンク２０の間に、反応性金属箔３０としてニッケルとアルミニウムを交互に積層した積層膜と、はんだ３１，３２としてＳｎ－Ｓｂはんだ板とを各々挿入した。反応性金属箔３０の厚さを０．０５ｍｍとした。次に、これら積み重ねた部材を、金属ベース板５０側およびヒートシンク２０側から加圧した。この状態で反応性金属箔３０に電流を流して発火させ、はんだ３１，３２を溶解した後に凝固させ、金属ベース板５０とヒートシンク２０とを接合した。その後、はんだのボイド状態（接合性）とはみ出しの有無について調べた。はんだ３１，３２として用いるＳｎ－Ｓｂはんだ板の厚さを種々変更し、上記検証を繰り返し行った。Ｓｎ－Ｓｂはんだ板の厚さ（図６のはんだの厚さ）は、０．１ｍｍから０．７ｍｍまで変化させた。その結果を図６に示す。 Example 1
The preferred range of the thicknesses of the solders 31 and 32 for joining the heat sink 20 and the metal base plate 50 in the present invention was verified. FIG. 6 is an explanatory diagram showing the relationship between solder thickness, bondability, and protrusion. First, according to Embodiment 1, the power semiconductor module 1 (refer FIG. 1) was produced. Specifically, the semiconductor device 10 in which nickel plating is applied to the surface of the metal base plate 50 and the heat sink 20 in which nickel plating is applied to the joint surface between the metal base plate 50 were prepared. A laminated film in which nickel and aluminum were alternately laminated as the reactive metal foil 30 and Sn—Sb solder plates as the solders 31 and 32 were inserted between the metal base plate 50 and the heat sink 20, respectively. The thickness of the reactive metal foil 30 was 0.05 mm. Next, these stacked members were pressed from the metal base plate 50 side and the heat sink 20 side. In this state, an electric current was passed through the reactive metal foil 30 to ignite, and the solders 31 and 32 were melted and then solidified to join the metal base plate 50 and the heat sink 20. Thereafter, the void state (joinability) of the solder and the presence or absence of protrusion were examined. The thickness of the Sn—Sb solder plate used as the solders 31 and 32 was variously changed, and the above verification was repeated. The thickness of the Sn—Sb solder plate (the thickness of the solder in FIG. 6) was changed from 0.1 mm to 0.7 mm. The result is shown in FIG.
　図６に示す結果より、Ｓｎ－Ｓｂはんだ板厚が０．２ｍｍ以上０．５ｍｍ以下である場合、加圧によるはんだはみ出しがパワー半導体モジュール１の性能に悪影響を与えない程度に少なく（はんだはみ出し有無：良好）、かつ、金属ベース板５０とヒートシンク２０との接合性はよい（接合性：○）ことがわかった。それに対して、Ｓｎ－Ｓｂはんだ板厚が０．２ｍｍより薄い場合、はんだによって金属ベース板とヒートシンクの隙間を埋めることができず、隙間が残ってしまい（はんだはみ出し有無：不足）、金属ベース板５０とヒートシンク２０との接合性は悪い（接合性：×）ことがわかった。また、Ｓｎ－Ｓｂはんだ板が０．５ｍｍより厚い場合、金属ベース板５０とヒートシンク２０との接合性はよいが（接合性：○）、加圧によるはんだのはみ出しが多くなってしまうことがわかった（はんだはみ出し有無：はみ出し発生）。したがって、ニッケルめっき処理した金属ベース板５０とヒートシンク２０の接合において、Ｓｎ－Ｓｂはんだ板の厚さは０．２ｍｍ以上０．５ｍｍ以下が望ましいことがわかった。なお、金属ベース板５０とヒートシンク２０との接合の前後で、Ｓｎ－Ｓｂはんだ板の厚さとはんだ３１，３２の厚さにほとんど変化はなかった。 From the results shown in FIG. 6, when the Sn—Sb solder plate thickness is 0.2 mm or more and 0.5 mm or less, the solder protrusion due to pressurization is so small that it does not adversely affect the performance of the power semiconductor module 1 (the presence or absence of solder protrusion) : Good), and it was found that the metal base plate 50 and the heat sink 20 have good bondability (bondability: ◯). On the other hand, when the Sn—Sb solder plate thickness is less than 0.2 mm, the gap between the metal base plate and the heat sink cannot be filled with the solder, and the gap remains (solder protruding or not: insufficient). 50 and the heat sink 20 were found to have poor bondability (bondability: x). In addition, when the Sn—Sb solder plate is thicker than 0.5 mm, the joining property between the metal base plate 50 and the heat sink 20 is good (joining property: ○), but it is found that the solder protrudes by pressurization. (Existence of solder protrusion: occurrence of protrusion). Therefore, it was found that the thickness of the Sn—Sb solder plate is preferably 0.2 mm or more and 0.5 mm or less in the joining of the nickel-plated metal base plate 50 and the heat sink 20. Note that there was almost no change in the thickness of the Sn—Sb solder plate and the thickness of the solders 31 and 32 before and after the joining of the metal base plate 50 and the heat sink 20.
　また、金属ベース板５０およびヒートシンク２０の表面に施されるめっきとして、ニッケルめっきの代わりに、金めっきまたは金蒸着を用いても、上述したような同様の結果が得られると推測される。 Also, it is assumed that the same result as described above can be obtained even if gold plating or gold vapor deposition is used instead of nickel plating as the plating applied to the surfaces of the metal base plate 50 and the heat sink 20.
（実施例２）
　図７は、絶縁基板および金属ベース板が反った状態を模式的に示す断面図である。金属ベース板５０と、セラミックスからなる絶縁基板６０とは熱膨張率が異なる。このため、金属ベース板５０と絶縁基板６０とをはんだにより接合すると、熱膨張率の差により金属ベース板５０は絶縁基板６０側に凸状に反ってしまう。したがって、この金属ベース板５０をヒートシンク２０の上に置いた場合、金属ベース板５０とヒートシンク２０との間に隙間（以下、金属ベース板隙間量ｔとする）が生じる。このため、金属ベース板５０とヒートシンク２０との接合に際してはこの隙間を埋めるのに十分な厚さのはんだが必要となる。 (Example 2)
FIG. 7 is a cross-sectional view schematically showing a state where the insulating substrate and the metal base plate are warped. The thermal expansion coefficient differs between the metal base plate 50 and the insulating substrate 60 made of ceramics. For this reason, when the metal base plate 50 and the insulating substrate 60 are joined by solder, the metal base plate 50 warps in a convex shape toward the insulating substrate 60 due to a difference in thermal expansion coefficient. Therefore, when the metal base plate 50 is placed on the heat sink 20, a gap (hereinafter referred to as a metal base plate gap amount t) is generated between the metal base plate 50 and the heat sink 20. For this reason, when joining the metal base plate 50 and the heat sink 20, solder having a thickness sufficient to fill this gap is required.
　図８は、絶縁基板の厚さと金属ベース板－ヒートシンク間の隙間量との関係を示す特性図である。金属ベース板５０の反り（金属ベース板隙間量ｔ）は、ヒートシンク２０が接合される面に対して反対側の面（図７では紙面の上側）にはんだ付けされるセラミックスからなる絶縁板６１の厚さにも影響される。ここで、パワー半導体モジュール１の性能を考慮すると、絶縁板６１の最適な厚さは、上述したように０．２ｍｍ以上０．６ｍｍ以下であるのが好ましいので、この範囲で絶縁板６１の厚さと金属ベース板隙間量ｔとの関係を調べた。図８に示す結果から明らかなように、絶縁板６１の厚さにほぼ比例して金属ベース板５０の反り（金属ベース板隙間量ｔ）は大きくなることがわかった。 FIG. 8 is a characteristic diagram showing the relationship between the thickness of the insulating substrate and the gap amount between the metal base plate and the heat sink. The warp (metal base plate gap amount t) of the metal base plate 50 is that of the insulating plate 61 made of ceramics soldered to the surface opposite to the surface to which the heat sink 20 is bonded (upper side of the paper surface in FIG. 7). It is also affected by the thickness. Here, considering the performance of the power semiconductor module 1, the optimum thickness of the insulating plate 61 is preferably 0.2 mm or more and 0.6 mm or less as described above. And the relationship between the metal base plate gap amount t. As is apparent from the results shown in FIG. 8, it was found that the warp (metal base plate gap amount t) of the metal base plate 50 increases in proportion to the thickness of the insulating plate 61.
　図９は、金属ベース板－ヒートシンク間の隙間量とはんだの厚さとの関係を示す特性図である。次に、金属ベース板隙間量ｔと、金属ベース板５０とヒートシンク２０とを良好に接合するために必要なはんだ３１，３２の厚さとの関係を調べた。実施例１と同様に、金属ベース板５０とヒートシンク２０とを接合する反応性金属箔３０およびはんだ３１，３２を用い、これら積み重ねた部材を、金属ベース板５０側およびヒートシンク２０側から加圧した。 FIG. 9 is a characteristic diagram showing the relationship between the amount of the gap between the metal base plate and the heat sink and the thickness of the solder. Next, the relationship between the metal base plate gap amount t and the thicknesses of the solders 31 and 32 necessary to satisfactorily join the metal base plate 50 and the heat sink 20 was examined. In the same manner as in Example 1, a reactive metal foil 30 and solders 31 and 32 for joining the metal base plate 50 and the heat sink 20 were used, and these stacked members were pressed from the metal base plate 50 side and the heat sink 20 side. .
　図９に示す結果より、絶縁板６１の厚さが０．２ｍｍ以上０．６ｍｍ以下である場合、金属ベース板５０とヒートシンク２０を接合するために必要なはんだ３１，３２の厚さ（Ｓｎ－Ｓｂはんだ板の厚さ）は、約０．２ｍｍ以上０．５ｍｍ以下であることがわかった。これは実施例１の結果と一致している。つまり、はんだ３１，３２の厚さを０．２ｍｍ以上０．５ｍｍ以下とすることで、金属ベース板隙間量ｔを埋めて、金属ベース板５０とヒートシンク２０との接合性をよくすることができ、かつ、加圧によるはんだのはみ出しを少なくすることができることがわかる。 From the results shown in FIG. 9, when the thickness of the insulating plate 61 is not less than 0.2 mm and not more than 0.6 mm, the thicknesses of the solders 31 and 32 required to join the metal base plate 50 and the heat sink 20 (Sn− The thickness of the Sb solder plate was found to be about 0.2 mm or more and 0.5 mm or less. This is consistent with the result of Example 1. In other words, by setting the thickness of the solders 31 and 32 to 0.2 mm or more and 0.5 mm or less, the metal base plate gap amount t can be filled and the bondability between the metal base plate 50 and the heat sink 20 can be improved. And it turns out that the protrusion of the solder by pressurization can be decreased.
（実施例３）
　次に、実施の形態２において説明したパワー半導体モジュール２（図３参照）における熱抵抗を検証した。まず、実施の形態２に従い、ヒートシンク一体型のパワー半導体モジュール２を作製した。詳細には、ヒートシンク２０と金属ベース板５０のそれぞれの接合面にスズを主成分とするめっき３５，３６（以下、スズめっきとする）が施されている。スズめっきの厚さは０．０５ｍｍ以下とした。また、反応性金属箔３０の厚さは０．０６ｍｍとした。それ以外の構成は、実施例１と同様である。 (Example 3)
Next, the thermal resistance in the power semiconductor module 2 (see FIG. 3) described in the second embodiment was verified. First, according to the second embodiment, a heat semiconductor integrated power semiconductor module 2 was produced. Specifically, plating 35 and 36 (hereinafter referred to as tin plating) containing tin as a main component is applied to each joint surface of the heat sink 20 and the metal base plate 50. The thickness of the tin plating was 0.05 mm or less. Moreover, the thickness of the reactive metal foil 30 was 0.06 mm. Other configurations are the same as those in the first embodiment.
　実施例１のようなニッケルめっき同士の接合では、反応性金属箔３０の他に接合材としてはんだ３１，３２が必要であるが、スズめっき３５，３６同士の接合では、反応性金属箔３０のみでヒートシンク２０と金属ベース板５０とを接合することができることがわかった。その理由は、反応性金属箔３０の発火、発熱によりスズめっき自身が溶融し、接合材として働くからであると推測される。 In the joining between the nickel platings as in the first embodiment, the solders 31 and 32 are necessary as the joining material in addition to the reactive metal foil 30, but in the joining between the tin platings 35 and 36, only the reactive metal foil 30 is used. Thus, it was found that the heat sink 20 and the metal base plate 50 can be joined. The reason is presumed that the tin plating itself is melted by the ignition and heat generation of the reactive metal foil 30 and works as a bonding material.
　図１０は、ヒートシンク熱伝導率と熱抵抗との関係を示す特性図である。また、実施の形態３に従い、金属ベース板５０を用いずに、ヒートシンク一体型のパワー半導体モジュールを作製した（以下、実施例とする）。ここでは、はんだを用いずに、めっき３５，３６によって、ヒートシンク２０と絶縁基板６０を直接接合している。比較として、金属ベース板とヒートシンクとの間に放熱グリースを介してネジ締め付けした従来構造のパワー半導体モジュールを用意した（図１１参照。以下、従来構造とする）。 FIG. 10 is a characteristic diagram showing the relationship between heat sink thermal conductivity and thermal resistance. Further, according to the third embodiment, a power semiconductor module integrated with a heat sink was manufactured without using the metal base plate 50 (hereinafter referred to as an example). Here, the heat sink 20 and the insulating substrate 60 are directly joined by plating 35 and 36 without using solder. As a comparison, a power semiconductor module having a conventional structure in which a screw is tightened between a metal base plate and a heat sink via heat-dissipating grease was prepared (see FIG. 11, hereinafter referred to as a conventional structure).
　そして、実施例および従来構造において、ヒートシンクの熱伝導率を種々変更し、それぞれ放熱性を評価した。ヒートシンクの材料となるアルミニウム合金の種類を変えることで、ヒートシンクの熱伝導率を４つの条件に変化させている。この４つの条件のヒートシンクの熱伝導率における、実施例および従来構造の放熱性を評価した結果を図１０に示す。図１０の横軸は、ヒートシンクの熱伝導率［Ｗ／（ｍ・Ｋ）］であり、縦軸は、半導体チップとヒートシンク間（ジャンクション－冷媒問）の熱抵抗Ｒｔｈ（ｊ－ｗ）［Ｋ／Ｗ］である。 And in the examples and the conventional structure, the heat conductivity of the heat sink was variously changed and the heat dissipation was evaluated. By changing the type of aluminum alloy used as the material of the heat sink, the heat conductivity of the heat sink is changed to four conditions. FIG. 10 shows the results of evaluating the heat dissipation of the example and the conventional structure in the heat conductivity of the heat sink under these four conditions. The horizontal axis of FIG. 10 is the heat conductivity [W / (m · K)] of the heat sink, and the vertical axis is the thermal resistance Rth (jw) [K between the semiconductor chip and the heat sink (junction-refrigerant question). / W].
　図１０に示す結果より、ヒートシンクの熱伝導率を１３８Ｗ／（ｍ・Ｋ）とした場合、従来構造では、熱抵抗は約０．４３５Ｋ／Ｗであった（同図中「基準」を参照）。それに対して、実施例では、約０．４２２Ｋ／Ｗであった。これにより、実施例では熱抵抗を約３％低減することができることがわかった。さらに、ヒートシンクの熱伝導率を２０９Ｗ／（ｍ・Ｋ）とした場合、実施例では、熱抵抗は約０．３５５Ｋ／Ｗであった。これにより、実施例では、従来構造（基準）に対して熱抵抗を約２０％低減できることがわかった。したがって、実施例が従来構造に比べて放熱性に優れることが明らかである。このように絶縁基板とヒートシンクを、金属ベース板および放熱グリースを介さずに金属材料で直接接合することにより、放熱性を大きく向上することができることがわかった。 From the results shown in FIG. 10, when the heat conductivity of the heat sink is 138 W / (m · K), the conventional structure has a thermal resistance of about 0.435 K / W (see “reference” in the figure). . On the other hand, in the Example, it was about 0.422 K / W. Thereby, it turned out that a thermal resistance can be reduced about 3% in an Example. Furthermore, when the heat conductivity of the heat sink was 209 W / (m · K), in the example, the thermal resistance was about 0.355 K / W. Thereby, in the Example, it turned out that thermal resistance can be reduced about 20% with respect to the conventional structure (reference | standard). Therefore, it is clear that the example is superior in heat dissipation compared with the conventional structure. Thus, it was found that the heat dissipation can be greatly improved by directly bonding the insulating substrate and the heat sink with a metal material without using the metal base plate and the heat dissipation grease.
　図１０では、ヒートシンクの熱伝導率が１３８Ｗ／（ｍ・Ｋ）より小さくなると従来構造の方が実施例に比べて熱抵抗が小さくなっている。この理由は、実施例では、金属ベース板がなく、熱抵抗におけるヒートシンクの熱伝導の寄与が大きいためと推測される。したがって、ヒートシンクの熱伝導率は１３８Ｗ／（ｍ・Ｋ）以上であることが好ましい。このような結果は、はんだと反応性金属を用いて接合する場合（図４，５参照）においても同様に得ることができる。 In FIG. 10, when the heat conductivity of the heat sink is smaller than 138 W / (m · K), the thermal resistance of the conventional structure is smaller than that of the embodiment. The reason for this is presumed that in the examples, there is no metal base plate, and the heat conduction contributes greatly to the heat resistance. Accordingly, the heat conductivity of the heat sink is preferably 138 W / (m · K) or more. Such a result can be obtained in the same manner when joining using solder and a reactive metal (see FIGS. 4 and 5).
　以上において本発明では、絶縁基板上の回路パターンにボンディングワイヤで接続された状態で封止された半導体チップを備えるパワー半導体モジュールを例に説明しているが、上述した実施の形態に限らず、さまざまな構成の回路に適用することが可能である。また、パワー半導体モジュールよりも低い電流性能および電圧性能を有する半導体モジュールに適用することが可能である。 In the above, in the present invention, a power semiconductor module including a semiconductor chip sealed in a state of being connected to a circuit pattern on an insulating substrate with a bonding wire has been described as an example, but not limited to the above-described embodiment, The present invention can be applied to circuits having various configurations. Further, the present invention can be applied to a semiconductor module having lower current performance and voltage performance than a power semiconductor module.
　以上のように、本発明にかかる半導体装置および半導体装置の製造方法は、電気自動車、電鉄、工作機械などにおいて大電流を制御するためのパワー半導体モジュールに有用である。 As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor module for controlling a large current in an electric vehicle, an electric railway, a machine tool, and the like.
　　１　　パワー半導体モジュール
　１０　　半導体チップを含む部材（半導体装置）
　２０　　ヒートシンク
　３０　　反応性金属箔
　３１，３２，３３，３４　　はんだ
　４０　　半導体チップ
　５０　　金属ベース板
　６０　　絶縁基板
　６１　　絶縁板
　６２，６３　　金属板
　７０　　樹脂ケース
　７１　　シリコーンゲル
　７２　　エポキシ樹脂
　７３　　蓋
　８１　　ボンディングワイヤ
　８２　　外部接続端子 DESCRIPTION OF SYMBOLS 1 Power semiconductor module 10 Member (semiconductor device) containing a semiconductor chip
20 heat sink 30 reactive metal foil 31, 32, 33, 34 solder 40 semiconductor chip 50 metal base plate 60 insulating substrate 61 insulating plate 62, 63 metal plate 70 resin case 71 silicone gel 72 epoxy resin 73 lid 81 bonding wire 82 external connection Terminal

Claims (24)

  1. 　ヒートシンクと、
    　反応性金属箔を熱源として溶融、凝固したはんだ又はめっきにより前記ヒートシンクの一の主面に接合された半導体チップを含む部材と、
    　を備えることを特徴とする半導体モジュール。     A heat sink,
    A member including a semiconductor chip bonded to one of the main surfaces of the heat sink by melting or solidifying solder or plating using a reactive metal foil as a heat source;
    A semiconductor module comprising:
  2. 　前記部材は、金属ベース板と、前記金属ベース板の一の主面に接合された絶縁基板と、前記絶縁基板の一の主面に接合された前記半導体チップと、を備え、
    　前記金属ベース板の他の主面に前記ヒートシンクが接合されていることを特徴とする請求項１に記載の半導体モジュール。     The member includes a metal base plate, an insulating substrate bonded to one main surface of the metal base plate, and the semiconductor chip bonded to one main surface of the insulating substrate,
    The semiconductor module according to claim 1, wherein the heat sink is bonded to another main surface of the metal base plate.
  3. 　前記部材は、絶縁基板と、前記絶縁基板の一の主面に接合された前記半導体チップと、を備え、
    　前記絶縁基板の他の主面に前記ヒートシンクが接合されていることを特徴とする請求項１に記載の半導体モジュール。     The member includes an insulating substrate and the semiconductor chip bonded to one main surface of the insulating substrate,
    The semiconductor module according to claim 1, wherein the heat sink is bonded to another main surface of the insulating substrate.
  4. 　前記反応性金属箔は、ニッケルとアルミニウムが交互に積層されてなる積層膜であることを特徴とする請求項１に記載の半導体モジュール。 The semiconductor module according to claim 1, wherein the reactive metal foil is a laminated film in which nickel and aluminum are alternately laminated.
  5. 　前記反応性金属箔は、物理蒸着法によって積層された積層膜であることを特徴とする請求項４に記載の半導体モジュール。 The semiconductor module according to claim 4, wherein the reactive metal foil is a laminated film laminated by a physical vapor deposition method.
  6. 　前記反応性金属箔の厚さは、０．０５ｍｍ以上０．１ｍｍ以下であることを特徴とする請求項４に記載の半導体モジュール。 The semiconductor module according to claim 4, wherein the thickness of the reactive metal foil is 0.05 mm or more and 0.1 mm or less.
  7. 　前記絶縁基板は、絶縁板と、前記絶縁板の両面にそれぞれ接合された金属板とからなることを特徴とする請求項２に記載の半導体モジュール。 3. The semiconductor module according to claim 2, wherein the insulating substrate includes an insulating plate and a metal plate bonded to both surfaces of the insulating plate.
  8. 　前記絶縁板の厚さは、０．２ｍｍ以上１．０ｍｍ以下であることを特徴とする請求項７に記載の半導体モジュール。 The semiconductor module according to claim 7, wherein the insulating plate has a thickness of 0.2 mm to 1.0 mm.
  9. 　前記絶縁板は、アルミナ、ジルコニアが添加されたアルミナ、窒化珪素または窒化アルミニウムであることを特徴とする請求項７に記載の半導体モジュール。 8. The semiconductor module according to claim 7, wherein the insulating plate is alumina, alumina added with zirconia, silicon nitride, or aluminum nitride.
  10. 　前記絶縁基板は、絶縁板と、前記絶縁板の両面にそれぞれ接合された金属板とからなることを特徴とする請求項３に記載の半導体モジュール。 4. The semiconductor module according to claim 3, wherein the insulating substrate includes an insulating plate and a metal plate bonded to both surfaces of the insulating plate.
  11. 　前記絶縁板の厚さは、０．２ｍｍ以上１．０ｍｍ以下であることを特徴とする請求項１０に記載の半導体モジュール。 The semiconductor module according to claim 10, wherein the insulating plate has a thickness of 0.2 mm to 1.0 mm.
  12. 　前記絶縁板は、アルミナ、ジルコニアが添加されたアルミナ、窒化珪素または窒化アルミニウムであることを特徴とする請求項１０に記載の半導体モジュール。 11. The semiconductor module according to claim 10, wherein the insulating plate is alumina, alumina to which zirconia is added, silicon nitride, or aluminum nitride.
  13. 　前記金属板は、銅、銅合金、アルミニウムまたはアルミニウム合金であることを特徴とする請求項７～１２のいずれか一つに記載の半導体モジュール。 13. The semiconductor module according to claim 7, wherein the metal plate is copper, a copper alloy, aluminum, or an aluminum alloy.
  14. 　前記ヒートシンクは、銅、銅合金、アルミニウム、アルミニウム合金、銅－モリブデンまたはアルミニウム－炭化珪素であることを特徴とする請求項１に記載の半導体モジュール。 2. The semiconductor module according to claim 1, wherein the heat sink is made of copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum, or aluminum-silicon carbide.
  15. 　前記ヒートシンクの表面は、ニッケルめっき、金めっき又はスズめっきが施されることを特徴とする請求項１４に記載の半導体モジュール。 15. The semiconductor module according to claim 14, wherein the surface of the heat sink is subjected to nickel plating, gold plating or tin plating.
  16. 　前記金属ベース板は、銅、銅合金、アルミニウム、アルミニウム合金、銅－モリブデン合金、鉄または鉄合金であることを特徴とする請求項２に記載の半導体モジュール。 3. The semiconductor module according to claim 2, wherein the metal base plate is made of copper, copper alloy, aluminum, aluminum alloy, copper-molybdenum alloy, iron or iron alloy.
  17. 　前記金属ベース板の表面は、ニッケルめっき、金めっき又はスズめっきが施されていることを特徴とする請求項１６に記載の半導体モジュール。 The semiconductor module according to claim 16, wherein the surface of the metal base plate is subjected to nickel plating, gold plating or tin plating.
  18. 　前記半導体チップと絶縁基板、および絶縁基板と金属ベース板は、それぞれはんだにより接合されていることを特徴とする請求項２に記載の半導体モジュール。 3. The semiconductor module according to claim 2, wherein the semiconductor chip and the insulating substrate, and the insulating substrate and the metal base plate are respectively joined by solder.
  19. 　前記半導体チップと絶縁基板は、はんだにより接合されていることを特徴とする請求項３に記載の半導体モジュール。 4. The semiconductor module according to claim 3, wherein the semiconductor chip and the insulating substrate are joined by solder.
  20. 　前記絶縁基板と他の部材とを接合する前記はんだは、反応性金属箔を熱源として溶融、凝固したはんだであることを特徴とする請求項１８または１９に記載の半導体モジュール。 20. The semiconductor module according to claim 18, wherein the solder that joins the insulating substrate and another member is a solder that is melted and solidified using a reactive metal foil as a heat source.
  21. 　前記はんだの主成分は、スズ－鉛合金、スズ－銀合金、スズ－ビスマス合金、スズ－アンチモン合金、スズ－銅合金またはスズ－インジウム合金であることを特徴とする請求項１８または１９に記載の半導体モジュール。 20. The main component of the solder is a tin-lead alloy, a tin-silver alloy, a tin-bismuth alloy, a tin-antimony alloy, a tin-copper alloy, or a tin-indium alloy. Semiconductor module.
  22. 　絶縁基板の一の主面に半導体チップを接合する第１の工程と、
    　前記半導体チップにワイヤもしくはリードフレームを接合する第２の工程と、
    　前記第１の工程および前記第２の工程の後、反応性金属箔を熱源としてはんだ又はめっきを溶融、凝固させ、前記絶縁基板の他の主面側にヒートシンクを接合する第３の工程と、
    　を備えることを特徴とする半導体モジュールの製造方法。     A first step of bonding a semiconductor chip to one main surface of an insulating substrate;
    A second step of bonding a wire or a lead frame to the semiconductor chip;
    After the first step and the second step, a third step of melting and solidifying solder or plating using a reactive metal foil as a heat source and bonding a heat sink to the other main surface side of the insulating substrate;
    A method for manufacturing a semiconductor module, comprising:
  23. 　前記第１の工程において、前記絶縁基板の他の主面に金属ベース板を接合し、
    　前記第３の工程において、前記金属ベース板に前記ヒートシンクを接合することを特徴とする請求項２２に記載の半導体モジュールの製造方法。     In the first step, a metal base plate is bonded to the other main surface of the insulating substrate;
    23. The method of manufacturing a semiconductor module according to claim 22, wherein, in the third step, the heat sink is joined to the metal base plate.
  24. 　前記第３の工程において、前記絶縁基板に前記ヒートシンクを接合することを特徴とする請求項２２に記載の半導体モジュールの製造方法。 23. The method of manufacturing a semiconductor module according to claim 22, wherein, in the third step, the heat sink is bonded to the insulating substrate.
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