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WO2006034683A3 - Verfahren zur vereinzelung von oberflächenmontierbaren halbleiterbauteilen und zur bestückung derselben mit aussenkontakten - Google Patents

Verfahren zur vereinzelung von oberflächenmontierbaren halbleiterbauteilen und zur bestückung derselben mit aussenkontakten Download PDF

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Publication number
WO2006034683A3
WO2006034683A3 PCT/DE2005/001676 DE2005001676W WO2006034683A3 WO 2006034683 A3 WO2006034683 A3 WO 2006034683A3 DE 2005001676 W DE2005001676 W DE 2005001676W WO 2006034683 A3 WO2006034683 A3 WO 2006034683A3
Authority
WO
WIPO (PCT)
Prior art keywords
components
separating surface
semiconductor
fitting external
component positions
Prior art date
Application number
PCT/DE2005/001676
Other languages
English (en)
French (fr)
Other versions
WO2006034683A2 (de
Inventor
Edward Fuergut
Horst Groeninger
Original Assignee
Infineon Technologies Ag
Edward Fuergut
Horst Groeninger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Edward Fuergut, Horst Groeninger filed Critical Infineon Technologies Ag
Publication of WO2006034683A2 publication Critical patent/WO2006034683A2/de
Publication of WO2006034683A3 publication Critical patent/WO2006034683A3/de
Priority to US11/692,943 priority Critical patent/US7485493B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Vereinzelung von oberflächenmontierbaren Halbleiterbauteilen (1) und zur Bestückung derselben mit Außenkontaktflächen. Dazu werden Halbleiterbauteilkomponenten auf einen metallischen Träger (4) in Zeilen (5) und Spalten (6) in entsprechenden Halbleiterbauteilpositionen (7) des metallischen Trägers (4) aufgebracht. Anschließend werden eine Vielzahl von Halbleiterbauteilpositionen (7) und die dort befindlichen Komponenten in eine Kunststoffgehäusemasse (8) eingebettet, wodurch eine Verbundplatte (3) entsteht, die anschließend durch Laserablation in einzelne Halbleiterbauteile (1) getrennt wird, welche mit Hilfe der Lasertechnik ihren Oberseiten (13) beschriftet werden. Diese beschrifteten Oberseiten (13) können dann auf eine Klebstofffolie aufgeklebt werden, so dass es möglich ist, die Unterseiten unter Beibehaltung der Halbleiterbauteilpositionen (7) frei zu legen.
PCT/DE2005/001676 2004-09-30 2005-09-22 Verfahren zur vereinzelung von oberflächenmontierbaren halbleiterbauteilen und zur bestückung derselben mit aussenkontakten WO2006034683A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/692,943 US7485493B2 (en) 2004-09-30 2007-03-29 Singulating surface-mountable semiconductor devices and fitting external contacts to said devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004048202A DE102004048202B4 (de) 2004-09-30 2004-09-30 Verfahren zur Vereinzelung von oberflächenmontierbaren Halbleiterbauteilen und zur Bestückung derselben mit Außenkontakten
DE102004048202.0 2004-09-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/692,943 Continuation US7485493B2 (en) 2004-09-30 2007-03-29 Singulating surface-mountable semiconductor devices and fitting external contacts to said devices

Publications (2)

Publication Number Publication Date
WO2006034683A2 WO2006034683A2 (de) 2006-04-06
WO2006034683A3 true WO2006034683A3 (de) 2006-08-24

Family

ID=36062178

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2005/001676 WO2006034683A2 (de) 2004-09-30 2005-09-22 Verfahren zur vereinzelung von oberflächenmontierbaren halbleiterbauteilen und zur bestückung derselben mit aussenkontakten

Country Status (3)

Country Link
US (1) US7485493B2 (de)
DE (1) DE102004048202B4 (de)
WO (1) WO2006034683A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006001601B4 (de) 2006-01-11 2008-06-26 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterwafers mit Rückseitenidentifizierung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010055856A1 (en) * 2000-06-13 2001-12-27 Su Tao Method of dicing a wafer from the back side surface thereof
JP2003034780A (ja) * 2001-04-23 2003-02-07 Furukawa Electric Co Ltd:The レーザーダイシング用粘着テープ
US20030109072A1 (en) * 2001-11-29 2003-06-12 Thorsten Meyer Process for producing a component module
FR2837620A1 (fr) * 2002-03-25 2003-09-26 Commissariat Energie Atomique Procede de transfert d'elements de substrat a substrat

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JP2000022044A (ja) * 1998-07-02 2000-01-21 Mitsubishi Electric Corp 半導体装置とその製造方法
US20020000665A1 (en) * 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP3827497B2 (ja) * 1999-11-29 2006-09-27 株式会社ルネサステクノロジ 半導体装置の製造方法
US6291272B1 (en) * 1999-12-23 2001-09-18 International Business Machines Corporation Structure and process for making substrate packages for high frequency application
US6566627B2 (en) * 2000-08-11 2003-05-20 Westar Photonics, Inc. Laser method for shaping of optical lenses
JP3906962B2 (ja) * 2000-08-31 2007-04-18 リンテック株式会社 半導体装置の製造方法
US7230316B2 (en) * 2002-12-27 2007-06-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having transferred integrated circuit
JP2004221187A (ja) * 2003-01-10 2004-08-05 Toshiba Corp 半導体装置の製造装置及びその製造方法
US6773961B1 (en) * 2003-08-15 2004-08-10 Advanced Semiconductor Engineering Inc. Singulation method used in leadless packaging process
US7282395B2 (en) * 2005-12-07 2007-10-16 Freescale Semiconductor, Inc. Method of making exposed pad ball grid array package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010055856A1 (en) * 2000-06-13 2001-12-27 Su Tao Method of dicing a wafer from the back side surface thereof
JP2003034780A (ja) * 2001-04-23 2003-02-07 Furukawa Electric Co Ltd:The レーザーダイシング用粘着テープ
US20030109072A1 (en) * 2001-11-29 2003-06-12 Thorsten Meyer Process for producing a component module
FR2837620A1 (fr) * 2002-03-25 2003-09-26 Commissariat Energie Atomique Procede de transfert d'elements de substrat a substrat

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 06 3 June 2003 (2003-06-03) *

Also Published As

Publication number Publication date
WO2006034683A2 (de) 2006-04-06
DE102004048202A1 (de) 2006-04-06
US20070232024A1 (en) 2007-10-04
DE102004048202B4 (de) 2008-05-21
US7485493B2 (en) 2009-02-03

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