WO2005086226A1 - Traitement thermique d’amelioration de la qualite d’une couche mince prelevee - Google Patents
Traitement thermique d’amelioration de la qualite d’une couche mince prelevee Download PDFInfo
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- WO2005086226A1 WO2005086226A1 PCT/FR2005/000541 FR2005000541W WO2005086226A1 WO 2005086226 A1 WO2005086226 A1 WO 2005086226A1 FR 2005000541 W FR2005000541 W FR 2005000541W WO 2005086226 A1 WO2005086226 A1 WO 2005086226A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Definitions
- the present invention relates to a method of forming a structure comprising a layer taken from a donor wafer, the donor wafer comprising before sampling a first layer of a semiconductor material comprising germanium, the method comprising the following successive steps : (a) formation of a weakening zone in the thickness of said first layer comprising germanium; (b) bonding of the donor wafer to a recipient wafer; I (c) supply of energy to weaken the donor wafer at the level of the embrittlement zone, this supply of energy possibly leading to separation of the layer removed from the donor wafer at the level of the embrittlement zone and thus to remove a layer comprising the remaining part of the first layer; (d) treatment of the sampled layer.
- Step (a) can be carried out by simple implantation of a single atomic species (for example of hydrogen) or by co-implantation of at least two different atomic species (for example of hydrogen and of helium), with an appropriate dosage and implantation energy of the species to be implanted.
- a single atomic species for example of hydrogen
- co-implantation of at least two different atomic species for example of hydrogen and of helium
- Step (b) of 'bonding the donor wafer to the receiving plate is typically done at the surface of the donor wafer which has undergone the implantation, via a bonding layer of dielectric material, such as SiO 2 .
- the bonding techniques typically used by those skilled in the art include a first bonding by molecular adhesion. We can refer to the document "Semiconductor Wafer Bonding Science and
- step (c) energy is supplied in thermal form to weaken the donor wafer at the embrittlement zone. This supply of thermal energy is likely to lead to the separation of the layer removed from the donor wafer at the embrittlement zone. thermal and / or mechanical form, may however be necessary to effectively separate the sampled layer, and consequently make it possible to detach and transfer it to the receiving wafer, thus making it possible to form a semiconductor-over-insulating structure
- SeOI such as an SOI structure (in the case where the sampled layer is made of silicon), SiGeOI (in the case where the sampled layer is made of germanium silicon), GeOI (in the case where the sampled layer is made of germanium), SGOI (in the case where the sampled layer comprises a layer of SiGe on which is placed a layer of constrained silicon), or sSOI (in the case where the sampled layer is in constrained silicon).
- SOI structure in the case where the sampled layer is made of silicon
- SiGeOI in the case where the sampled layer is made of germanium silicon
- GeOI in the case where the sampled layer is made of germanium
- SGOI in the case where the sampled layer comprises a layer of SiGe on which is placed a layer of constrained silicon
- sSOI in the case where the sampled layer is in constrained silicon
- a semiconductor-on-insulator structure 30 is schematically represented (consisting of a receiving plate 20 covered with the sampled layer 1 by means of an electrically insulating layer 5) which has, in its part semiconductor (ie the sampled layer 1), such a reduction in crystal quality.
- the sampled layer 1 comprises a defective zone 1A, this defective zone 1A comprising crystalline defects and an existing surface roughness.
- the defective zone 1A has a thickness typically around 150 nm for an atomic implantation of hydrogen.
- the implantation step may have caused in the sampled layer 1 a reduction in the crystal quality.
- Step (d) of processing the sampled layer 1 is then necessary to remove this defective zone 1A, and thus recover at least part of the healthy zone 1B of the sampled layer 1.
- CMP polishing mechanical or I mechanical-chemical planarization
- sacrificial oxidation is conventionally understood to mean a step comprising the operations of oxidizing the defective zone and removing the oxide layer then formed by means of chemical etching (for example by using hydrofluoric acid HF).
- chemical etching for example by using hydrofluoric acid HF.
- a four-step process is disclosed in document US2004 / 0053477, in which the sample of a strained Si layer is taken from a donor plate comprising a buffer layer of SiGe.
- Step (a) consists of implanting in the buffer layer and step (d) comprises removing the removed part of the buffer layer by polishing the SiGe surface and then selective etching of SiGe with respect to constrained Si.
- step (d) notably allows the desired layer to be obtained in the end with a good surface quality, without risking damaging it too much (which could be the case if a single polishing were used).
- the chemical etching implemented during this step (d) can in certain cases cause problems of at least partial detachment of the bonding interface (bonding carried out during step (b)).
- the chemical etching of step (d) can in particular delaminate at the edge of the bonding layer, that is to say attacking the latter at its level with the edge of the structure produced.
- this chemical etching requires prior preparation of the etching surface, typically carried out by mechanical polishing means. Indeed, this preparation for etching is still necessary to make up for some of the significant roughness which could subsequently cause etching that is too inhomogeneous, capable of creating through defects or holes in the remaining layer, but also making the free face of the final product rough. In addition, the presence of defects throughout the thickness of the sampled layer (and not only in the thickness of the defective zone) is also liable to cause inhomogeneous etching. However, the successive actions of polishing and chemical etching make the post-detachment finishing step (d) (as well as the entire sampling process) long, complex and costly from an economic point of view.
- a first object of the invention is to reduce the duration, the economic cost, and the number of treatment means, during step (d), of a sampled layer, and in particular no longer use mechanical means for polishing.
- a second objective of the invention is to produce a structure, such as a semiconductor-on-insulator SeOl structure, by taking a layer of semiconductor material comprising Ge, such as in particular a layer of SiGe.
- a third objective is to produce such a structure from a layer of better quality sampled.
- a fourth objective of the invention is to reduce the amount of material sacrificed during the treatment of the layer removed.
- a fifth objective of the invention is to propose a simple method for processing the sampled layer and which is easily integrated into the whole of the Smart-Cut® type sampling process.
- the present invention attempts to overcome these problems by proposing, according to a first aspect, a method of forming a structure comprising a layer taken from a donor wafer, the donor wafer comprising before taking a first layer of a semiconductor material comprising germanium, the method comprising the following steps: (a) forming a weakening zone in the thickness of said first layer comprising germanium; (b) bonding of the donor wafer to a recipient wafer; (c) supply of energy to weaken the donor plate at the level of the weakening zone, characterized in that step (a) is carried out by subjecting the donor plate to a co-implantation of at least two different atomic species , and in that step (c) is carried out by implementing a heat treatment at a temperature between 300
- step (c) is carried out at a temperature between 325 ° C and 375 ° C for about two hours ;
- the heat input from step (c) can lead to the separation of the donor wafer at the level of the embrittlement zone and thus to the removal of a layer comprising a part of the first layer;
- step (c) further comprises, after step (c), a step of additional energy supply adapted to separate the donor wafer at the embrittlement zone; - the additional energy supply is a thermal and / or mechanical supply;
- step (b) further comprises, before step (b), a step implemented by plasma activation so as to strengthen the bonding;
- - the co-location of step (a) is a co-location of helium and hydrogen;
- - the dosages of helium and hydrogen are chosen so that the helium dose represents 30 to 70% of the total dose, preferably 40 to 60% of the total dose;
- the donor wafer comprising before removal a second layer of a material different from that of said first layer, the etching operation is a selective etching of the remaining part after separation of the first layer from said second layer;
- a sacrificial oxidation is carried out of at least part of the remaining part of the first layer capable of removing material from said remaining part and strengthening the bonding interface;
- the method further comprises, after step (d), a crystal growth adapted to thicken said second layer;
- the first layer is made of Si1-xGex with 0 ⁇ x ⁇ 1 and the donor plate has a second layer (2) made of elastically constrained Si.
- the donor wafer comprises a support substrate in solid Si, a buffer structure in SiGe, a first layer (1) comprising Si1-xGex (x ⁇ O) and a second layer (2) in constrained Si; -
- the first layer is made of Si1-xGex with 0 ⁇ x ⁇ 1
- the donor plate (10) further comprises a second layer of elastically constrained Si and a third layer of S - x Ge x on the second layer.
- Step (d) comprises a selective etching of the remaining part of the first layer (1) with respect to the second layer (2).
- the donor plate (10) comprises a support substrate in solid Si, a buffer structure in SiGe, and a multilayer structure comprising alternately first layers (1A, 1 B, 1 C, 1 D, 1 E) in Si 1-x Ge x (x ⁇ O) and second layers (2A, 2B, 2C, 2D, 2E) in constrained Si, so that a plurality of samples can be taken from the same donor wafer (10).
- the method further comprises, before step (a), the formation of the strained layer at a deposition temperature between about 450 ° C and about 650 ° C.
- the method further comprises, before step (b), a step of forming a bonding layer on the donor wafer and / or on the receiving wafer, the bonding layer comprising an electrically insulating material, such as by example of SiO 2 , Si 3 N 4 or Si x O y N 2 .
- the invention proposes an application of said method for forming a structure, to the formation of a semiconductor-aur-insulator structure of the sSI, SGOI, SiGeOI or GeOI type.
- the invention proposes a semiconductor-on-insulator structure obtained after having implemented all the steps (a), (b) and (c) of the method according to the first aspect of the invention, and after removing the contact of the sampled layers with the remaining part of the donor wafer, this structure having low frequency and high frequency roughness less than 30 A RMS, as measured in profilometry 500 microns and AFM 2 * 2 // m 2 , anywhere on the plate.
- - Figure 1 shows a schematic sectional view of a semiconductor-on-insulator structure obtained after the implementation of a process
- Smart-Cut® according to the state of the art
- - Figure 2 shows a sectional view obtained by TEM by the Applicant of a semiconductor-on-insulator structure obtained after the implementation of a method according to the invention
- - Figures 3a to 3e schematically represent the different steps of a method according to the invention to form a structure comprising a layer taken from Smart-Cut®
- - Figures 4a and 4b schematically show a first variant according to the invention
- - Figures 5a and 5b schematically show a second variant according to the invention
- - Figure 6 illustrates the presence of pore type defects in a structure for which a post-separation heat treatment at 600 ° C has been implemented.
- FIGS. 3a to 3e a first method of sampling of a first layer 1 in SH- x Ge x (with xe] 0; 1]) and of a second layer 2 in elastically constrained Si is illustrated, starting from of a donor plate 10, to transfer them to a receiving plate 20, according to the invention.
- a donor wafer 10 comprising the first layer 1 in Si ⁇ - x Ge x and the second layer 2 in Si forced to take, is illustrated.
- a donor wafer 10 including Si-i- x Ge x comprises a solid Si substrate 5 on which has been formed, for example by crystal growth, a SiGe buffer structure (not shown) composed of different layers .
- the latter may have a gradual change in thickness of its composition in Ge, ranging from 0% at the level of the solid Si substrate to approximately 100 ⁇ % at the interface with the first layer 1 in Si 1- x Ge x (also preferentially formed by crystal growth).
- a second layer 2 of constrained Si is formed on the first layer 1 of Si ⁇ -x Ge x . In a first case, the growth of the second layer 2 is carried out in situ, directly in continuation of the formation of the first layer 1.
- the growth of the second layer 2 is produced after a slight stage of surface preparation of the underlying adaptation layer 2, for example by CMP polishing.
- the second Si layer 2 is advantageously formed by epitaxy using known techniques such as CVD and MBE techniques (abbreviations of "Chemical Vapor Deposition” and "Molecular Beam Epitaxy”).
- the silicon included in the second layer 2 is then forced by this first layer 1 to increase its nominal lattice parameter to make it substantially identical to that of its growth substrate and thus present internal elastic stresses in tension.
- a too large layer thickness, greater than a critical equilibrium thickness would indeed cause a relaxation of the stress in the thickness of the film towards the nominal mesh parameter of the silicon and / or a generation of faults.
- the critical equilibrium thickness is effectively linked to the temperature of deposition: it is all the more important as the deposition is carried out at low temperature).
- a weakening zone 4 is then formed in the donor plate 10 under the second layer 2.
- an implantation can be carried out to form the weakening zone in the thickness of the first layer 1 in Si- ⁇ -x Ge x (as shown in Figure 3b).
- This weakening zone 4 is formed by implantation of atomic species whose dosage, nature, and energy are chosen so as to determine an implant depth and a weakening level.
- the parameters determining the implantation of atomic species are adjusted so as to minimize the roughness appearing at the level of the embrittlement zone 4 after detachment. Indeed, the magnitude of the post-detachment roughness is partly caused by the parameters defining the implantation used, as we will see later.
- the implantation of atomic species is a co-implantation of atomic species (ie an implantation of, mainly, at least two different atomic species), such as for example a co-implantation of hydrogen. , and helium or argon or another rare gas or another suitable gas.
- atomic species ie an implantation of, mainly, at least two different atomic species
- the weakening zone 4 is generally finer than in the case of a simple implantation.
- the use of co-implantation will above all make it possible to obtain a post-detachment roughness less than the roughness obtained with a simple implantation of hydrogen or helium.
- the total dose in co-implantation thus typically represents 1/3 of the dose in implantation of a single species.
- the energy of the implantation is chosen so as to have an implant depth close to the depth of the first layer 1.
- an implant depth of the order of 300 to 600 nanometers can be obtained.
- the doses of helium and hydrogen are chosen so that the dose of helium represents 30 to 70% of the total dose, preferably 40 to 60% of the total dose.
- a step of bonding a receiving plate 20 with the side of the donor plate 10 having undergone co-implantation is carried out.
- the receiving plate 20 can be made of solid Si or other materials.
- a bonding layer may be formed, such as a layer comprising Si0 2 , Si 3 N4, Si x O y N z on one and / or the other of the Respective surfaces to be glued.
- the technique used to form this bonding layer may be a deposit, in order to avoid any deterioration of the stresses in the second layer; 2 or any consequent diffusion in the first layer 1.
- a preparation of the surfaces to be bonded can optionally be implemented, using known techniques of cleaning and preparation surface such as SC1 and SC2 solutions, ozonated solutions, etc. Bonding as such can firstly be carried out by molecular adhesion, being able to take account of the hydrophilicity which each of the two surfaces to be bonded presents. We can also implement plasma activation of one or both bonding surfaces just before bonding.
- Plasma activation makes it possible in particular to create pendant bonds, for example on an oxide surface, on the treated surface or surfaces, and therefore increases the bonding forces to be produced and reduces the number of defects at the bonding interface 6, as well as their influence on the quality of the collage.
- Such reinforcement of the bonding interface 6 will also have the advantage of making this interface much more resistant to the chemical attack of a subsequent etching (implemented at the time of the finishing of the surface of the sampled layer, by example during a selective etching step or a sacrificial oxidation step), and avoid delamination problems at the edge as previously discussed, which can typically occur for a bonding energy of less than about 0.8 J / m 2 .
- plasma activation can be implemented so that in the end, after bonding and after removal, the bonding energy is greater than or equal to about 0.8 J / m 2 .
- the plasma can for example be obtained from an inert gas, such as Ar or N 2 , or from an oxidizing gas, such as O 2 .
- Plasma activation can typically be performed at room temperature, below about 100 ° C. The use of this technique therefore also has the advantage of not causing significant problems of the diffusion of Ge from the first layer 1 in SiGe to the second layer
- step (b) an energy supply in thermal form is implemented during step (c) to weaken the donor wafer at the weakening zone.
- the thermal budget typically temperature and duration
- thermal energy also called “thermal embrittlement treatment” thereafter
- the embrittlement heat treatment is typically implemented at a temperature below 800 ° C, or at least below a limit temperature from which it is considered that the diffusion of Ge in the neighboring layers becomes detrimental.
- FIG. 3d the separation of the donor plate 10 is shown in a first part 10 ′ comprising a remainder of the first layer 1 ′′ and in a second part 30 comprising the other part of the first layer 1 ′ and the second layer 2.
- this separation can be carried out thanks to the supply of energy from the embrittlement heat treatment, however, when the supply of energy from the embrittlement heat treatment is not sufficient to lead to separation, the latter can be carried out by means of an additional energy supply (for example in the form of thermal and / or mechanical energy) sufficient to break the weak bonds at the level of the weakening zone 4, and I thus separate the donor wafer .;
- an additional energy supply for example in the form of thermal and / or mechanical energy
- the separation can be obtained at temperatures between about 300 ° C and about 600 ° C for longer or shorter times depending on whether, respectively, the temperature is lower or higher.
- a heat treatment it is possible to implement a heat treatment, directly after separation, with the aim of strengthening the bonding interface 6.
- this heat treatment for strengthening the bonding is implemented
- the heat treatment for reinforcing the bonding interface 6 is carried out at a temperature T 2 chosen lower than the temperature from which the Ge diffuses in a non-negligible manner in the thickness of the second layer 2.
- the heat treatment for reinforcing the bonding interface 6 can thus be carried out at a temperature T 2 chosen less than or equal to about 800 ° C.
- the temperature T 2 may for example be between 350 ° C and 800 ° C, maintained for 30 minutes to 4 hours.
- This heat treatment for strengthening the bonding can in particular, but not limited to, be implemented during a sacrificial oxidation step, during which an oxidation of the surface of the rest of the first layer 1 ′ is carried out (typically layer of SiGe) around 600/800 ° C, followed by removal of the oxide formed.
- sacrificial oxidation thus has the dual objective of strengthening the bonding interface and of removing at least part of the defective zone.
- This heat treatment for strengthening the bonding is carried out in an inert atmosphere (such as an Ar or N 2 atmosphere), slightly oxidizing or oxidizing.
- the layers removed then exhibit: - an improvement in the crystalline quality of its damaged parts during implantation (with reference to FIG. 3b) and during separation (with reference to FIG. 3d); - a smoothed surface, especially for high frequency roughness (HF roughness); - a bonding energy greater than approximately 0.8 J / m 2 (without plasma activation). It will be noted that the reduction in the thickness of the defective zone 1A is more particularly observed when the embrittlement zone is formed by co-implantation of atomic species.
- the surface roughness after detachment is also significantly reduced when a co-implantation is implemented rather than an implantation of a single species. This is mainly due to the fact, already mentioned previously, that the total dose of co-implanted species is much lower than the dose implanted when a single species is implanted.
- the co-location has the advantage, compared to the establishment of a single species, of reducing the thickness of the defective zone I, which in particular makes it possible to reduce or simplify the finishing treatments put implemented after detachment.
- co-location also has the advantage of reducing roughness, which also facilitates finishing treatments.
- such a heat treatment for strengthening the bonding may not be completely satisfactory. The Applicant has observed, in particular for heat treatments carried out at 600 ° C.
- FIG. 6 shows two views obtained by TEM (respectively on a scale of 10 nm for the top view and 2 nm for the bottom view) of an intermediate structure (intended to ultimately form a
- the Applicant proposes to carry out the embrittlement heat treatment step by performing a low temperature annealing, at a temperature between 300 ° C and 400 ° C, for example at approximately 350 ° C (+/- 25 ° C), for a period of between approximately 30 minutes and approximately four hours, for example for approximately two hours.
- a low temperature annealing at a temperature between 300 ° C and 400 ° C, for example at approximately 350 ° C (+/- 25 ° C)
- said embrittlement treatment may or may not lead to separation of the layer removed from the donor wafer.
- an additional supply of energy in thermal and / or mechanical form, can be carried out.
- results of roughness measurement on a SGOI structure at 20% Ge, carried out by the Applicant are presented below and relate to the case of a embrittlement heat treatment for approximately two hours, at a temperature substantially equal to 350 ° C. .
- the Applicant has thus carried out roughness measurements at both low frequencies (carried out using the Dektak® profilometry tool from the company Veeco Instruments Inc., 500 ⁇ m scanning) and high frequencies (carried out by scanning a surface 2 * 2 ⁇ m 2 with the tip of an AFM microscope with atomic force). The results of these measurements are expressed in average RMS (“Root Mean Square”) values.
- the treatment at low temperature (typically around 350 ° C.) is only likely to cause a temperature gradient of small amplitude (in comparison with that observed for treatment at higher temperature (for example 500 ° C or 600 ° C) in the oven enclosure.
- the detachment parameters identified here make it possible in particular to reduce the thickness of the defective zone, to limit the presence of defects and to minimize the surface roughness. In such conditions, any post-detachment finishing steps are facilitated; in particular, the use of a polishing / planarization operation is avoided or at least limited.
- the healthy zone 1B is much greater in proportion in the SiGeOI obtained. according to the invention only in -; the semiconductor-on-insulator according to the state of the art.
- a structure 30 is obtained comprising the receiving plate 20, the second layer 2 and the remaining part of the first layer 1 '. This structure 30 has an improved crystalline quality and a reduced roughness, without the need to carry out an intermediate polishing operation.
- the remaining part 1 ′ is free of pores or other defects, in particular near the surface.
- an electrically insulating bonding layer has been formed previously, between the second layer 2 and the wafer, receiver 20, one then obtains a SiGe / sSOI or Ge / sSOI structure.
- a finishing step is then implemented to remove the few slight roughness and the few crystalline defects remaining on the surface, such as the implementation of chemical etching, for example in the context of selective etching of a layer. compared to another or an engraving made during a sacrificial oxidation. Mechanical polishing means implemented prior to chemical etching to reduce surface roughness (and therefore to reduce inhomogeneities between the different points of the front engraving), need not necessarily be provided.
- the implementation of a co-implantation ensures a much smoother sampling surface than in the case of a simple implantation.
- the layer V of Si ⁇ - x Ge x is removed in order to obtain a final structure sSOI (cf. FIG. 3e).
- To selectively remove the layer 1 'of Si ⁇ - x Ge x it will be possible to implement selective etching by using for example HF: H 2 O 2 : CH 3 COOH, SC1 (NH 4 OH / H 2 O 2 / H 2 O), or HNA
- the etching time is directly correlated with the speed of the etching. It is typically around 5 minutes for 800A to burn with
- the donor plate 10 comprises, before sampling, a first layer 1 of Si 1-x Ge x , then a second layer 2 of constrained Si j and a third layer 3 in Si ⁇ -x Ge x which is located on the second layer
- the embrittlement zone is then formed according to the invention under the second layer 2, for example in the first layer 1.
- Selective etching of the Si ⁇ -x Ge x can then be implemented after detachment, in accordance with what has been seen previously, so as to ultimately produce a 30 SGOI structure (Strained-Silicon-On-Silicon Germanium- On-lnsulator structure, as represented in FIG. 6b) with a first layer 1 made of Si- ⁇ -x Ge x and a second layer 2 in constrained Si.
- the second layer 1 may optionally be thickened in Si constrained by crystal growth.
- a second selective chemical etching of the constrained Si can then be carried out, for example by means of chemical species based for example on KOH (potassium hydroxide), NH 4 OH (ammonium hydroxide), TMAH (ammonium tetramethyl hydroxide), ED.P (ethylene diamine / pyrocatechol / pyrazine).
- the second layer 2 in constrained Si plays here the role only of a stop layer protecting the third 3 in Si 1-x Ge x from the first chemical attack. We then obtain a SiGeOI structure (not shown).
- the donor plate 10 comprises, before sampling, a multilayer structure comprising alternately first layers 1A, 1 B, 1 C, 1 D, 1 E in S -x Ge x (x ⁇ 0) and second layers 2A, 2B, 2C, 2D, 2E in constrained Si. It is thus possible to carry out a plurality of samples according to the invention from the same donor plate 10, each sample then being followed by recycling of the remaining part of the donor plate 10 in order to prepare it for a new sample. Thus, for example, a first 30A sSOI structure and a second 30B sSOI structure will be formed from the same donor wafer 10.
- each constrained layer (referenced “2" in Figures 3a to 3e, "1” in Figures 4a and 4b, and “2A”, “2B”, “2C”, “2D” or “2E” in FIGS. 5a and 5b) of the donor plate 10 is thick, that is to say that it has a relatively large thickness without exhibiting relaxation of its elastic stresses.
- Sio, 8 Geo, 2 can typically reach a thickness comprised between approximately 30 nm and 60 nm without its constraints are relaxed in one way or another. If such a thick constrained layer is thus formed, care must be taken not to exceed a certain limit temperature (which is around the deposition temperature) in the treatments which follow, and in particular the treatments situated between the deposition of the layer and the detachment thereof carried out by Smart-Cut®, in order to avoid loosening of the stresses.
- a plasma activation before bonding (as discussed above) which is typically done at an ambient temperature below about 100 ° C.
- At least one bonding layer of dielectric material such as Si0 2
- this layer of dielectric material subsequently helping (ie after detachment) to keep the elastic stresses.
- a person skilled in the art can easily transpose the invention presented above to other materials than Si ⁇ -x Ge x or that Si constrained insofar as he knows the properties and the physical quantities associated with these other materials. For example, by taking the steps previously described in I with reference to FIGS.
- the person skilled in the art will be able to produce a final structure 30 AsGa on insulator, if he chooses a donor wafer 10 whose first layer 1 is made of Ge and the second layer 2 is in AsGa, if it implants (as described above) in the Ge of the first layer 1, if it then transfers the remainder 1 'of Ge and the second layer 2 of AsGa on a receiver plate 20 via an electrically insulating interface, and if it selectively removes the rest 1 ′ of the Ge using known selective etching techniques.
- One or more stop layers in AIGaN and / or in AIN may possibly have been provided in the GaN layer.
- selective etching comprising the removal of the GaN located above the barrier layer.
- a dry etching using a plasma gas comprising CH 2 , H 2 and possibly Ar can burn GaN more quickly than AIN.
- the barrier layer can then be removed to finally obtain a GaN layer having little surface roughness and good thickness homogeneity. It is also possible in the same way to adapt the method according to the invention to other layers taken from an alloy III-V or 111-V1. It will also be possible to extend all of these materials to those comprising carbon in small quantities (approximately 5%) or dopants.
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007501318A JP2007526644A (ja) | 2004-03-05 | 2005-03-07 | 採取薄膜の品質改善熱処理方法 |
EP05737043A EP1733423A1 (fr) | 2004-03-05 | 2005-03-07 | TRAITEMENT THERMIQUE D’AMELIORATION DE LA QUALITE D’UNE COUCHE MINCE PRELEVEE |
US11/233,318 US20060014363A1 (en) | 2004-03-05 | 2005-09-21 | Thermal treatment of a semiconductor layer |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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FR0402340A FR2867307B1 (fr) | 2004-03-05 | 2004-03-05 | Traitement thermique apres detachement smart-cut |
FR0402340 | 2004-03-05 | ||
FR0409980A FR2867310B1 (fr) | 2004-03-05 | 2004-09-21 | Technique d'amelioration de la qualite d'une couche mince prelevee |
FR0409980 | 2004-09-21 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/233,318 Continuation US20060014363A1 (en) | 2004-03-05 | 2005-09-21 | Thermal treatment of a semiconductor layer |
Publications (2)
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WO2005086226A1 true WO2005086226A1 (fr) | 2005-09-15 |
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FR (1) | FR2867310B1 (fr) |
WO (2) | WO2005086226A1 (fr) |
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KR20070085086A (ko) | 2007-08-27 |
US20050245049A1 (en) | 2005-11-03 |
EP1721333A1 (fr) | 2006-11-15 |
JP2007526644A (ja) | 2007-09-13 |
JP2007526645A (ja) | 2007-09-13 |
US7449394B2 (en) | 2008-11-11 |
FR2867310A1 (fr) | 2005-09-09 |
WO2005086227A1 (fr) | 2005-09-15 |
US7276428B2 (en) | 2007-10-02 |
WO2005086227A8 (fr) | 2006-10-19 |
KR100860271B1 (ko) | 2008-09-25 |
EP1733423A1 (fr) | 2006-12-20 |
FR2867310B1 (fr) | 2006-05-26 |
US20050196937A1 (en) | 2005-09-08 |
WO2005086226A8 (fr) | 2006-10-26 |
JP4876067B2 (ja) | 2012-02-15 |
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