WO2005083577A2

WO2005083577A2 - Integrated circuit with two different bus control units

Info

Publication number: WO2005083577A2
Application number: PCT/IB2005/050524
Authority: WO
Inventors: Jürg FRIES
Original assignee: Koninklijke Philips Electronics N. V.
Priority date: 2004-02-18
Filing date: 2005-02-10
Publication date: 2005-09-09
Also published as: WO2005083577A3

Abstract

The integrated circuit according to the invention comprises an IIC controller unit (TIC block) having an IIC clock output (SCL) and a SPI controller unit (SPI block) having a SPI clock output (SCK SPI), wherein the IIC clock output (SCL) and the SPI clock output (SCK SPI) are connectable to a clock pin (88).

Description

Integrated circuit

The invention relates to an integrated circuit having two different bus control units, namely an IlC-bus and a SPI-bus control unit.. In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes: • some intelligent control, usually a single-chip microcontroller; • general-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data converters; and • application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, or DTMF generators for telephones with tone dialing. To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, a bi-directional two-wire bus for efficient inter-IC control has been developed. This bus is often called the Inter IC, IIC or I2C bus. An IIC bus compatible device incorporates an on-chip interface which allows to communicate directly with each other IIC device via the IIC bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. For 8-bit-oriented digital control applications, such as those requiring microcontrollers, certain design criteria can be established. A complete system usually consists of at least one microcontroller and other peripheral devices such as memories and I/O expanders. Furthermore, the cost of connecting the various devices within the system must be minimized. Also, a system that performs a control function does not require high-speed data transfer. Overall efficiency depends on the devices chosen and the nature of the interconnecting bus structure. To produce a system satisfying these criteria, a serial bus structure is needed. Although serial buses do not have the throughput capability of parallel buses, they require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system. Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss, and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible or at least difficult. Also, a procedure has to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the bus clock source must be defined. All these criteria are involved in the specification of the IIC bus. Another bus interface for data transfer is the serial peripheral interface (SPI), which is essentially a three- wire serial bus for eight- or sixteen-bit-wide data transfer applications. The three wires transfer information between devices connected to the SPI bus. Each device on the bus acts simultaneously as a transmitter and receiver. Two of the three lines transfer data, one line for each direction, and the third line is a serial clock. Some devices may be only transmitters while others only receivers. Generally, a device that transmits usually possesses the capability to also receive data. A display connected to an SPI bus is an example of a receive-only device while EEPROM is a receive and transmit device. In many cases it is helpful to have the possibility to chose which of the two buses, the IIC bus or the SPI bus, shall be used. Therefore, both bus interfaces can be integrated on a chip.

From the prior art it is generally known to implement two different buses for different applications. For example, in Wakeley US patent 6 463 499 Bl, a data bus cable having SCSI and IIC bus functionality is described. For this functionality, two unused conductive wires of a conventional SCSI bus cable are used to transfer the desired IIC signal. But disadvantageously, in Wakeley the number of pins of the integrated circuit is not reduced. Fig. 1 shows such a prior art design. A block diagram of a conventional integrated circuit comprising two different bus control units, an IIC bus and a SPI bus block, is depicted. The integrated circuit 1 comprises beside the two bus controllers, the clock generator 3, and among other things a microcontroller unit MCU, which is provided for executing a program stored in a program memory 4, and which controls the IIC block and the SPI block. The IIC block serves for a two wire data transfer with external components. The SPI block serves for the same purpose. Which one of the two interfaces, IIC or SPI, is used depends on the technical boundary conditions. The pins of the chip which are necessary for clock and data transfer of the two interfaces are marked with the reference signs 80, 81, and 86 to 89. As can be seen in Fig. 1, the chip needs six pins for the external connection of the two interfaces. This embodiment leads to a increasing number of pins of the integrated circuit. This in turn makes the production of the chip expensive and unfortunately increases the number of wires. The present invention provides a remedy for this problem too.

It is thus an object of the invention to provide an integrated circuit which provides both buses, the IIC and the SPI bus, without increasing the number of pins over that of a circuit providing only a SPI bus. The problem is solved by an integrated circuit with the features according to independent device claim and by a method for multiple exploitation of a pin of an integrated circuit with the features according to the independent method claim. The integrated circuit according to the invention comprises an IIC controller unit having an IIC clock output and a SPI controller unit having a SPI clock output, wherein the IIC clock output and the SPI clock output are both connectable to a clock pin. The method for multiple exploitation of a pin of an integrated circuit according to the invention comprises a program code with which a controllable switch is controlled, wherein the switch either connects the IIC clock output or the SPI clock output to a clock pin of the integrated circuit. The dependent claims identify further advantageous features and developments of the present invention. In one embodiment of the invention, the IIC controller unit of the integrated circuit comprises a serial data output/input and the SPI controller unit comprises a data input, whereby both the data output/input and the data input are connected to data pin. In another embodiment of the integrated circuit according to the invention, the clock pin is connected directly to the IIC clock input/output and via a controllable switch to the SPI clock output. Advantageously, the controllable switch of the integrated circuit according to the invention can be controlled by a microcontroller unit. In another aspect of the method according to the invention, the IIC bus controller works as master. Alternatively thereto, in the method according to the invention the SPI bus controller works as master. Preferably, in the method according to the invention, the IIC bus controller sitches to a wait mode while the SPI bus controller transmits or receives data. As alternative to the above, the SPI bus controller can go into a wait mode while the IIC bus controller transmits or receives data. Finally, the integrated circuit according to the invention can be used in a digital cordless baseband chip. Subsequently, the invention is further explained with the drawings showing in

Fig. 1 a block diagram of a conventional integrated circuit comprising an IIC bus and a SPI bus block; Fig. 2 a block diagram of an integrated circuit according to the invention comprising an IIC bus and a SPI bus block; FIG. 1 shows a block diagram of a conventional integrated circuit comprising an IIC bus and a SPI bus block. As explained above, this prior art design comprises an integrated circuit with two different bus control units, an IIC bus and a SPI bus block. Apart from the two bus controllers, a clock generator 3 and a microcontroller unit MCU are provided, the latter executing one or more programs stored in a program memory 4 and controlling the IIC block and the SPI block. Both the IIC block and the SPI block serve for a two wire data transfer with external components. Which one of the two interfaces, IIC or SPI, is used at a particular time depends on the technical boundary conditions. The pins of the chip necessary for clock and data transfer of the two interfaces are marked with the reference signs 80, 81, and 86 to 89. Obviously, the chip in Fig. 1 requires six pins for the external connection of the two interfaces. Fig. 2 shows a block diagram of an integrated circuit 1' with an IIC bus and an SPI bus block according to the invention. A microcontroller unit MCU, a random access memory (RAM) 5, a program memory 4, and a clock generator 3 can be formed in the same way as in the embodiment illustrated in Fig. 1. The clock generator 3 generates the clock signals for the IIC controller, the SPI controller and the microcontroller unit MCU. The main advantage of the embodiment according to the invention as shown in Fig. 2 is, that at least two pins, namely the pins 80 and 81 from Fig.1 , can be omitted. The data output DO_SPI and the chip select output CS_SPI remain unchanged. However, the data input DI_SPI of the SPI block is directly connected inside the chip to the serial data connection SDA of the IIC block and only a single pin 86 for both, the data input DI_SPI and the serial data transfer SDA, is used. With that, a first pin, pin 81 in Fig.1 , can be left out. Furthermore, the clock output SCK_SPI of the SPI -block is connected via a controllable switch 2 to the clock output SCL of the IIC block and a pin 88 of the chip 1'. With that, a second pin, namely pin 80 in Fig. 1, can be omitted. The controllable switch 2 can be controlled by the microcontroller unit MCU, executing the corresponding program code. If an external IIC device, not shown in Fig. 2, is connected to the serial bus and has to transmit data to the IIC block, the IIC block sends an interrupt INT to the microcontroller unit MCU. The microcontroller unit MCU then induces the opening of the controllable switch 2, i.e. it gets nonconducting. Subsequently, the data may be transferred from and to the external IIC device. On the other hand, if the controllable switch 2 is closed, the SPI block works as master and is able to receive or transmit data from and to an external SPI device, not shown in Fig. 2. The invention can be implemented for example in a digital cordless baseband chip, e.g. for wireless data transfer. The IIC bus supports any IC fabrication process, for example NMOS, CMOS, or bipolar process. Two wires, the serial data line SDA and the serial clock line SCL, carry information between the devices connected to the IIC bus. Each device is recognized by a unique address so that it can be determined whether it is a microcontroller, LCD driver, memory, or keyboard interface. Each device can operate as either a transmitter or a receiver, depending on the function of the device. Obviously, an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. Some of the features of the IIC bus are: • Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL). • Each device connected to the IIC bus is software-addressable by a unique address and simple master/slave relationships exist at all times. Masters can operate as master-transmitters or as master-receivers. • The IIC bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters should initiate data transfer simultaneously. • Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the standard-mode, up to 400 kbit/s in the fast-mode, or up to 3.4 Mbit/s in the high-speed mode. • On-chip filtering rejects spikes on the bus data line to preserve data integrity. • Finally, the number of integrated circuits (ICs) that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF. For the IlC-bus the following terminology is used: A transmitter is a device that sends data to the IIC bus. The transmitter can either be a device which puts data on the bus of its own accord (a "master- transmitter"), or in response to a request from data from another device (a "slave- transmitter"). - A receiver is the device that receives data from the bus. A master is a component that initiates a transfer, generates the clock signal and terminates the transfer. A master can be either a transmitter or a receiver. A slave is a device addressed by the master. A slave can be either a receiver or a transmitter. A multi-master has the ability to co-exist for more than one master on the bus at the same time without collision or data loss. Arbitration is the prearranged procedure that authorizes only one master to take control of the bus at a time. - Synchronization is the prearranged procedure that synchronizes the clock signals provided by two or more masters. For the IIC bus transfer the following terminology is used: To indicate that the IlC-bus is free or idle, the serial data line SDA and the clock line SCL are both in the high state. - The data transfer begins with a start condition START or SR

(Repeated START). The level of the serial data line SDA changes from high to low, while the SCL clock line remains high. When this occurs, the IIC bus becomes "busy". While the clock line SCL is low, the data bit to be transferred can be applied to the single data line SDA by a transmitter. During this time, the data line SDA may change its state as long as the clock line SCL remains low. A high or low bit of information (DATA) on the SDA data line is valid during the high level of the clock line SCL. This level must be kept stable during the entire time that the clock remains high, to avoid misinteφretation as a Start or Stop condition. Data transfer is terminated by a stop condition STOP. This occurs when the level on the SDA data line passes from the low state to the high state, while the SCL clock line remains high. After termination of the data transfer, the bus becomes free again. The IlC-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. Masters are usually microcontrollers. In the following, the the case of a data transfer between two microcontrollers connected to the IIC bus is considered. This highlights the master- slave and receiver-transmitter relationships found on the IlC-bus. It should be noted that these relationships are not permanent, but depend on the direction of data transfer at the time concerned. The data transfer would proceed as follows: (1) Microcontroller A wants to send information to microcontroller B: First microcontroller A (master) addresses microcontroller B (slave) and then microcontroller A (master-transmitter) sends data to microcontroller B (slave- receiver). Finally, microcontroller A terminates the transfer. (2) If microcontroller A wants to receive information from microcontroller B: First microcontroller A (master) addresses microcontroller B (slave), and then microcontroller A (master-receiver) receives data from microcontroller B (slave- transmitter). Finally, microcontroller A terminates the transfer. Even in this latter case, the master (microcontroller A) generates the timing and terminates the transfer. The possibility of connecting more than one microcontroller to the IIC bus means that two or more masters could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event, an arbitration procedure has been developed. This procedure relies on the wired AND connection of all IIC interfaces to the IIC bus. If two or more masters try to put information onto the IIC bus, the first master to produce a logical "one" when the other produces a logical "zero" will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired AND connection to the clock line SCL.

More detailed information concerning the IIC bus can be found in "The I2C bus specification", Philips Semiconductors, document order number 9398 393 40011, Version 2.1, January 2000. The SPI bus employs a simple shift register data transfer scheme: Data is clocked out of and into the active devices in a first-in, first-out fashion. It is in this manner that SPI devices transmit and receive in full duplex mode. The devices connected to the SPI bus may also be classified as master or slave devices. A master device initiates an information transfer on the bus and generates clock and control signals. A slave device is controlled by the master through a slave select line, also called chip select (CS) line, and is active only when selected. Generally, a dedicated chip select line CS_SPI is required for each slave device. The same device can possess the functionality of a master and a slave, but at any point of time only one master can control the bus in a multi-master mode configuration. Any slave device that is not selected must release the slave output line, i.e. make the output high impedance. All lines on the SPI bus are unidirectional: The clock signal on the clock line SCK_SPI is generated by the master and is primarily used to synchronize data transfer. The master-out, slave-in (DO_SPI) line carries data from the master to the slave; the master-in, slave-out (DI_SPI) line carries data from the slave to the master. Each slave device is selected by the master via individual chip select lines CS_SPI. Information on the SPI bus can be transferred at a rate of near zero bits per second to 1 Mbit per second. Data transfer is usually performed in blocks of eight or sixteen bit and is synchronized by the serial clock SCK_SPI. One bit of data is transferred for each clock cycle. Four clock modes are defined for the SPI bus by the value of the clock polarity and the clock phase bits. The clock polarity determines the level of the clock idle state and the clock phase determines which clock edge places new data on the SPI bus. Any hardware device capable of operation in more than one mode will have some method of selecting the value of these bits. This multi-mode capability combined with the simple shift register architecture makes the SPI bus very versatile and allows many non-serial devices to be used as SPI slaves. As can be seen from the above description, the invention retains the full capability of both busses, the IIC bus and the SPI bus. IIC and SPI devices can be wired on the same bus and accessed one after the other. Having illustrated and described a preferred embodiment for a novel integrated circuit and a method for multiple exploitation of a pin of an integrated circuit, it is noted that variations and modifications in the method and the circuit can be made without departing from the spirit of the invention or the scope of the appended claims.

REFERENCE NUMBER LIST

1 integrated circuit or chip second embodiment of an integrated circuit

2 controllable switch 3 clock generator

4 program memory

5 RAM

80 pin

81 pin 86 - 89 pins

INT interrupt

D/A internal data and address bus

Claims

CLAIMS:

1. An integrated circuit, comprising

- an IIC controller unit (IIC block) having an IIC clock output (SCL),

- a SPI controller unit (SPI block) having a SPI clock output (SCK_SPI),

- wherein said IIC clock output (SCL) and said SPI clock output (SCK_SPI) are connectable to a clock pin (88).

2. The integrated circuit according to claim 1, wherein

- the IIC controller unit (IIC block) has a serial data output input (SDA),

- the SPI controller unit (SPI block) has a data input (DI_SPI), and - said data output/input (DI_SPI) and said data input (DI_SPI) are connected to a data pin (86).

3. The integrated circuit according to claim 1 or 2, wherein the clock pin (88) is connected directly to the IIC clock output (SCL) and via a controllable switch (2) to the SPI clock output (SCK_SPI).

4. The integrated circuit according to any of the claim 1 to 3, wherein the controllable switch (2) is controlled by a microcontroller unit (MCU).

5. A method for multiple exploitation of a pin of an integrated circuit according to any of the previous claims, wherein a controllable switch (2) is controlled by means of a program code, whereby either the IIC clock output (SCL) or the SPI clock output (SCK_SPI) is connected to the clock pin (88).

6. The method according to claim 5, wherein said IIC bus controller (IIC block) works as master.

7. The method according to claim 5 or 6, wherein said SPI bus controller

(SPI block) works as master.

8. The method according to any of the claims 5 to 7, wherein said IIC bus controller (IIC block) goes into a wait mode while the SPI bus controller (SPI block) transmits or receives data.

9. The method according to any of the claims 5 to 8, wherein said SPI bus controller (SPI block) goes into a wait mode while the IIC bus controller (IIC block) transmits or receives data.

10. Use of the integrated circuit according to any of the claims 1 to 4 or of the method according to any of the claims 5 to 9 in a digital cordless baseband chip.