CN117076360B - Circuit compatible with integrated circuit bus interface and serial peripheral interface - Google Patents
Circuit compatible with integrated circuit bus interface and serial peripheral interface Download PDFInfo
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- CN117076360B CN117076360B CN202311027246.3A CN202311027246A CN117076360B CN 117076360 B CN117076360 B CN 117076360B CN 202311027246 A CN202311027246 A CN 202311027246A CN 117076360 B CN117076360 B CN 117076360B
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- 230000002093 peripheral effect Effects 0.000 title claims abstract description 24
- 238000004891 communication Methods 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 13
- 235000015429 Mirabilis expansa Nutrition 0.000 description 3
- 244000294411 Mirabilis expansa Species 0.000 description 3
- 235000013536 miso Nutrition 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004146 energy storage Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- General Engineering & Computer Science (AREA)
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Abstract
The application provides a circuit compatible with an integrated circuit bus interface and a serial peripheral interface, comprising: and the voltage dividing circuit is used for judging the type of the communication interface of the main chip. The micro control unit comprises a first pin, a fifth pin, a ninth pin and a thirteenth pin which are connected with a serial peripheral device (SPI) interface, a third pin, a seventh pin and a fifteenth pin which are connected with an integrated circuit bus (I2C) interface, a second pin, a fourth pin, an eighth pin, a tenth pin, a twelfth pin and a sixteenth pin which are connected with a main chip, and a sixth pin, an eleventh pin and a fourteenth pin which provide power for the micro control unit. The low-dropout linear voltage regulator is used for realizing that the input voltage of the I2C interface is 3.3V; the positive pole of rectifier diode is connected with the power supply of I2C interface, and rectifier diode's negative pole is connected with the power supply of SPI interface.
Description
Technical Field
The present application relates to integrated circuit technology, and more particularly, to a circuit compatible with an integrated circuit bus interface and a serial peripheral interface.
Background
In the prior art, there are typically two communication interfaces on a chip, an integrated circuit bus interface (Inter-INTEGRATED CIRCUIT, I2C) and a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI). However, devices formed based on chips only support one communication interface, which would seriously affect the interaction between devices in the internet age of everything interconnection.
Disclosure of Invention
The embodiment of the application provides a circuit compatible with an integrated circuit bus interface and a serial peripheral interface, which comprises: the micro-control unit, the low dropout linear voltage regulator, the voltage dividing circuit and the rectifier diode; the micro control unit comprises a first pin, a fifth pin, a ninth pin and a thirteenth pin which are connected with an SPI interface, a third pin, a seventh pin and a fifteenth pin which are connected with an I2C interface, a second pin, a fourth pin, an eighth pin, a tenth pin, a twelfth pin and a sixteenth pin which are connected with a main chip, and a sixth pin, an eleventh pin and a fourteenth pin which provide power for the micro control unit;
The voltage dividing circuit is used for judging the type of a communication interface adopted by the main chip so that the micro control unit can select a pin to be conducted on the micro control unit according to the type of the communication interface; when the pin to be conducted is a normally open pin, the interface of the main chip application is the I2C interface; when the pin to be conducted is a normally-off pin, the interface of the main chip application is the SPI interface;
the low dropout linear voltage regulator is used for realizing that the input voltage of the I2C interface is 3.3V;
the positive pole of rectifier diode with the power supply of I2C interface is connected, rectifier diode's negative pole with the power supply of SPI interface is connected.
In some embodiments, the second pin is connected to a first universal interface of the main chip, the fourth pin is connected to a write data pin on the main chip, the eighth pin is connected to a read data pin on the main chip, the tenth pin is connected to a second universal interface of the main chip, the sixth pin is connected to ground, the fourteenth pin provides power to the main chip, the twelfth pin is connected to an address selection pin on the main chip, and the sixteenth pin is connected to a clock pin on the main chip.
In some embodiments, the first pin is connected to a clock pin of the SPI interface, the fifth pin is connected to a write data pin of the SPI interface, the ninth pin is connected to a read data pin of the SPI interface, and the thirteenth pin is connected to an address selection pin of the SPI interface.
In some embodiments, the third pin is connected with a data line pin of the I2C interface, the seventh pin is connected with a charging pin of the I2C interface, and the fifteenth pin is connected with a serial clock pin of the I2C interface.
In some embodiments, the first pin and the third pin of the low dropout linear regulator are respectively connected with the power input end of the I2C interface, and the fifth pin of the low dropout linear regulator is connected with a dc power supply through a capacitor.
In some embodiments, when the voltage dividing circuit determines that the general interface is at a high level, the type of the communication interface adopted by the main chip is determined to be the I2C interface;
And when the voltage dividing circuit determines that the universal interface is at a low level, judging the type of the communication interface adopted by the main chip as the SPI interface.
In some embodiments, the voltage divider circuit includes: two resistors; wherein, the resistance value of one resistor is 1.8 kiloohms, and the resistance value of the other resistor is 927 ohms.
In some embodiments, the I2C interface has a supply voltage of 3.3V and the SPI interface has a supply voltage of 5V.
In some embodiments, the main chip is connected with a reset circuit formed by a resistor and a capacitor.
In some embodiments, the main chip is connected with a filter capacitor, a storage capacitor and a pull-up resistor.
The voltage dividing circuit included in the circuit compatible with the integrated circuit bus interface and the serial peripheral interface is used for judging the type of the communication interface adopted by the main chip, so that the micro control unit selects a pin to be conducted on the micro control unit according to the type of the communication interface; when the pin to be conducted is a normally open pin, the interface of the main chip application is the I2C interface; and when the pin to be conducted is a normally-off pin, the interface of the main chip application is the SPI interface. Thus, the main chip can support two interfaces, namely an SPI interface and an I2C interface; the equipment based on the main chip can be interconnected with other equipment through two interfaces, so that the application scene and the data transmission efficiency of the equipment are improved.
Drawings
FIG. 1 is a schematic diagram of the structure of a circuit compatible with an integrated circuit bus interface and a serial peripheral interface provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a micro control unit included in a circuit compatible with an integrated circuit bus interface and a serial peripheral interface provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of a voltage divider circuit included in a circuit compatible with an integrated circuit bus interface and a serial peripheral interface provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of a low dropout linear regulator included in a circuit compatible with an integrated circuit bus interface and a serial peripheral interface provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of rectifier diodes included in a circuit compatible with an integrated circuit bus interface and a serial peripheral interface provided by an embodiment of the present application;
FIG. 6 is a schematic diagram of a connection circuit provided by an embodiment of the present application;
fig. 7 is an alternative schematic diagram of a main chip according to an embodiment of the present application.
Detailed Description
The present application will be further described in detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present application more apparent, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a specific order or sequence, as permitted, to enable embodiments of the application described herein to be practiced otherwise than as illustrated or described herein. In the following description, the term "plurality" refers to at least two.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.
Fig. 1 is a schematic diagram of a circuit configuration of a compatible integrated circuit bus interface and a serial peripheral interface according to an embodiment of the present application, where the compatible integrated circuit bus interface and the serial peripheral interface circuit at least include: the device comprises a micro control unit, a low dropout linear voltage regulator, a voltage dividing circuit and a rectifier diode.
The micro control unit comprises a first pin, a fifth pin, a ninth pin and a thirteenth pin which are connected with the SPI interface, a third pin, a seventh pin and a fifteenth pin which are connected with the I2C interface, a second pin, a fourth pin, an eighth pin, a tenth pin, a twelfth pin and a sixteenth pin which are connected with the main chip, and a sixth pin, an eleventh pin and a fourteenth pin which provide power for the micro control unit.
The voltage dividing circuit is used for judging the type of a communication interface adopted by the main chip so that the micro control unit can select a pin to be conducted on the micro control unit according to the type of the communication interface; when the pin to be conducted is a normally open pin, the interface of the main chip application is the I2C interface; and when the pin to be conducted is a normally-off pin, the interface of the main chip application is the SPI interface.
The low dropout linear regulator is used for realizing that the input voltage of the I2C interface is 3.3V.
The positive pole of rectifier diode with the power supply of I2C interface is connected, rectifier diode's negative pole with the power supply of SPI interface is connected.
The constituent structures of the micro control unit, the voltage dividing circuit, the low dropout linear regulator, and the rectifier diode shown in fig. 1 will be described below based on fig. 2 to 5, respectively.
FIG. 2 is a schematic diagram of a micro control unit including a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, an eighth pin, a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin, a fourteenth pin, a fifteenth pin, and a sixteenth pin; the first to sixteenth pins are denoted by numerals 1 to 16 in fig. 2, respectively.
The first pin, the fifth pin, the ninth pin and the thirteenth pin are connected with the SPI interface. The third pin, the seventh pin, and the fifteenth pin are connected with the I2C interface. Specifically, the first pin is connected with a clock (SCK) pin of the SPI interface, the fifth pin is connected with a write data (MOSI) pin of the SPI interface, the ninth pin is connected with a read data (MISO) pin of the SPI interface, and the thirteenth pin is connected with an address selection (ADDSEL) pin of the SPI interface. The third pin is connected with a data line (SDA) pin of the I2C interface, the seventh pin is connected with a charging pin (CHG) of the I2C interface, and the fifteenth pin is connected with a Serial Clock (SCL) pin of the I2C interface.
The second pin, the fourth pin, the eighth pin, the tenth pin, the twelfth pin and the sixteenth pin are connected with the main chip. Specifically, the second pin is connected with a first universal interface (co mmsel 1) of the main chip, the fourth pin is connected with a write data (MOSI) pin on the main chip, the eighth pin is connected with a read data (MISO) pin on the main chip, the tenth pin is connected with a second universal interface (commsel 2) of the main chip, the sixth pin is connected with the eleventh pin and the ground, the fourteenth pin provides power for the main chip, the twelfth pin is connected with an address selection (ADDSEL) pin on the main chip, and the sixteenth pin is connected with a clock (SCL/SCK) pin on the main chip.
The sixth pin, the eleventh pin and the fourteenth pin provide power for the micro control unit. Specifically, the sixth pin and the eleventh pin are both connected to the ground, and the fourteenth pin is an input voltage.
The circuit compatible with the integrated circuit bus interface and the serial peripheral interface provided by the embodiment of the application comprises a voltage dividing circuit, as shown in fig. 3, which comprises: and two resistors, wherein one resistor has a resistance of 1.8 kiloohms and the other resistor has a resistance of 927 ohms. In FIG. 3, two resistors are respectively represented by R11 and R12, wherein the resistance value of R11 is 927 ohms, and the resistance value of R12 is 1.8 kiloohms; the ratio of errors in the resistance values of R11 and R12 may be 5%.
The voltage dividing circuit shown in fig. 3 is used for judging the type of a communication interface adopted by the main chip, so that the micro control unit selects a pin to be conducted on the micro control unit according to the type of the communication interface; when the pin to be conducted is a Normally Open (NO) pin, the interface of the main chip application is the I2C interface; when the pin to be conducted is a normally-off (NC) pin, the interface of the main chip application is the SPI interface.
In the implementation, when the voltage dividing circuit determines that the general interface (COMMSEL in fig. 3) is at a high level, the type of the communication interface adopted by the main chip is determined to be the I2C interface; and when the voltage dividing circuit determines that the universal interface is at a low level, judging the type of the communication interface adopted by the main chip as the SPI interface.
The circuit compatible with the integrated circuit bus interface and the serial peripheral interface provided by the embodiment of the application comprises a schematic diagram of a low dropout linear regulator, as shown in fig. 4, a first pin and a third pin of the low dropout linear regulator are respectively connected with a power input end (denoted by VDDIN in fig. 4) of the I2C interface, and a fifth pin of the low dropout linear regulator is connected with a direct current power supply (denoted by VDD in fig. 4) through a capacitor (denoted by C17 in fig. 4). In the embodiment of the application, the low dropout linear regulator is used for realizing that VDDIN and VDD of the I2C interface are both 3.3V.
The circuit compatible with the integrated circuit bus interface and the serial peripheral interface provided by the embodiment of the application comprises a schematic diagram of a rectifier diode, as shown in fig. 5, wherein the positive electrode of the rectifier diode is connected with a power supply (VBUS) of the I2C interface, and the negative electrode of the rectifier diode is connected with a power supply (VDDIN) of the SPI interface.
Wherein VBUS has a value of 5V and VDDIN has a value of 3.3V. A capacitance may be connected between VBUS and VDDIN.
The circuit compatible with the integrated circuit bus interface and the serial peripheral interface provided by the embodiment of the application further comprises a connecting circuit, wherein the connecting circuit comprises 4 resistors R5, R6, R7 and R8 respectively. R5, R6, R7 and R8 may also be referred to as pull-up resistors, with R5 and R8 having a resistance of 47 kiloohms and R6 and R7 having a resistance of 3.3 kiloohms; the error ratio of the four resistors is less than 5%. A schematic diagram of a connection circuit is shown in fig. 6, in which RESET represents RESET, SS represents chip select, SCL/SCK represents clock pins, MOSI represents write data, MISO represents read data, ADDSEL/CHG0 represents address select, VDDIN represents power supply input, VBUS represents power supply, and S1 and S2 represent reserved blank pins.
In the circuit compatible with the integrated circuit bus interface and the serial peripheral interface provided by the embodiment of the application, when the I2C interface is used, VBUS provides power for the micro control unit and the main chip, the voltage dividing circuit judges COMMSEL to be at a high level, the main chip is communicated through the I2C interface, and the micro control unit selects the normally open pin to be conducted. When the SPI interface is used, VDDIN provides power for the micro-control unit and the main chip, the rectifier diode is reversely cut off, the voltage dividing circuit judges COMMSEL to be at a low level, the main chip is communicated through the SPI interface, and the micro-control unit is normally Guan Yinjiao to be conducted.
An optional schematic diagram of a main chip provided by the embodiment of the application is shown in fig. 7, wherein the main chip is connected with a reset circuit formed by a resistor and a capacitor; the resistance of the reset circuit is R2 shown in fig. 7, and the capacitance of the reset circuit is C2 shown in fig. 7. The main chip shown in fig. 7 is also connected with a filter capacitor, an energy storage capacitor and a pull-up resistor. Wherein, filter capacitor includes: c3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16 and C17. The energy storage capacitor is C1. The pull-up resistor includes R1, R3, R4, R5, R6, R7, and R8.
As an example, the main chip provided by the embodiment of the application may be a vehicle-mounted touch chip.
In the embodiment of the application, the connection circuit shown in fig. 6 may be used to connect the main chip shown in fig. 7 with the circuits shown in fig. 2 to 5, where the circuits are compatible with the integrated circuit bus interface and the serial peripheral interface, so that when the main chip uses the I2C interface, VBUS provides power for the micro control unit and the main chip, the voltage dividing circuit determines COMMSEL that the voltage dividing circuit is at a high level, and the main chip communicates through the I2C interface, and then the micro control unit selects the normally open pin to be turned on. When the SPI interface is used by the main chip, VDDIN provides power for the micro-control unit and the main chip, the rectifier diode is reversely cut off, the voltage dividing circuit judges COMMSEL to be at a low level, the main chip is communicated through the SPI interface, and the micro-control unit is normally Guan Yinjiao to be conducted. Therefore, the main chip can be compatible with the I2C interface and the SPI interface, and any one of the I2C interface and the SPI interface can be adopted as required when equipment applying the main chip communicates with other equipment; the application scene and the data transmission efficiency of the equipment applying the main chip are improved.
The above is merely an example of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and scope of the present application are included in the protection scope of the present application.
Claims (8)
1. Circuitry compatible with integrated circuit bus interface and serial peripheral interface, characterized in that the circuitry comprises a plurality of logic circuits
The circuit comprises: the micro-control unit, the low dropout linear voltage regulator, the voltage dividing circuit and the rectifier diode; wherein,
The micro control unit comprises a first pin, a fifth pin, a ninth pin and a thirteenth pin which are connected with an SPI interface of the serial peripheral equipment, a third pin, a seventh pin and a fifteenth pin which are connected with an I2C interface of the integrated circuit bus, a second pin, a fourth pin, an eighth pin, a tenth pin, a twelfth pin and a sixteenth pin which are connected with a main chip, and a sixth pin, an eleventh pin and a fourteenth pin which provide power for the micro control unit; the second pin is connected with a first universal interface of the main chip, the fourth pin is connected with a write data pin on the main chip, the eighth pin is connected with a read data pin on the main chip, the tenth pin is connected with a second universal interface of the main chip, the sixth pin is connected with the eleventh pin and the ground, the fourteenth pin provides power for the main chip, the twelfth pin is connected with an address selection pin on the main chip, and the sixteenth pin is connected with a clock pin on the main chip;
The voltage dividing circuit is used for judging the type of a communication interface adopted by the main chip so that the micro control unit can select a pin to be conducted on the micro control unit according to the type of the communication interface; when the voltage dividing circuit determines that the universal interface is at a high level, judging the type of the communication interface adopted by the main chip as the I2C interface; when the voltage dividing circuit determines that the universal interface is at a low level, judging the type of the communication interface adopted by the main chip as the SPI interface; when the pin to be conducted is a normally open pin, the interface of the main chip application is the I2C interface; when the pin to be conducted is a normally-off pin, the interface of the main chip application is the SPI interface;
the low dropout linear voltage regulator is used for realizing that the input voltage of the I2C interface is 3.3V;
the positive pole of rectifier diode with the power supply of I2C interface is connected, rectifier diode's negative pole with the power supply of SPI interface is connected.
2. The circuit of claim 1, wherein the first pin is connected to a clock pin of the SPI interface, the fifth pin is connected to a write data pin of the SPI interface, the ninth pin is connected to a read data pin of the SPI interface, and the thirteenth pin is connected to an address select pin of the SPI interface.
3. The circuit of claim 1, wherein the third pin is connected to a data line pin of the I2C interface, the seventh pin is connected to a charging pin of the I2C interface, and the fifteenth pin is connected to a serial clock pin of the I2C interface.
4. The circuit of claim 1, wherein a first pin and a third pin of the low dropout linear regulator are respectively connected to a power input terminal of the I2C interface, and a fifth pin of the low dropout linear regulator is connected to a dc power supply through a capacitor.
5. The circuit of claim 1, wherein the voltage divider circuit comprises: two resistors; wherein, the resistance value of one resistor is 1.8 kiloohms, and the resistance value of the other resistor is 927 ohms.
6. The circuit of claim 1, wherein the I2C interface has a supply voltage of 3.3V and the SPI interface has a supply voltage of 5V.
7. The circuit of claim 1, wherein the main chip is connected with a reset circuit comprising a resistor and a capacitor.
8. The circuit of claim 1, wherein the main chip is connected with a filter capacitor, a storage capacitor and a pull-up resistor.
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| CN202311027246.3A CN117076360B (en) | 2023-08-15 | 2023-08-15 | Circuit compatible with integrated circuit bus interface and serial peripheral interface |
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