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WO1998031051A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO1998031051A1
WO1998031051A1 PCT/JP1997/000058 JP9700058W WO9831051A1 WO 1998031051 A1 WO1998031051 A1 WO 1998031051A1 JP 9700058 W JP9700058 W JP 9700058W WO 9831051 A1 WO9831051 A1 WO 9831051A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
pads
leads
semiconductor device
cantilevered
Prior art date
Application number
PCT/JP1997/000058
Other languages
French (fr)
Japanese (ja)
Inventor
Yasuhisa Hagiwara
Hiroaki Tanaka
Fujio Ito
Hiromichi Suzuki
Sigeki Tanaka
Original Assignee
Hitachi, Ltd.
Hitachi Microcomputer System, Ltd.
Hitachi Kokkai Semiconductor, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Microcomputer System, Ltd., Hitachi Kokkai Semiconductor, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/000058 priority Critical patent/WO1998031051A1/en
Publication of WO1998031051A1 publication Critical patent/WO1998031051A1/en

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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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Definitions

  • the present invention relates to a semiconductor device, in particular, a power semiconductor integrated circuit (ic;) in which a large current needs to flow, and a pad (external terminal) of a semiconductor chip on which a semiconductor integrated circuit including various drive circuits is mounted.
  • the present invention relates to a semiconductor device in which wires are electrically connected to leads and a technique effective when applied to a method of manufacturing the semiconductor device.
  • a pad provided on a semiconductor integrated circuit (ic) chip and each inner lead are individually wire-bonded.
  • ic semiconductor integrated circuit
  • a serial-parallel conversion driver circuit Alternatively, some semiconductor integrated circuits with built-in power circuits use multiple external connection terminals for power supply and ground (GND). This is because a large current flows through the power supply circuit and, eventually, the ground line, and the above-described method is adopted to reduce the resistance.
  • GND power supply and ground
  • a semiconductor device for a 32-bit central processing unit has a plurality of power terminals and ground terminals (for example, 40 each) on the peripheral surface of the device.
  • a common lead continuous in a series and / or a common lead for a series of grounds is provided in a small number of ground leads among the multiple leads.
  • a plurality of first pads and a plurality of second pads arranged substantially in parallel on one side of a semiconductor chip having a square planar shape are interposed with a plurality of first pads and a plurality of second pads.
  • the semiconductor device in which each of the leads is electrically connected, the semiconductor device is connected to each of a plurality of first pads among a plurality of first and second pads arranged on the semiconductor chip.
  • a plurality of first leads extending in a first direction intersecting the arrangement direction of the first pad and the second pad, and the arrangement of the first pad and the second pad.
  • the plurality of first pads and each of the plurality of first leads are electrically connected to each other via a wire, and the plurality of first pads are arranged in the same second direction.
  • the second lead connected to each of the second pads is formed of the same lead frame as the plurality of first leads, and the plurality of second pads and the plurality of first leads are formed. Between the first lead and the first lead, and a wire shorter than a wire connecting the first pad and the first lead is interposed between the second lead and the second lead.
  • a semiconductor device in which each of the second pads is electrically connected is disclosed in Japanese Patent Application Laid-Open No. 5-21691.
  • Japanese Patent Application Laid-Open No. 5-216964 discloses a semiconductor device including a heat sink laminated with a material interposed therebetween and a package body for sealing the heat sink with a resin.
  • the present inventor has found the following problems as a result of studying the above-mentioned conventional technology.
  • the inner lead refers to a lead extending inside the sealing body
  • the outer lead refers to a lead extending outside the sealing body.
  • An object of the present invention is to reduce the number of external connection terminals used for the same purpose in a semiconductor integrated circuit, to increase the number of signal input / output pins, and to reduce the resistance of a common current path such as a power supply and GND. It is an object of the present invention to provide a technology capable of freely setting the arrangement position of a common outer lead such as a power supply and G: ⁇ 'D in a semiconductor device capable of reducing the power consumption.
  • Another object of the present invention is to provide a semiconductor integrated circuit having the same purpose.
  • Another object of the present invention is to reduce the number of external connection terminals used for the same purpose in a semiconductor integrated circuit, increase the number of signal input / output pins, and reduce the resistance of a common current path such as a power supply and GND. It is an object of the present invention to provide a semiconductor device which can reduce heat dissipation and improve heat radiation efficiency.
  • the present invention relates to a plurality of first pads (external terminals) and a plurality of second pads (outer terminals) arranged substantially parallel to one side of a circuit element forming surface of a semiconductor chip having a square planar shape.
  • Each of the plurality of first leads connected to each of the plurality of first pads extends in a first direction that intersects the arrangement direction of the first and second pads.
  • the first and second pads are arranged in the same second direction as the arrangement direction of the first and second pads.
  • Each of the plurality of first pads and each of the plurality of first leads are electrically connected via a wire.
  • a cantilevered second lead connected to each of the plurality of second pads is provided between the plurality of second pads and the plurality of first leads in the second direction. Is arranged to extend.
  • the plurality of first leads and second leads are made of the same lead frame.
  • Each of the plurality of second pads is electrically connected to the cantilevered second lead via a short wire that is shorter than a wire connecting the first pad and the first lead.
  • the semiconductor chip, the first lead, and the cantilevered second lead are supported by a heat radiating plate via an insulative adhesive film.
  • the cantilevered second lead of the present invention is a lead used for a common purpose such as an earth line, GND, and power supply.
  • the cantilevered second lead of the present invention is provided with an adhesive flow stopping means for stopping a flow of a pelleting adhesive for pelletizing a semiconductor chip on the insulating adhesive film. It is provided at a position closer to the semiconductor chip than the pad is disposed on the second suspension rod.
  • the adhesive flow stopping means of the present invention comprises a slit or a step.
  • the present invention provides a plurality of first pads and a plurality of second pads arranged substantially in parallel with one side of a device forming surface of a semiconductor chip having a square planar shape, This is a method for manufacturing a semiconductor device in which each of a plurality of leads is electrically connected via a wire.
  • Each of the plurality of first leads connected to each of the plurality of first pads is extended in a first direction intersecting the arrangement direction of the first and second pads. And arranging them in the same second direction as the arrangement direction of the first pad and the second pad.
  • the semiconductor chip After silvering a predetermined portion of the lead frame, the semiconductor chip is fixed to a predetermined position of the heat sink with a pelleting adhesive via an insulating adhesive film, and the first pad and the second pad are fixed.
  • the two pads and the first and second lead inner leads are electrically connected by bonding, and the power supply or GND is externally connected to the second lead by wire bonding.
  • the inner lead for the lead to be taken out is electrically connected and sealed with resin.
  • FIG. 1 is a plan view showing a schematic configuration of a resin-sealed semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
  • FIG. 3 is a plan view showing an entire configuration of a lead frame with a spreader according to the resin-sealed semiconductor device of the first embodiment.
  • FIG. 4 is a cross-sectional view taken along line BB of FIG.
  • FIG. 5 is a plan view showing the overall schematic configuration of the resin-encapsulated semiconductor device of Embodiment 1 in a state where pellet bonding is completed.
  • FIG. 6 is a cross-sectional view taken along line CC of FIG.
  • FIG. 7 is a plan view showing the overall schematic configuration of the resin-encapsulated semiconductor device according to the present embodiment in a completed bonding state.
  • FIG. 8 is a cross-sectional view taken along the line DD ′ of FIG.
  • FIG. 9 is a flowchart of the method for manufacturing the resin-encapsulated semiconductor device of the first embodiment.
  • FIG. 10 is a plan view showing a schematic configuration of a lead frame of a resin-sealed semiconductor device according to a second embodiment of the present invention.
  • FIG. 11 is a cross-sectional view taken along line EE ′ of FIG.
  • FIG. 12 is a plan view showing a schematic configuration of a main part of a resin-sealed semiconductor device according to a third embodiment of the present invention.
  • FIG. 13 is a cross-sectional view taken along line FF ′ of FIG.
  • FIG. 14 is a sectional view showing a schematic configuration of a main part of a modification of the third embodiment of the present invention.
  • FIG. 15 is a plan view showing a schematic configuration of a lead frame of the resin-sealed semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 16 is a sectional view taken along the line GG ′ of FIG.
  • FIG. 17 is a plan view showing an overall schematic configuration of a resin-bonded semiconductor device according to Embodiment 4 of the present invention in a bonding completed state.
  • FIG. 18 is a cross-sectional view taken along line HH of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a plan view showing a schematic configuration of a resin-sealed semiconductor device according to Embodiment 1 of the present invention
  • FIG. 2 is a sectional view taken along line AA ′ of FIG.
  • the resin-encapsulated semiconductor device has an element forming surface of a semiconductor chip 1 having a square planar shape.
  • a plurality of first pads 1A for signals and a plurality of second pads 1B for power supplies are provided substantially parallel to one side of the (surface).
  • the surface (rear surface) of the semiconductor chip 1 opposite to the element forming surface is fixed to the upper surface of the heat spreader 2 by a pelleting material (paste) 4 with an insulating adhesive 3 interposed therebetween. .
  • the signal first pad 1A and the power supply second pads 1B are electrically connected to the respective leads 6 via wires 15 respectively. .
  • the second pad extending in the first direction intersecting the arrangement direction of the pads 1A and the second pads 1B and being the same as the arrangement direction of the first pads 1A and the second pads 1B. It is arranged toward the direction.
  • Each of the plurality of first pads 1A and each of the plurality of first leads 6A are electrically connected via a wire 15.
  • the cantilevered second leads (lead bars for power supply) connected to the plurality of second pads 1B, respectively.
  • 6B is formed from the same lead frame as the plurality of first leads 6A, and a second lead is formed between the plurality of second pads 1B and the plurality of first leads 6A. It is arranged to extend in the direction.
  • the cantilevered second lead 6B is connected to the first lead 1A and the first lead 6A via wires 5A and 5B, which are shorter than the wire 5 connecting the first pad 1A and the first lead 6A. Each of the plurality of second pads 1B is electrically connected.
  • the semiconductor chip 1, the first lead 1A, and cantilever The second lead 6B is supported by a heat spreader (heat radiating plate) 2 with an insulating adhesive film (insulating adhesive coating film) 3 interposed therebetween. Then, the semiconductor chip 1, the heat spreader (heat radiating plate) 2, the bonding wires — 5, 5A, 5B, the inner lead portion of the lead 6A, and the cantilevered second lead 6B are sealed. Sealed with resin (mold resin) 7.
  • the cantilevered second lead 6B is a lead used for a common purpose such as a ground line, a ground connection, and a power supply.
  • the outer lead 6B1 of the cantilevered second lead 6B is a power lead bar
  • the inner lead 6B2 is a GND lead bar.
  • the cantilever second lead 6B is composed of four leads.
  • one side of the cantilevered second lead 6B is supported by a corner portion (hanging portion) of a normal lead frame, and the other two sides are semiconductors.
  • a Y-shaped lead extending around the chip 1 and separated (floating) from the element forming surface, that is, a lead from the power supply lead 6B1 and a ground lead 6B2.
  • the semiconductor chip 1 has a structure in which two power supply lead bars 16 B 1 and a GND lead 6 B 2 are formed on one side of the semiconductor chip 1.
  • Each of the four cantilevered second leads 6B is provided at a corner of the lead frame in a cantilevered structure.
  • the signal first lead 6A and the cantilevered second lead 6B are made of, for example, a Cu alloy having a thickness of 0.15 mm.
  • the reason why the hanging portion of the cantilevered second lead 6B is made thicker and a portion of the lead bar is divided into two portions and made thinner is that the hanging portion increases the strength,
  • The-part is for reducing the influence of thermal stress.
  • the bent shape of the part of the lead bar is the pad arranged at a part of the corner of the chip and the pad arranged near the center of each side of the chip. This is to keep the distance to the part of the dove constant and to keep the length of the wire when bonding the wire as constant as possible.
  • the heat spreader 2 is made of, for example, an electrolytic copper foil having a thickness of 0.15 mm.
  • the insulating adhesive film 3 is made of, for example, a thermoplastic resin having a thickness of 0.02 rn m (for example, using a thermoplastic polyimide resin or a thermoplastic epoxy resin) or a thermosetting resin (for example, And thermosetting polyimide resin).
  • the pellet attaching material 4 is made of, for example, an epoxy adhesive containing an Ag filler having a thickness of 0.01 to 0.05 mm.
  • the thickness of the semiconductor chip 1 is about 0 4 and Bondi ring wire in mm using the example A u line diameter, in the sealing resin 7 using the mold resin:.
  • FIG. 9 is a diagram illustrating the manufacturing of the resin-encapsulated semiconductor device according to the first embodiment. It is a process flow chart of the method.
  • the manufacturing method of the resin-encapsulated semiconductor device of the first embodiment is as shown in FIG. 3 by first etching or stamping a 0.15 mm thick CLi material.
  • a lead frame having such a pattern is manufactured (step 101).
  • Ag plating is applied to the bonded end of the first lead 6A and a part of the cantilevered second lead 6B.
  • Step 102 As shown in FIG. 4, a heat spreader 2 made of a Cu foil coated with a thermoplastic resin or a polyimide resin of a thermosetting resin (insulating adhesive film 3) is used.
  • Step 103 Bonding by thermocompression bonding (Step 103) Next, using an epoxy-based pelletizing material 4 for the part of the heat spreader 2 of the lead frame with a heat spreader, as shown in FIGS. As shown, the semiconductor chip (pellet) 1 is bonded (step 104). Then, as shown in FIGS. 7 and 8, each of the lead wires of the semiconductor chip 1 and the inner lead of the first lead 6A and the cantilevered second lead 6B is bonded by Au wire bonding. 6 B 1 and 6 B 2 are electrically connected, and the respective lead bars 6 B 1 and 6 B 2 are electrically connected to the inner lead of the first lead 6 A (step 10). Five ) .
  • the semiconductor chip 1, the heat spreader 2, the bonding wires 5, 5A, 5B, the inner lead portion of the first lead 6A, and the cantilever second lead 6B are sealed. Seal with resin 7 (Step 106) Then, apply Ag plating to the lead portion of the first lead 6A and the lead portion of the cantilevered second lead 6B.
  • the application (Step 107), the lead frame is cut and molded to complete a resin-sealed semiconductor device (Step 108).
  • the cantilevered second lead 6B By forming the cantilevered second lead 6B using the hanging lead in the above manufacturing process, the cantilevered second lead 6B (power supply lead bar or GXD Even if the lead bar is used, the semiconductor device with a high yield can be obtained because it is fixed by the heat spreader 2.
  • cantilevered second lead 6B (power supply lead or GND) Since the lead bar is not connected to the inner lead of the first lead 6A, it can be connected to the power supply terminal or the GND terminal at any position in the semiconductor chip 1, and Can be connected to the inner lead at the position. As a result, the power supply voltage in the semiconductor chip can be stabilized, and a semiconductor device with good electrical characteristics can be obtained.
  • the cantilevered second lead 6B (lead bar for power supply or lead bar for GND) is fixed by a heat spreader, the cantilevered second lead 6B is one-sided.
  • the cantilevered second lead 6B (power supply lead bar or GND lead bar) occurs in the semiconductor manufacturing process. For this reason, for example, the degree of freedom in designing the power supply lead bar or the GND lead bar can be obtained. Further, since it is not connected to the inner lead of the first lead 6A, it is possible to form a power supply lead bar having a plurality of potentials.
  • FIG. 10 is a plan view showing a schematic configuration of a lead frame of the resin-encapsulated semiconductor device according to the second embodiment of the present invention.
  • FIG. 11 is a line E--E 'of FIG. It is sectional drawing cut
  • the resin-encapsulated semiconductor device of the second embodiment includes a cantilevered second lead 6B (lead for power supply or GND) having the shape and structure shown in FIGS. 3 and 4 of the first embodiment.
  • the lead bar has the shape shown in FIGS. 10 and 11. That is, one side is supported at the corner of the normal lead frame, and the other two sides extend to the central part around the periphery of the semiconductor chip 1 and are separated (floated) from the circuit element forming surface.
  • This is a cantilevered second lead 6 B ′ having a structure in which one lead bar whose center is cut off by 6 B 3 and 6 B 4 is formed.
  • the reason why the lead bar is cut at the center and the slit is provided between the lead bars 6B3 and 6B4 is to relieve thermal stress and to expand the use and application range. belongs to.
  • the cantilevered second lead 6B of the second embodiment can have the same function as the cantilevered second lead 6B of the first embodiment with a simple shape of one lead bar. . That is, the second lead of the cantilever suspension of the present invention has a lead structure in which a suspension lead is used as a power supply lead or a GND lead. Other types of cantilever hanging lead structures may be used.
  • FIG. 12 is a plan view showing a schematic configuration of a main part of a resin-encapsulated semiconductor device according to a third embodiment of the present invention.
  • FIG. 13 is a sectional view taken along line FF ′ of FIG. It is sectional drawing.
  • the resin-encapsulated semiconductor device includes a cantilevered second lead (lead for power supply or lead bar for GND) having the shape and structure shown in FIGS. 10 and 11 of the second embodiment. )
  • the slit 6S is provided on each of the two lead bars 6B3 and 6B4 of 6B ', and the outside thereof is plated with Ag 6M.
  • the slit 6 S is coated with the Ag in the slit 6 S. It is provided so as not to protrude into the 6 M area and contaminate the bonding area.
  • the cantilevered second lead (for power supply) Lead bar or GND lead bar) This is provided to ensure the reliability of wire bonding to 6B '.
  • Ag plating is performed to bond to the cantilevered second lead 6B ', but if Ag plating is applied to the entire cantilevered second lead 6B', the semiconductor device can be mounted on a substrate. Due to the heat, the adhesion between the Ag plating surface and the resin is generally weaker than the adhesion between the Cu substrate surface and the sealing resin (mold resin). Therefore, the cantilevered second lead 6B 'and the sealing resin (mold resin) (Resin) peels off. This peeling may break the bonding wire (Au wire) connected to the cantilevered second lead 6B '. Therefore, as in the third embodiment, two lead bars are used. Ag plating is applied only to the outside of the portion where the slit 6S is provided on each of 6B3 and 6B4, so that the bonding wire joined to the cantilevered second lead 6B 'can be used. Au wire is not cut
  • the pellet attachment material (paste) 4 is attached to the cantilevered second lead (lead bar for power supply or lead bar for GND).
  • a step 6D is provided so as not to contaminate the part to be bonded and the bonding wire (Au wire 1) of 6B, and the bonding wire (Au wire). 1) Bonding property may be ensured.
  • the step 6D can be formed by, for example, press working.
  • FIG. 15 is a plan view showing a schematic configuration of a lead frame of the resin-encapsulated semiconductor device according to the fourth embodiment of the present invention
  • FIG. FIG. 3 is a plan view cut along a G ′ line.
  • the resin-encapsulated semiconductor device of the fourth embodiment includes a cantilevered second lead (power supply lead bar or GND lead bar) having the shape and structure shown in FIGS. 10 and 11 of the second embodiment. Ag plating is applied only to the parts necessary for bonding the wires of the two leads 6B3 and 6B4, as shown in Figs. 15 and 16. It was done.
  • a cantilevered second lead power supply lead bar or GND lead bar
  • the common lead for supplying the power supply voltage is cantilevered (one end is free in a lead frame state), the deformation of the common lead can be reduced, and the electrical reliability is reduced. It is possible to provide a semiconductor device which is expensive and has a large number of signal input / output pins.
  • the width of the common lead for supplying the power supply voltage is wider than the signal lead width, so that the inductance of the common voltage supply path such as the power supply and GND can be reduced, so that the noise margin can be increased. it can.
  • the fixed part of the common lead for supplying power supply voltage is located at a part of the corner where there is no signal lead, so the position of the common outer lead such as power supply and GND can be freely arranged. be able to.
  • the arrangement position of a common outer lead such as a power supply and GND can be freely arranged.
  • the number of external connection terminals used for the same purpose in a semiconductor integrated circuit can be reduced, the number of signal input / output pins can be increased, and the resistance of a common current path such as power supply and GND can be reduced. Manufacturing time can be reduced.
  • the number of external connection terminals used for the same purpose in a semiconductor integrated circuit can be reduced, the number of signal input / output pins can be increased, and the resistance of a common current path such as power supply 0 and GND can be reduced.
  • the heat radiation efficiency can be improved.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A semiconductor device provided with a line of first pads (1A) and second pads (1B) arranged along one side edge on the element forming surface of a rectangular semiconductor chip (1). First leads which are respectively connected to the first pads (1A) are extended in a first direction crossing the line of the first and second pads (1A and 1B) and overhung second leads (6B) respectively connected to the second pads (1B) are arranged in a second direction which is the same as the line of the pads (1A and 1B) between a plurality of second pads (1B) and a plurality of first leads. In addition, the first leads and overhung second leads (6B) are supported by a heat radiating plate (2) with an insulating adhesive film in between.

Description

明 細 書  Specification
半導体装置及びその製造方法 Semiconductor device and manufacturing method thereof
技術分野 Technical field
本発明は、 半導体装置、 特に、 大電流を流す必要のあるパワー半導 体集積回路 （ i c；) 、 各種の駆動回路を構成した半導体集積回路が搭 載される半導体チップのパッ ド （外部端子） と リードとをワイヤ一で 電気的に接続する半導体装置及びその製造方法に適用して有効な技術 に関する。  The present invention relates to a semiconductor device, in particular, a power semiconductor integrated circuit (ic;) in which a large current needs to flow, and a pad (external terminal) of a semiconductor chip on which a semiconductor integrated circuit including various drive circuits is mounted. The present invention relates to a semiconductor device in which wires are electrically connected to leads and a technique effective when applied to a method of manufacturing the semiconductor device.
背景技術 Background art
半導体集積回路に用いられるリ一ドフレームには各種の形状のもの がある。 と ころで、 通常は半導体集積回路 （ i c ) チップに設けられ たパッ ドと各インナ一リードとは個別にワイヤ一ボンディ ングされる のであるが、 例えば、 シ リアル—パラ レル変換ドライバー回路、 或い は、 パワー回路等を内蔵した半導体集積回路のよう に電源用、 グラン ド （G N D ) 用に複数の外部接続端子を使用しているものもある。 こ れは、 電源回路、 ひいてはアースラインに大電流が流れるためであり 、 抵抗を低減させるために前記方法が採用されている。  There are various shapes of lead frames used in semiconductor integrated circuits. Here, usually, a pad provided on a semiconductor integrated circuit (ic) chip and each inner lead are individually wire-bonded. For example, a serial-parallel conversion driver circuit, Alternatively, some semiconductor integrated circuits with built-in power circuits use multiple external connection terminals for power supply and ground (GND). This is because a large current flows through the power supply circuit and, eventually, the ground line, and the above-described method is adopted to reduce the resistance.
例えば、 3 2ビッ トの中央演算処理装置 （C P U ) 用の半導体素子 は、 該素子の周囲表面等に電源端子やグランド端子を複数 （4 0個づ つ等） 持っている。  For example, a semiconductor device for a 32-bit central processing unit (CPU) has a plurality of power terminals and ground terminals (for example, 40 each) on the peripheral surface of the device.
そして、 このような半導体素子を用いて半導体装置を構成する場合. 多数本のリ一ド先端内方の空間部分に、 複数本のり一ド先端前方を横 切るように、 リード先端と所定間隔離して、 前記多数本のリードのう ちの少数本の電源用のリ一ドに一連に連続する共通リ一ド又は前記多 数本のリードのうちの少数本のグランド用のリードに一連に連続する グランド用の共通リ一ドの両方又はそのいずれか一方を備えた半導体 装置用リードフ レ一ムが、 特開平 1— 9 3 1 5 6号公報に開示されて いる。 And when configuring a semiconductor device using such a semiconductor element. In the space inside the tips of the many leads, it is separated from the tips of the leads by a predetermined distance so as to cross the front of the tips of the plurality of leads. A common lead continuous in a series and / or a common lead for a series of grounds is provided in a small number of ground leads among the multiple leads. A lead frame for a semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 1-93156.
また、 平面形状が方形状に形成された半導体チップの一辺にほぼ平 行に配列された複数個の第 1パッ ド、 複数個の第 2パッ ドのそれぞれ に、 ワイヤ一を介在して、 複数本のリードのそれぞれが電気的に接続 される半導体装置において、 前記半導体チップに複数個配列された第 1パッ ド及び第 2パッ ドのうち、 複数個の第 1パッ ドのそれぞれに接 続される複数本の第 1 リードのそれぞれが、 前記第 1パッ ド及び第 2 パッ ドの配列方向と交差する第 1方向に延在され、 かつ、 この第 1 パ ッ ド及び第 2パッ ドの配列方向と同一の第 2方向に向って配列され、 前記複数個の第 1パッ ドのそれぞれと複数本の第 1 リードのそれぞれ とがワイヤ一を介在して電気的に接続され、 前記複数個配列された第 1パッ ド及び第 2パッ ドのうち、 複数個の第 2パッ ドのそれぞれに接 続される第 2 リードが、 前記複数本の第 1 リードと同一のリードフ レ —ムから形成され、 かつ、 複数個の第 2パッ ドと複数本の第 1 リード との間に第 2方向に延在して配置されるとともに、 前記第 1パッ ドと 第 1 リードとを接続するワイヤ一に比べて短いワイヤ一を介在して、 前記第 2 リードに前記複数個の第 2パッ ドのそれぞれが電気的に接続 される半導体装置が、 特開平 5— 2 1 6 9 1号公報に開示されている また、 電源、 接地電極を含む多数の電極を有する半導体チップと、 この半導体チップと、 この半導体チップの周辺に配置されてその内方 端が前記電極にヮィヤーを介して接続された状態で外方端が装置外に 導出される複数のリードと、 これらリードの一部がチップ上に延びて 前記チップ上に絶縁材を介して積層される導体板と、 チップ下に延び て前記チップ下に絶縁材を介して積層される放熱板と、 これらを樹脂 封止するパッケージ本体とを備えてなる半導体装置が、 特開平 5— 2 1 6 9 4号公報に開示されている。 In addition, a plurality of first pads and a plurality of second pads arranged substantially in parallel on one side of a semiconductor chip having a square planar shape are interposed with a plurality of first pads and a plurality of second pads. In a semiconductor device in which each of the leads is electrically connected, the semiconductor device is connected to each of a plurality of first pads among a plurality of first and second pads arranged on the semiconductor chip. A plurality of first leads extending in a first direction intersecting the arrangement direction of the first pad and the second pad, and the arrangement of the first pad and the second pad. The plurality of first pads and each of the plurality of first leads are electrically connected to each other via a wire, and the plurality of first pads are arranged in the same second direction. Of the first and second pads The second lead connected to each of the second pads is formed of the same lead frame as the plurality of first leads, and the plurality of second pads and the plurality of first leads are formed. Between the first lead and the first lead, and a wire shorter than a wire connecting the first pad and the first lead is interposed between the second lead and the second lead. A semiconductor device in which each of the second pads is electrically connected is disclosed in Japanese Patent Application Laid-Open No. 5-21691. A semiconductor chip having a large number of electrodes including a power supply and a ground electrode; and a semiconductor chip disposed around the semiconductor chip and having an inner end connected to the electrode via a wire. A plurality of leads whose ends are led out of the device; a conductor plate in which some of these leads extend on the chip and are laminated on the chip via an insulating material; Japanese Patent Application Laid-Open No. 5-216964 discloses a semiconductor device including a heat sink laminated with a material interposed therebetween and a package body for sealing the heat sink with a resin.
本発明者は、 前記従来の技術を検討した結果、 以下の問題点を見い だした。  The present inventor has found the following problems as a result of studying the above-mentioned conventional technology.
前記従来の技術では、 アウターリードとィンナ一リ一ドの配設位置 がユーザの仕様によって固定されるため、 ユーザの仕様が異なると、 ユーザの仕様に応じて新規のリードフ レームを作製しなければならな い。 このため、 新規なリー ドフ レームの作製に時間と経費がかかると いう問題があった。  In the above-mentioned conventional technology, the arrangement positions of the outer lead and the inner lead are fixed according to the user's specification. Therefore, if the user's specification is different, a new lead frame must be produced according to the user's specification. No. For this reason, there has been a problem that it takes time and money to produce a new lead frame.
本願において、 ィンナーリ一ドとは封止体の内部に延在するリ一ド を言い、 アウターリードとは封止体の外部に延在するリ一ドを首う。 本発明の目的は、 半導体集積回路における同一の用途に用いられる 外部接続端子の数を削減し、 信号の入出力ピンが多ピンにできるとと もに、 電源、 G N D等共通の電流経路の抵抗を低減できる半導体装置 において、 電源、 G :\' D等共通のアウターリードの配設位置を自由に 設定するこ とが可能な技術を提供するこ とにある。  In the present application, the inner lead refers to a lead extending inside the sealing body, and the outer lead refers to a lead extending outside the sealing body. An object of the present invention is to reduce the number of external connection terminals used for the same purpose in a semiconductor integrated circuit, to increase the number of signal input / output pins, and to reduce the resistance of a common current path such as a power supply and GND. It is an object of the present invention to provide a technology capable of freely setting the arrangement position of a common outer lead such as a power supply and G: \ 'D in a semiconductor device capable of reducing the power consumption.
本発明の他の目的は、 半導体集積回路における同一の用途に用いら れる外部接続端子の数を削減し、 信号の入出力ピンが多ピンにできる とともに、 電源、 G N D等共通の電流経路の抵抗を低減できる半導体 装置の製造時間を低減することが可能な技術を提供することにある。 本発明の他の目的は、 半導体集積回路における同一の用途に用いら れる外部接続端子の数を削減し、 信号の入出力ピンが多ピンにできる とともに、 電源、 G N D等共通の電流経路の抵抗を低減でき、 かつ、 放熱効率を向上できる半導体装置を提供することにある。 Another object of the present invention is to provide a semiconductor integrated circuit having the same purpose. Technology that can reduce the number of external connection terminals that can be used, increase the number of signal input / output pins, and reduce the resistance of semiconductor devices that can reduce the resistance of common current paths such as power supply and GND. Is to do. Another object of the present invention is to reduce the number of external connection terminals used for the same purpose in a semiconductor integrated circuit, increase the number of signal input / output pins, and reduce the resistance of a common current path such as a power supply and GND. It is an object of the present invention to provide a semiconductor device which can reduce heat dissipation and improve heat radiation efficiency.
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記 述及ぴ添付図面から明らかになるであろう。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
1 . 本発明は、 平面形状が方形状に形成された半導体チップの回 路素子形成面の一辺にほぼ平行に配列された複数個の第 1パッ ド （外 部端子） 及び第 2パッ ド （外部端子） のそれぞれに、 ワイヤ一を介在 して、 複数本のリ一ドのそれぞれが電気的に接続された半導体装置で める。  1. The present invention relates to a plurality of first pads (external terminals) and a plurality of second pads (outer terminals) arranged substantially parallel to one side of a circuit element forming surface of a semiconductor chip having a square planar shape. A semiconductor device in which each of the plurality of leads is electrically connected to each of the external terminals via a wire.
前記複数個の第 1パッ ドのそれぞれに接続される複数本の第 1 リ一 ドのそれぞれが、 前記第 1パッ ド及び第 2パク ドの配列方向と交差す る第 1方向に延在され、 かつ、 この第 1パッ ド及び第 2パッ ドの配列 方向と同一の第 2方向に向って配列されている。  Each of the plurality of first leads connected to each of the plurality of first pads extends in a first direction that intersects the arrangement direction of the first and second pads. The first and second pads are arranged in the same second direction as the arrangement direction of the first and second pads.
前記複数個の第 1パッ ドのそれぞれと複数本の第 1 リ一ドのそれぞ れとがワイヤーを介在して電気的に接続されている。  Each of the plurality of first pads and each of the plurality of first leads are electrically connected via a wire.
前記複数個の第 2パッ ドのそれぞれに接続される片持ち吊り第 2 リ —ドが、 複数個の第 2パッ ドと複数本の第 1 リードとの間に第 2方向 に延在して配置されている。 A cantilevered second lead connected to each of the plurality of second pads is provided between the plurality of second pads and the plurality of first leads in the second direction. Is arranged to extend.
前記複数本の第 1 リードと第 2 リ一ドは同一のリードフレームから なっている。  The plurality of first leads and second leads are made of the same lead frame.
前記第 1パッ ドと第 1 リードとを接続するヮィャ一に比べて短いヮ ィャ一を介在して、 前記片持ち吊り第 2 リードに前記複数個の第 2パ ッ ドのそれぞれが電気的に接続され、 前記半導体チップ、 第 1 リード、 及び片持ち吊リ第 2 リードは絶緣性接着膜を介在して放熱板で支持さ れているものである。  Each of the plurality of second pads is electrically connected to the cantilevered second lead via a short wire that is shorter than a wire connecting the first pad and the first lead. The semiconductor chip, the first lead, and the cantilevered second lead are supported by a heat radiating plate via an insulative adhesive film.
2 . 本発明の前記片持ち吊り第 2 リードはアースライン、 G N D 用、 電源用等の共通の目的で使用されるリ'一ドである。  2. The cantilevered second lead of the present invention is a lead used for a common purpose such as an earth line, GND, and power supply.
3 . 本発明の前記片持ち吊り第 2 リードには、 前記絶緣性接着膜 の上に半導体チップをペレツ ト付けするためのペレッ ト付け接着剤の 流れを止める接着剤流れ止め手段が当該片持ち吊り第 2 リ一ド上のパ ッ ドの配設位置より半導体チップ側の位置に設けられている。  3. The cantilevered second lead of the present invention is provided with an adhesive flow stopping means for stopping a flow of a pelleting adhesive for pelletizing a semiconductor chip on the insulating adhesive film. It is provided at a position closer to the semiconductor chip than the pad is disposed on the second suspension rod.
4 . 本発明の前記接着剤流れ止め手段は、 スリ ッ トもしくは段差 からなる。  4. The adhesive flow stopping means of the present invention comprises a slit or a step.
5 . 本発明は、 平面形状が方形状に形成された半導体チップの素 子形成面の一辺にほぼ平行に配列された複数個の第 1パッ ド及び複数 個の第 2パッ ドのそれぞれに、 ワイヤ一を介在して、 複数本のリ一ド のそれぞれが電気的に接続される半導体装置の製造方法である。  5. The present invention provides a plurality of first pads and a plurality of second pads arranged substantially in parallel with one side of a device forming surface of a semiconductor chip having a square planar shape, This is a method for manufacturing a semiconductor device in which each of a plurality of leads is electrically connected via a wire.
前記複数個の第 1パッ ドのそれぞれに接続される複数本の第 1 リ一 ドのそれぞれを、 前記第 1パッ ド及び第 2パジ ドの配列方向と交差す る第 1方向に延在させ、 かつ、 この第 1パッ ド及び第 2パッ ドの配列 方向と同一の第 2方向に向けて配列させ、 前記複数個の第 2パッ ドの それぞれに接続される片持ち吊り第 2 リードを、 複数個の第 2パッ ド と複数本の第 1 リードとの間に第 2方向に延在して配置させたバタ一 ン （形状） のリードフレームを形成する。 Each of the plurality of first leads connected to each of the plurality of first pads is extended in a first direction intersecting the arrangement direction of the first and second pads. And arranging them in the same second direction as the arrangement direction of the first pad and the second pad. A butter-shaped (shape) lead in which a cantilevered second lead connected to each is extended in the second direction between a plurality of second pads and a plurality of first leads. Form a frame.
そのリ一ドフレームの所定部分を銀めつきした後、 放熱板の所定位 置に前記半導体チップを絶縁性接着膜を介在してペレッ 卜付け接着剤 で固定し、 前記第 1パッ ド及び第 2パッ ドと、 前記第 1 リード及び第 2 リードのィンナ一リードとを、 ヮィャ一ボンディ ングによリ電気的 に接続し、 前記第 2 リードとワイヤ一ボンディングにより電源もしく は G N Dを外部へ取リ出すリ一ド用のインナ一リードとを電気的に接 続して、 樹脂で封止するものである。 図面の簡単な説明  After silvering a predetermined portion of the lead frame, the semiconductor chip is fixed to a predetermined position of the heat sink with a pelleting adhesive via an insulating adhesive film, and the first pad and the second pad are fixed. The two pads and the first and second lead inner leads are electrically connected by bonding, and the power supply or GND is externally connected to the second lead by wire bonding. The inner lead for the lead to be taken out is electrically connected and sealed with resin. BRIEF DESCRIPTION OF THE FIGURES
第 1図は本発明の実施の形態 1の樹脂封止型半導体装置の概略構成 を示す平面図である。  FIG. 1 is a plan view showing a schematic configuration of a resin-sealed semiconductor device according to Embodiment 1 of the present invention.
第 2図は第 1図の A— A ' 線で切った断面図である。  FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
第 3図は本実施形態 1の樹脂封止型半導体装置に係るスプレツダ付 リ一ドフレームの全体構成を示す平面図である。  FIG. 3 is a plan view showing an entire configuration of a lead frame with a spreader according to the resin-sealed semiconductor device of the first embodiment.
第 4図は第 3図の B— B， 線で切った断面図である。  FIG. 4 is a cross-sectional view taken along line BB of FIG.
第 5図は本実施形態 1の樹脂封止型半導体装置のペレッ トボンディ ング完了状態の全体概略構成を示す平面図である。  FIG. 5 is a plan view showing the overall schematic configuration of the resin-encapsulated semiconductor device of Embodiment 1 in a state where pellet bonding is completed.
第 6図は第 5図の C— C， 線で切った断面図である。  FIG. 6 is a cross-sectional view taken along line CC of FIG.
第 7図は本実施形態丄 の樹脂封止型半導体装置のヮィヤーボンディ ング完了状態の全体概略構成を示す平面図である。  FIG. 7 is a plan view showing the overall schematic configuration of the resin-encapsulated semiconductor device according to the present embodiment in a completed bonding state.
第 8図は第 7図の D— D ' 線で切つた断面図である 第 9図は本実施形態 1.の樹脂封止型半導体装置の製造方法のフロー チヤ一 卜である。 FIG. 8 is a cross-sectional view taken along the line DD ′ of FIG. FIG. 9 is a flowchart of the method for manufacturing the resin-encapsulated semiconductor device of the first embodiment.
第 1 0図は本発明の実施の形態 2の樹脂封止型半導体装置のリ一ド フ レームの概略構成を示す平面図である。  FIG. 10 is a plan view showing a schematic configuration of a lead frame of a resin-sealed semiconductor device according to a second embodiment of the present invention.
第 1 1図は第 1 0図の E— E ' 線で切った断面図である。  FIG. 11 is a cross-sectional view taken along line EE ′ of FIG.
第 1 2図は本発明の実施の形態 3の樹脂封止型半導体装置の主要部 の概略構成を示す平面図である。  FIG. 12 is a plan view showing a schematic configuration of a main part of a resin-sealed semiconductor device according to a third embodiment of the present invention.
第 1 3図は第 1 2図の F— F ' 線で切った断面図である。  FIG. 13 is a cross-sectional view taken along line FF ′ of FIG.
第 1 4図は本発明の実施の形態 3の変形例の主要部の概略構成を示 す断面図である。  FIG. 14 is a sectional view showing a schematic configuration of a main part of a modification of the third embodiment of the present invention.
第 1 5図は本発明の実施の形態 4の樹脂封止型半導体装置のリ一ド フ レームの概略構成を示す平面図である。  FIG. 15 is a plan view showing a schematic configuration of a lead frame of the resin-sealed semiconductor device according to the fourth embodiment of the present invention.
第 1 6図は第 1 5図の G— G ' 線で切った断面図である。  FIG. 16 is a sectional view taken along the line GG ′ of FIG.
第 1 7図は本発明の実施の形態 4の樹脂封止型半導体装置のヮィャ —ボンディ ング完了状態の全体の概略構成を示す平面図である。 第 1 8図は第 1 7図の H— H， 線で切った断面図である。 発明を実施するための最良の形態  FIG. 17 is a plan view showing an overall schematic configuration of a resin-bonded semiconductor device according to Embodiment 4 of the present invention in a bonding completed state. FIG. 18 is a cross-sectional view taken along line HH of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
(実施形態 1 )  (Embodiment 1)
第 .1図は本発明の実施の形態 1の樹脂封止型半導体装置の概略構成 を示す平面図であり、 第 2図は第 1図の A— A ' 線で切った断面図で ある。  FIG. 1 is a plan view showing a schematic configuration of a resin-sealed semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along line AA ′ of FIG.
第 1図及第 2図に示すように、 本実施形態 1 の樹脂封止型半導体装 置は、 平面形状が方形状に形成された半導体チップ 1の素子形成面 (表面） の一辺にほぼ平行に複数個の信号用の第 1パッ ド 1 Aと電源 用の複数個の第 2パッ ド 1 Bが設けられている。 前記半導体チップ 1 の素子形成面と反対側の面 （裏面） はヒ一トスプレッダ 2の上面に絶 縁性接着剤 3を介在させてペレッ ト付け材 （ぺ一スト） 4によって固 着されている。 As shown in FIGS. 1 and 2, the resin-encapsulated semiconductor device according to the first embodiment has an element forming surface of a semiconductor chip 1 having a square planar shape. A plurality of first pads 1A for signals and a plurality of second pads 1B for power supplies are provided substantially parallel to one side of the (surface). The surface (rear surface) of the semiconductor chip 1 opposite to the element forming surface is fixed to the upper surface of the heat spreader 2 by a pelleting material (paste) 4 with an insulating adhesive 3 interposed therebetween. .
前記信号用の第 1パッ ド 1 Aと電源用の複数個の第 2パッ ド 1 Bは 、 それぞれワイヤ一 5を介在して、 複数本のリード 6のそれぞれに電 気的に接続されている。 前記半導体チップ 1に複数個配列された第 1 ノ、。ッ ド 1 A及び第 2パッ ド 1 Bのうち、 複数個の第 1パッ ド 1 Aのそ れぞれに接続される複数本の信号用の第 1 リード 6 Aのそれぞれが、 前記第 1パッ ド 1 A及び第 2パッ ド 1 Bの配列方向と交差する第 1方 向に延在され、 かつ、 この第 1パッ ド 1 A及び第 2パッ ド 1 Bの配列 方向と同一の第 2方向に向って配列されている。  The signal first pad 1A and the power supply second pads 1B are electrically connected to the respective leads 6 via wires 15 respectively. . A first plurality arranged on the semiconductor chip 1; Out of the first pad 1A and the second pad 1B, each of the first leads 6A for a plurality of signals connected to each of the first pads 1A is the first lead 6A. The second pad extending in the first direction intersecting the arrangement direction of the pads 1A and the second pads 1B and being the same as the arrangement direction of the first pads 1A and the second pads 1B. It is arranged toward the direction.
前記複数個の第 1パッ ド 1 Aのそれぞれと複数本の第 1 リ―ド 6 A のそれぞれとがワイヤ一 5を介在して電気的に接続されている。 前記 複数個配列された第 1パッ ド 1 A及び第 2パッ ド 1 Bのうち、 複数個 の第 2パッ ド 1 Bのそれぞれに接続される片持ち吊り第 2 リード （電 源用リードバー） 6 Bが、 前記複数本の第 1 リード 6 Aと同一のリ一 ドフレームから形成され、 かつ、 複数個の第 2パツ ド 1 B と複数本の 第 1 リード 6 Aとの間に第 2方向に延在して配置される。  Each of the plurality of first pads 1A and each of the plurality of first leads 6A are electrically connected via a wire 15. Of the plurality of first pads 1A and second pads 1B arranged in a plurality, the cantilevered second leads (lead bars for power supply) connected to the plurality of second pads 1B, respectively. 6B is formed from the same lead frame as the plurality of first leads 6A, and a second lead is formed between the plurality of second pads 1B and the plurality of first leads 6A. It is arranged to extend in the direction.
そして、 前記第 1パッ ド 1 Aと第 1 リ―ド 6 Aとを接続するワイヤ — 5に比べて短いワイヤ一 5 A , 5 B を介在して、 前記片持ち吊り第 2 リード 6 Bに前記複数個の第 2パッ ド 1 Bのそれぞれが電気的に接 続されている。 前記半導体チップ 1、 第 1 リード 1 A、 及び片持ち吊 り第 2 リード 6 Bは絶緣性接着膜 （絶緣性接着剤塗布膜） 3 を介在し てヒ一トスプレッダ （放熱板） 2で支持されている。 そして、 前記半 導体チップ 1、 ヒ一トスプレッダ （放熱板） 2、 ボンディングワイヤ — 5， 5 A , 5 B、 リード 6 Aのインナ一リード部、 及び片持ち吊り 第 2 リ一ド 6 Bは封止樹脂 （モールドレジン） 7で封止されている。 前記片持ち吊り第 2 リード 6 Bは、 アースライン、 G N D用， 電源 用等の共通の目的で使用されるリードである。 本実施形態 1 において は、 片持ち吊り第 2 リード 6 Bの外側のリード 6 B 1は電源用リ一ド バーであり， 内側のリード 6 B 2は G N D用リ一ドバ一である。 すな わち、 片持ち吊り第 2 リード 6 Bは、 4本のリードで構成されている ことになる。 The cantilevered second lead 6B is connected to the first lead 1A and the first lead 6A via wires 5A and 5B, which are shorter than the wire 5 connecting the first pad 1A and the first lead 6A. Each of the plurality of second pads 1B is electrically connected. The semiconductor chip 1, the first lead 1A, and cantilever The second lead 6B is supported by a heat spreader (heat radiating plate) 2 with an insulating adhesive film (insulating adhesive coating film) 3 interposed therebetween. Then, the semiconductor chip 1, the heat spreader (heat radiating plate) 2, the bonding wires — 5, 5A, 5B, the inner lead portion of the lead 6A, and the cantilevered second lead 6B are sealed. Sealed with resin (mold resin) 7. The cantilevered second lead 6B is a lead used for a common purpose such as a ground line, a ground connection, and a power supply. In the first embodiment, the outer lead 6B1 of the cantilevered second lead 6B is a power lead bar, and the inner lead 6B2 is a GND lead bar. In other words, the cantilever second lead 6B is composed of four leads.
すなわち、 前記片持ち吊り第 2 リード 6 Bは、 第 3図及び第 4図に 示すように、 通常のリードフレームのコーナ部 （吊り部） でその一辺 が支持され、 他の二辺がそれぞれ半導体チップ 1の周辺に延在して素 子形成面から離間した （浮いた） Y字状のリード、 すなわち、 電源用 リ一ドバ一 6 B 1及び G N D用リ一ドバ一 6 B 2からなリ、 半導体チ ップ 1の一辺に対して二本の電源用リードバ ·一 6 B 1及ぴ G N D用リ —ドバ一 6 B 2を形成する構造となっている。 そして、 それぞれ 4本 の片持ち吊り第 2 リード 6 Bがリードフレームのコ一ナ部に片持ち吊 リ構造で設けられている。 また、 前記信号用の第 .1 リード 6 A及ぴ片 持ち吊り第 2 リ一ド 6 Bは、 例えば、 それぞれ厚さ 0 . 1 5 m mの C u合金からなっている。  That is, as shown in FIGS. 3 and 4, one side of the cantilevered second lead 6B is supported by a corner portion (hanging portion) of a normal lead frame, and the other two sides are semiconductors. A Y-shaped lead extending around the chip 1 and separated (floating) from the element forming surface, that is, a lead from the power supply lead 6B1 and a ground lead 6B2. The semiconductor chip 1 has a structure in which two power supply lead bars 16 B 1 and a GND lead 6 B 2 are formed on one side of the semiconductor chip 1. Each of the four cantilevered second leads 6B is provided at a corner of the lead frame in a cantilevered structure. The signal first lead 6A and the cantilevered second lead 6B are made of, for example, a Cu alloy having a thickness of 0.15 mm.
前記片持ち吊り第 2 リ一ド 6 Bの吊リ部を太く し、 リ一ドバ一部を 二本に分けて細く してあるのは、 吊 り部は強度を増大させ、 リ一ドバ —部は熱応力の影響を緩和させるためである。 また、 リードバ一部の 平面形状を屈曲形にしてあるのは、 チップのコーナ一部に配置される パッ ドと、 チップの各辺の中央付近に配置されるパッ ドのそれぞれと. 前記リ一ドバ一部との距離を一定にして、 ワイヤ一ボンディ ング時の ワイヤ一の長さをできるだけ一定にするためである。 The reason why the hanging portion of the cantilevered second lead 6B is made thicker and a portion of the lead bar is divided into two portions and made thinner is that the hanging portion increases the strength, The-part is for reducing the influence of thermal stress. The bent shape of the part of the lead bar is the pad arranged at a part of the corner of the chip and the pad arranged near the center of each side of the chip. This is to keep the distance to the part of the dove constant and to keep the length of the wire when bonding the wire as constant as possible.
前記ヒ一トスプレッダ 2は、 例えば、 厚さ 0 . 1 5 m mの電解銅箔 からなつている。 前記絶緣性接着膜 3は、 例えば、 厚さ 0 . 0 2 rn m の熱可塑性樹脂 （例えば、 熱可塑性ポリイ ミ ド系樹脂、 熱可塑性ェポ キシ系樹脂を用いる） 又は熱硬化性樹脂 （例えば、 熱硬化性ポリイミ ド系樹脂を用いる） からなつている。  The heat spreader 2 is made of, for example, an electrolytic copper foil having a thickness of 0.15 mm. The insulating adhesive film 3 is made of, for example, a thermoplastic resin having a thickness of 0.02 rn m (for example, using a thermoplastic polyimide resin or a thermoplastic epoxy resin) or a thermosetting resin (for example, And thermosetting polyimide resin).
また、 前記ぺレッ ト付け材 4は、 例えば、 厚さ 0 . 0 1〜 0 . 0 5 m mの A gフイラ入りのェポキシ系接着材からなっている。 半導体チッ プ 1の厚さは、 直径約 0 . 4 m mであるボンディ ングワイヤーと して は例えば A u線を用い、 封止樹脂 7と してはモールドレジンを用いる : 次に、 本実施形態 1の樹脂封止型半導体装置の製造方法について説 明する。 The pellet attaching material 4 is made of, for example, an epoxy adhesive containing an Ag filler having a thickness of 0.01 to 0.05 mm. The thickness of the semiconductor chip 1 is about 0 4 and Bondi ring wire in mm using the example A u line diameter, in the sealing resin 7 using the mold resin:. Next, the present embodiment The method of manufacturing the resin-encapsulated semiconductor device 1 will be described.
第 4図〜第 9図は本実施形態 1の樹脂封止型半導体装置の製造方法 を説明するための図であり、 第 9図は本実施形態 1の樹脂封止型半導 体装置の製造方法の工程フローチヤ トである。  4 to 9 are views for explaining a method of manufacturing the resin-encapsulated semiconductor device according to the first embodiment. FIG. 9 is a diagram illustrating the manufacturing of the resin-encapsulated semiconductor device according to the first embodiment. It is a process flow chart of the method.
本実施形態 1の樹脂封止型半導体装置の製造方法は、 第 9図に示す ように、 まず最初に、 0 . 1 5 m m厚の C Li材からエッチング又はス タンピングにより、 第 3図に示すようなパターンのリードフレームを 作製する （ステップ 1 0 1 ) 。 そして、 第 1 リード 6 Aのボンディ ン グされる先端及び片持ち吊り第 2 リード 6 Bの一部に A gめっきを行 い （ステップ 1 0 2 ) 、 第 4図に示すように、 熱可塑性樹脂又は熱硬 化性樹脂のポリイ ミ ド樹脂 （絶縁性接着膜 3 ) を塗布した C u箔から なるヒ一トスプレッダ 2を熱圧着により接合する （ステップ 1 0 3 ) 次に、 このヒ一トスプレッダ付きリードフレームのヒ一トスプレツ ダ 2の部分にエポキシ系のペレッ ト付け材 4 を用いて、 第 5図及び第 6図に示すように、 半導体チップ （ペレッ ト） 1 を接着する （ステツ プ 1 0 4 ) 。 その後、 第 7図及び第 8図に示すように、 A uワイヤ一 ボンディ ングにより半導体チップ 1 と第 1 リード 6 Aのインナ一リ ド 及び片持ち吊り第 2 リード 6 Bの各リ一ドバ一 6 B 1， 6 B 2とを電 気的に接続し、 前記各リ一ドバ一 6 B 1， 6 B 2と第 1 リード 6 Aの インナ一リードとを電気的に接続する （ステップ 1 0 5 ) 。 As shown in FIG. 9, the manufacturing method of the resin-encapsulated semiconductor device of the first embodiment is as shown in FIG. 3 by first etching or stamping a 0.15 mm thick CLi material. A lead frame having such a pattern is manufactured (step 101). Then, Ag plating is applied to the bonded end of the first lead 6A and a part of the cantilevered second lead 6B. (Step 102) As shown in FIG. 4, a heat spreader 2 made of a Cu foil coated with a thermoplastic resin or a polyimide resin of a thermosetting resin (insulating adhesive film 3) is used. Bonding by thermocompression bonding (Step 103) Next, using an epoxy-based pelletizing material 4 for the part of the heat spreader 2 of the lead frame with a heat spreader, as shown in FIGS. As shown, the semiconductor chip (pellet) 1 is bonded (step 104). Then, as shown in FIGS. 7 and 8, each of the lead wires of the semiconductor chip 1 and the inner lead of the first lead 6A and the cantilevered second lead 6B is bonded by Au wire bonding. 6 B 1 and 6 B 2 are electrically connected, and the respective lead bars 6 B 1 and 6 B 2 are electrically connected to the inner lead of the first lead 6 A (step 10). Five ) .
次に、 前記半導体チップ 1、 ヒ一トスプレッダ 2、 ボンディングヮ ィャ一 5， 5 A， 5 B、 第 1 リ一ド 6 Aのインナ一リード部、 及び片 持ち吊り第 2 リード 6 B を封止樹脂 7で封止する （ステップ 1 0 6 ) その後、 第 1 リード 6 Aのァタ一リ一ド部及ぴ片持ち吊り第 2 リ一 ド 6 Bのァタ一リード部に A gめっきを施こし （ステップ 1 0 7 ) 、 リードフレームを切断して成形し、 樹脂封止型半導体装置を完成する (ステップ 1 0 8 ) 。  Next, the semiconductor chip 1, the heat spreader 2, the bonding wires 5, 5A, 5B, the inner lead portion of the first lead 6A, and the cantilever second lead 6B are sealed. Seal with resin 7 (Step 106) Then, apply Ag plating to the lead portion of the first lead 6A and the lead portion of the cantilevered second lead 6B. The application (Step 107), the lead frame is cut and molded to complete a resin-sealed semiconductor device (Step 108).
前記製造工程において、 吊リ リードを用いて片持ち吊り第 2 リ一ド 6 Bを形成することによ り、 片持ち構造の吊リ第 2 リ一ド 6 B (電源 甩リ一ドバー又は G X D用リードバ一） であつても、 ヒ一卜スプレッ ダ 2によ リ固定されるため、 歩留の良い半導体装置を得ることができ By forming the cantilevered second lead 6B using the hanging lead in the above manufacturing process, the cantilevered second lead 6B (power supply lead bar or GXD Even if the lead bar is used, the semiconductor device with a high yield can be obtained because it is fixed by the heat spreader 2.
-Q 。 -Q.
また、 片持ち吊り第 2 リ一ド 6 B (電源用リ一ドバ一又は G N D用 リ一ドバ—） が第 1 リード 6 Aのインナ一リ一ドと接続されていない ため、 半導体チップ 1 内の任意の位置の電源端子又は G N D端子と接 続することができ、 また、 任意の位置のインナ一リードと接続するこ とができる。 これによ り、 半導体チップ内の電源電圧の安定化をはか ることができ、 電気的特性の良い半導体装置を得ることができる。 本実施形態 1の構造では、 片持ち吊り第 2 リード 6 B (電源用リー ドバー又は G N D用リードバ一） をヒ一トスプレッダにより固定する 構造であるため、 片持ち吊 り第 2 リード 6 Bが片持ち構造であっても， 半導体製造工程で片持ち吊り第 2 リード 6 B (電源用リ一ドバ一又は G N D用リードバ一） の変形が起こらない。 このため、 例えば、 電源 用リ—ドバ一又は G N D用リ一ドバ一の設計の自由度を得ることがで きる。 また、 第 1 リード 6 Aのインナ一リードと接続されていないた め、 複数電位の電源用リ一ドバ一を形成することができる。 In addition, cantilevered second lead 6B (power supply lead or GND) Since the lead bar is not connected to the inner lead of the first lead 6A, it can be connected to the power supply terminal or the GND terminal at any position in the semiconductor chip 1, and Can be connected to the inner lead at the position. As a result, the power supply voltage in the semiconductor chip can be stabilized, and a semiconductor device with good electrical characteristics can be obtained. In the structure of the first embodiment, since the cantilevered second lead 6B (lead bar for power supply or lead bar for GND) is fixed by a heat spreader, the cantilevered second lead 6B is one-sided. Even with a holding structure, no deformation of the cantilevered second lead 6B (power supply lead bar or GND lead bar) occurs in the semiconductor manufacturing process. For this reason, for example, the degree of freedom in designing the power supply lead bar or the GND lead bar can be obtained. Further, since it is not connected to the inner lead of the first lead 6A, it is possible to form a power supply lead bar having a plurality of potentials.
(実施形態 2 )  (Embodiment 2)
第 1 0図は本発明の実施の形態 2の樹脂封止型半導体装置のリ一ド フ レームの概略構成を示す平面図であり、 第 1 1図は第 1 0図の E— E ' 線で切つた断面図である。  FIG. 10 is a plan view showing a schematic configuration of a lead frame of the resin-encapsulated semiconductor device according to the second embodiment of the present invention. FIG. 11 is a line E--E 'of FIG. It is sectional drawing cut | disconnected by.
本実施形態 2の樹脂封止型半導体装置は、 前記実施形態 1 の第 3図 及び第 4図に示す形状構造の片持ち吊リ第 2 リ一ド 6 B (電源用リー ドバ一又は G N D用リードバ一） を、 第丄 0図及び第 1 1図に示す形 状構造にしたものである。 すなわち、 通常のリードフ レームのコーナ 部でその一辺が支持され、 他の二辺がそれぞれ半導体チップ 1の周辺 の中央部ま'で延在して回路素子形成面から離間した （浮いた） Y字伏 のリ一ドからなり、 半導体チップ 1の一辺に対して二本のリ一ドバ一 6 B 3 , 6 B 4により中央部が切れた一本のリードバーを形成する構 造の片持ち吊り第 2 リード 6 B ' にしたものである。 The resin-encapsulated semiconductor device of the second embodiment includes a cantilevered second lead 6B (lead for power supply or GND) having the shape and structure shown in FIGS. 3 and 4 of the first embodiment. The lead bar) has the shape shown in FIGS. 10 and 11. That is, one side is supported at the corner of the normal lead frame, and the other two sides extend to the central part around the periphery of the semiconductor chip 1 and are separated (floated) from the circuit element forming surface. Two leads on one side of the semiconductor chip 1. This is a cantilevered second lead 6 B ′ having a structure in which one lead bar whose center is cut off by 6 B 3 and 6 B 4 is formed.
このように、 リードバーを中央部で切ってリードバ一 6 B 3， 6 B 4の間にスリツ トを設けるのは、 熱応力を緩和するためであり、 また、 使用、 適用範囲を拡大するためのものである。  The reason why the lead bar is cut at the center and the slit is provided between the lead bars 6B3 and 6B4 is to relieve thermal stress and to expand the use and application range. belongs to.
本実施形態 2の片持ち吊り第 2 リード 6 B， は、 一本のリードバ一 の簡単な形状構造で前記実施形態 1の片持ち吊り第 2 リード 6 Bと同 等の機能をもたせることができる。 すなわち、 本発明の片持ち吊リ第 2 リ一ドは、 吊リ リードを利用して電源用リ一ドバ一又は G N D用リ —ドバ一とするリード構造であれば、 前記実施形態 1， 2以外の片持 ち吊り リード構造であってもよい。  The cantilevered second lead 6B of the second embodiment can have the same function as the cantilevered second lead 6B of the first embodiment with a simple shape of one lead bar. . That is, the second lead of the cantilever suspension of the present invention has a lead structure in which a suspension lead is used as a power supply lead or a GND lead. Other types of cantilever hanging lead structures may be used.
(実施形態 3 )  (Embodiment 3)
第 1 2図は本発明の実施の形態 3の樹脂封止型半導体装置の主要部 の概略構成を示す平面図であり、 第 1 3図は第 1 2図の F— F ' 線で 切った断面図である。  FIG. 12 is a plan view showing a schematic configuration of a main part of a resin-encapsulated semiconductor device according to a third embodiment of the present invention. FIG. 13 is a sectional view taken along line FF ′ of FIG. It is sectional drawing.
本実施形態 3の樹脂封止型半導体装置は、 前記実施形態 2の第 1 0 図及び第 1 1図に示す形状構造の片持ち吊り第 2 リード （電源用リ一 ドバ一又は G N D用リードバ一） 6 B ' の二本のリードバ一 6 B 3， 6 B 4にそれぞれスリ ッ ト 6 S を設け、 その外側に A gめっき 6 Mを 施したものである。  The resin-encapsulated semiconductor device according to the third embodiment includes a cantilevered second lead (lead for power supply or lead bar for GND) having the shape and structure shown in FIGS. 10 and 11 of the second embodiment. ) The slit 6S is provided on each of the two lead bars 6B3 and 6B4 of 6B ', and the outside thereof is plated with Ag 6M.
前記スリツ 卜 6 Sは、 半導体チップ 1 をぺレッ ト付け材 （ペースト） 4 を用い、 ヒ一トスプレツダ 2に接着する時に、 前記ぺレッ 卜付け材 (ぺ一スト） 4が前記 A gめつき 6 Mの領域にはみ出してボンディ ン グ領域を汚染しないように設けられ、 片持ち吊 り第 2 リード （電源用 リ一ドバ一又は G N D用リードバ一） 6 B ' へのワイヤ一ボンディ ン グの信頼性を確保するために設けたものである。 When the semiconductor chip 1 is adhered to the heat spreader 2 using the pelleting material (paste) 4, the slit 6 S is coated with the Ag in the slit 6 S. It is provided so as not to protrude into the 6 M area and contaminate the bonding area. The cantilevered second lead (for power supply) Lead bar or GND lead bar) This is provided to ensure the reliability of wire bonding to 6B '.
片持ち吊り第 2 リ一ド 6 B ' へボンディ ングするため、 A gめっき を行うが、 片持ち吊り第 2 リード 6 B ' 全体に A gめっきを行う と、 半導体装置を基板実装する時の熱により、 A gめっき面とレジンとの 接着が一般に C u基材面と封止樹脂 （モールドレジン） との接着より も弱いため、 片持ち吊り第 2 リード 6 B ' と封止樹脂 （モールドレジ ン） が剥離する。 この剥離によ り、 片持ち吊り第 2 リード 6 B ' に接 合したボンディングワイヤ一 （ A u ワイヤ一） が切断されるおそれが あるので、 本実施形態 3のように、 二本のリードバー 6 B 3， 6 B 4 にそれぞれスリ ッ ト 6 Sを設けた部分の外側のみに A gめっきを施こ すことによつて片持ち吊り第 2 リード 6 B ' に接合したボンディ ング ワイヤ一 （ A uワイヤ一） が切断されないようにしてある  Ag plating is performed to bond to the cantilevered second lead 6B ', but if Ag plating is applied to the entire cantilevered second lead 6B', the semiconductor device can be mounted on a substrate. Due to the heat, the adhesion between the Ag plating surface and the resin is generally weaker than the adhesion between the Cu substrate surface and the sealing resin (mold resin). Therefore, the cantilevered second lead 6B 'and the sealing resin (mold resin) (Resin) peels off. This peeling may break the bonding wire (Au wire) connected to the cantilevered second lead 6B '. Therefore, as in the third embodiment, two lead bars are used. Ag plating is applied only to the outside of the portion where the slit 6S is provided on each of 6B3 and 6B4, so that the bonding wire joined to the cantilevered second lead 6B 'can be used. Au wire is not cut
なお、 前記スリ ッ ト 6 Sの代りに、 ヒー トスプレッダ 2 を接着する 時に、 前記ペレッ ト付け材 （ペースト） 4が前記片持ち吊り第 2 リ一 ド （電源用リードバ一又は G N D用リードバ一） 6 B， のワイヤ一ボ ンディンされる部分及びボンディ ングワイヤ一 （A u ワイヤ一） を汚 染しないように第 1 4図に示すように、 段差 6 Dを設けて、 ボンディ ングワイヤ一 （ A u ワイヤ一） のボンディ ング性を確保するようにし てもよい。 前記段差 6 Dは、 例えば、 プレス加工によって形成するこ とができる。  When the heat spreader 2 is bonded instead of the slit 6S, the pellet attachment material (paste) 4 is attached to the cantilevered second lead (lead bar for power supply or lead bar for GND). As shown in Fig. 14, a step 6D is provided so as not to contaminate the part to be bonded and the bonding wire (Au wire 1) of 6B, and the bonding wire (Au wire). 1) Bonding property may be ensured. The step 6D can be formed by, for example, press working.
(実施形態 4 )  (Embodiment 4)
第 1 5図は本発明の実施の形態 4の樹脂封止型半導体装置のリ一ド フ レームの概略構成を示す平面図であり、 第 1 6図は第 1 5図の G— G ' 線で切った靳面図である。 FIG. 15 is a plan view showing a schematic configuration of a lead frame of the resin-encapsulated semiconductor device according to the fourth embodiment of the present invention, and FIG. FIG. 3 is a plan view cut along a G ′ line.
本実施形態 4の樹脂封止型半導体装置は、 前記実施形態 2の第 1 0 図及び第 1 1図に示す形状構造の片持ち吊り第 2 リード （電源用リ一 ドバ一又は G N D用リードバ一） 6 B， の二本のリ一ドバ一 6 B 3， 6 B 4のワイヤ一ボンディ ングに必要な部分のみに、 第 1 5図及び第 1 6図に示すように、 A gめっきを施したものである。  The resin-encapsulated semiconductor device of the fourth embodiment includes a cantilevered second lead (power supply lead bar or GND lead bar) having the shape and structure shown in FIGS. 10 and 11 of the second embodiment. Ag plating is applied only to the parts necessary for bonding the wires of the two leads 6B3 and 6B4, as shown in Figs. 15 and 16. It was done.
このように二本のリ一ドバー 6 B 3 , 6 B 4のワイヤ一ボンディン グに必要な部分のみに A gめっきを施こすことにより、 ヒ一トスプレ ッダ 2を接着する時に、 前記ペレッ ト付け材 （ペースト） 4が前記片 持ち吊り第 2 リード （電源用リードバー又は G N D用リードバ一） 6 E ' のワイヤ一ボンディ ンされる部分及ぴボンデイングワイヤー （ A u ワイヤ一） を汚染しないようにして、 第 1 7図及び第 1 8図に示す ように、 ボンディ ングワイヤ一 （ A uワイヤ一） のボンディング性を 確保するとともに、 片持ち吊り第 2 リ―ド 6 B ' と封止樹脂 （モール ドレジン） との接着性を向上することができる,， これにより、 半導体 装置の基板実装時においても、 片持ち吊 り第 2 リード 6 B ' と封止樹 脂 （モールドレジン） の剥離を起りにく く、 信頼性の高いパッケージ を得ることができる。  By applying Ag plating only to the portions necessary for bonding the wires of the two lead bars 6B3 and 6B4 in this manner, when the heat spreader 2 is bonded, the pellet is formed. Attachment material (paste) 4 does not contaminate the cantilevered second lead (power supply lead bar or GND lead bar) 6 E 'wire-bonded part and bonding wire (Au wire) Then, as shown in FIGS. 17 and 18, the bonding property of the bonding wire (Au wire) is ensured, and the cantilevered second lead 6B 'and the sealing resin ( This can improve the adhesiveness with the mold resin), and this can cause the cantilevered second lead 6B 'and the sealing resin (mold resin) to peel off even when the semiconductor device is mounted on the substrate. Anyway, trust It is possible to obtain a high package.
本実施形態 4の半導体装置の製法を簡単に説明すると、 第 1 5図及 び第 1 6図に示すように、 二本のリ―ドバ一 6 B 3， 6 B 4のワイヤ —ボンディ ングに必要な部分のみに A gめつきを施こ した後、 半導体 チップ 1 をペレッ ト付け材 （ぺ一スト） 4 を用いて、 ヒ一トスプレッ ダ 2を接着する。 そして、 第 1 7図及び第：！ 8図に示すように、 片持 ち吊り第 2 リード (電源用リ—ドバ一又は G X D用リ一ドバー) 6 B と半導体チップ 1. とをボンディ ングワイヤ一 （ A u ワイヤ一） を介在 させて接続する。 その後、 前記実施形態 1 と同様に、 樹脂で封止する, 以上の本実施形態 1〜4の説明からわかるように、 本発明のうち代 表的なものによって得られる効果は、 以下のとおりである。 The manufacturing method of the semiconductor device according to the fourth embodiment will be briefly described. As shown in FIGS. 15 and 16, two lead bars 6B3 and 6B4 are used for bonding. After applying Ag plating only to the necessary parts, the semiconductor chip 1 is glued to the heat spreader 2 using a pelleting material (past) 4. And Fig. 17 and No.:! 8 As shown in Figure 8, cantilever suspended second lead (lead bar for power supply or lead bar for GXD) 6 B And the semiconductor chip 1. are connected via a bonding wire (Au wire). After that, similarly to the first embodiment, sealing is performed with a resin. As can be seen from the above description of the first to fourth embodiments, the effects obtained by typical ones of the present invention are as follows. is there.
( 1 ) 電源電圧供給用の共通リードを片持ち （リードフレームの状 態で、 一端側が自由な状態） 構造にしたので、 共通リードの変形を低 減することができるので、 電気的信頼性が高く、 かつ、 信号の入出力 ピンが多ピンの半導体装置を提供できる。  (1) Since the common lead for supplying the power supply voltage is cantilevered (one end is free in a lead frame state), the deformation of the common lead can be reduced, and the electrical reliability is reduced. It is possible to provide a semiconductor device which is expensive and has a large number of signal input / output pins.
( 2 ) 電源電圧供給用の共通リ一ドの幅を信号リ一ド幅より広く し たので、 電源、 G N D等共通の電圧供給経路のインダクタンスを低減 できるので、 ノイズマ一ジンを大きくすることができる。  (2) The width of the common lead for supplying the power supply voltage is wider than the signal lead width, so that the inductance of the common voltage supply path such as the power supply and GND can be reduced, so that the noise margin can be increased. it can.
( 3 ) 電源電圧供給用の共通リ一ドの固定部を信号リ一ドの無いコ —ナ一部に配置したので、 電源、 G N D等共通のアウターリードの配 設位置を自由に配設することができる。  (3) The fixed part of the common lead for supplying power supply voltage is located at a part of the corner where there is no signal lead, so the position of the common outer lead such as power supply and GND can be freely arranged. be able to.
( 4 ) 片持ち吊り リード構造を採用し、 かつ、 ヒ一トスプレダ （放 熱板） を内蔵させることにより、 電気的信頼性が高く、 信号の入出力 ピンを多ピンにできるとともに、 放熱効率を向上できる。  (4) The use of a cantilevered lead structure and a built-in heat spreader (heat-dissipating plate) ensures high electrical reliability, allows a large number of signal input / output pins, and improves heat dissipation efficiency. Can be improved.
以上、 本発明を前記実施形態に基づいて具体的に説明したが、 本発 明は、 前記実施形態に限定されるものではなく .. その要旨を逸脱しな い範囲において種々変更し得ることはいうまでもない。 産業上の利用可能性  As described above, the present invention has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments. Various changes can be made without departing from the gist of the present invention. Needless to say. Industrial applicability
半導体集積回路における同一の用途に用いられる外部接続端子の数 を削減し、 信号の入出力ピンが多ピンにできるとともに. 電源、 G λ' P T JP97 0 δ o 17 The number of external connection terminals used for the same purpose in a semiconductor integrated circuit can be reduced, and the number of signal input / output pins can be increased. Power supply, G λ ' PT JP97 0 δ o 17
D等共通の電流経路の抵抗を低減できる半導体装置において、 電源、 G N D等共通のアウターリードの配設位置を自由に配設することがで きる。 In a semiconductor device capable of reducing the resistance of a common current path such as D, the arrangement position of a common outer lead such as a power supply and GND can be freely arranged.
また、 半導体集積回路における同一の用途に用いられる外部接続端 子の数を削減し、 信号の入出力ピンが多ピンにできるとともに、 電源 、 G N D等共通の電流経路の抵抗を低減できる半導体装置の製造時間 を低減することができる。  In addition, the number of external connection terminals used for the same purpose in a semiconductor integrated circuit can be reduced, the number of signal input / output pins can be increased, and the resistance of a common current path such as power supply and GND can be reduced. Manufacturing time can be reduced.
また、 半導体集積回路における同一の用途に用いられる外部接続端 子の数を削減し、 信号の入出力ピンを多ピンにできるとともに、 電源0 、 G N D等共通の電流経路の抵抗を低減でき、 かつ、 放熱効率を向上 できる。  In addition, the number of external connection terminals used for the same purpose in a semiconductor integrated circuit can be reduced, the number of signal input / output pins can be increased, and the resistance of a common current path such as power supply 0 and GND can be reduced. The heat radiation efficiency can be improved.

Claims

請 求 の 範 囲 The scope of the claims
1 - 平面形状が方形状に形成された半導体チップの素子形成面の一 辺にほぼ平行に配列された複数個の第 1パッ ド （外部端子） 及び第 2 パッ ド （外部端子） のそれぞれに、 ワイヤ一を介在して、 複数本のリ ―ドのそれぞれが電気的に接続された半導体装置であって、 前記複数 個の第 1パッ ドのそれぞれに接続される複数本の第 1 リ一ドのそれぞ れが、 前記第 1パッ ド及び第 2パッ ドの配列方向と交差する第 1方向 に延在され、 かつ、 この第 1パッ ド及び第 2パッ ドの配列方向と同一 の第 2方向に向って配列され、 前記複数個の第 1パッ ドのそれぞれと 複数本の第 1 リ一ドのそれぞれとがワイャ一を介在して電気的に接続 され、 前記複数個の第 2パッ ドのそれぞれに接続される片持ち吊リ第 2 リードが、 複数個の第 2パッ ドと複数本の第 1 リ一ドとの間に第 2 方向に延在して配置され、 かつ、 前記複数本の第 1 リードと第 2 リ一 ドは同一のリードフレームからなり、 前記片持ち吊リ第 2 リ一ドに前 記複数個の第 2パッ ドのそれぞれが電気的に接続され、 前記半導体チ ップ、 第 1 リード、 及び片持ち吊リ第 2 リードは絶縁性接着膜を介在 して放熱板で支持されていることを特徴とする半導体装置 1-Each of a plurality of first pads (external terminals) and second pads (external terminals) arranged approximately parallel to one side of the element forming surface of a semiconductor chip having a square planar shape A semiconductor device in which each of a plurality of leads is electrically connected via a wire, wherein a plurality of first leads connected to each of the plurality of first pads are provided. Each of the pads extends in a first direction that intersects the arrangement direction of the first and second pads, and is the same as the arrangement direction of the first and second pads. Are arranged in two directions, each of the plurality of first pads and each of the plurality of first leads are electrically connected via a wire, and the plurality of second pads are Second leads connected to each of the multiple pads and multiple second pads A plurality of the first leads and the second leads are formed of the same lead frame, and the first leads and the second leads are formed of the same lead frame. Each of the plurality of second pads is electrically connected to the lead, and the semiconductor chip, the first lead, and the cantilevered second lead are interposed with an insulating adhesive film. Semiconductor device characterized by being supported by a heat sink
2 . 前記片持ち吊リ第 2 リ一ドは共通の目的で使用されるリ一ドで あることを特徴とする請求の範囲 1 に記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the cantilevered second lead is a lead used for a common purpose.
3 . 前記片持ち吊り第 2 リードには、 前記絶縁性接着膜の上に半導 体チップをペレツ ト付けするためのペレツ ト付け接着剤の流れを止め る接着剤流れ止め手段が当該片持ち吊り第 2 リード上のバッ ドの配設 位置よ リ半導体チップ側の位置に設けられていることを特徴とする請 求の範囲 1又は 2に記載の半導体装置。 3. The cantilever hanging second lead is provided with an adhesive flow stopping means for stopping a flow of a pelleting adhesive for pelletizing a semiconductor chip on the insulating adhesive film. The battery is provided at a position closer to the semiconductor chip than the position of the pad on the second suspension lead. 3. The semiconductor device according to claim 1 or 2.
4 . 前記接着剤流れ止め手段は、 スリ ッ トからなる こ とを特徴とす る請求の範囲 3に記載の半導体装置。  4. The semiconductor device according to claim 3, wherein the adhesive flow stopping means is formed of a slit.
5 . 前記接着剤流れ止め手段は、 段差からなることを特徴とする請 求の範囲 3に記載の半導体装置。  5. The semiconductor device according to claim 3, wherein said adhesive flow stopping means comprises a step.
6 . 平面形状が方形状に形成された半導体チップの素子形成面の一 辺にほぼ平行に配列された複数個の第 1パッ ド及び複数個の第 2パッ ドのそれぞれに、 ワイヤ一を介在して、 複数本のリードのそれぞれが 電気的に接続される半導体装置の製造方法であって、 前記複数個の第 1パッ ドのそれぞれに接続される複数本の第 1 リードのそれぞれを、 前記第 1パッ ド及び第 2パッ ドの配列方向と交差する第 1方向に延在 させ、 かつ、 この第 1パッ ド及び第 2パッ ドの配列方向と同一の第 2 方向に向けて配列させ、 前記複数個の第 2パッ ドのそれぞれに接続さ れる片持ち吊り第 2 リードを、 複数個の第 2パッ ドと複数本の第 1 リ —ドとの間に第 2方向に延在して配置させたパタ一ン （形状） のリ一 ド リ一 ドフ レームを形成し、 その リードフ レームの所定部分を銀めつ きした後、 放熱板の所定位置に前記半導体チップを絶縁性接着膜を介 在してペレ ツ ト付け接着剤で固定し、 前記第 1パッ ド及び第 2パッ ド と、 前記第 1 リード及び第 2 リ一ドのィンナ―'リ一ドとを、 ヮィャ一' ボンディ ングによ り電気的に接続し、 前記第 2 リードとワイヤ一ボン ディ ングによ り電源もしくは G Dを外部へ取り出すリ一ド用ィン十 —リードとを電気的に接続して、 樹脂で封止することを特徴とする半 導体装置の製造方法。  6. A wire is interposed between each of a plurality of first pads and a plurality of second pads arranged substantially parallel to one side of an element forming surface of a semiconductor chip having a square planar shape. A method of manufacturing a semiconductor device in which each of a plurality of leads is electrically connected, wherein each of the plurality of first leads connected to each of the plurality of first pads is: Extending in a first direction intersecting the arrangement direction of the first pad and the second pad, and being arranged in the same second direction as the arrangement direction of the first pad and the second pad; A cantilevered second lead connected to each of the plurality of second pads is extended in a second direction between the plurality of second pads and the plurality of first leads. A lead frame of the arranged pattern (shape) is formed and its lead After the predetermined portion of the frame is silvered, the semiconductor chip is fixed to a predetermined position of the heat sink with a pelleting adhesive via an insulating adhesive film, and the first and second pads are fixed. The lead is electrically connected to the inner lead of the first lead and the second lead by a wire bonding, and the second lead is connected to the inner lead of the second lead by a wire bonding. A method for manufacturing a semiconductor device, comprising: electrically connecting a lead or a lead for taking out a power supply or a GD to the outside; and sealing with a resin.
PCT/JP1997/000058 1997-01-14 1997-01-14 Semiconductor device and method for manufacturing the same WO1998031051A1 (en)

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JP2008283213A (en) * 2008-07-18 2008-11-20 Panasonic Corp Semiconductor device and manufacturing method of semiconductor device
JP2009032899A (en) * 2007-07-27 2009-02-12 Renesas Technology Corp Semiconductor device
JP2009212211A (en) * 2008-03-03 2009-09-17 Rohm Co Ltd Semiconductor device

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JPH0837264A (en) * 1994-07-25 1996-02-06 Mitsui High Tec Inc Manufacture of lead frame
JPH0837276A (en) * 1994-07-25 1996-02-06 Mitsui High Tec Inc Manufacture of semiconductor device composite lead frame
JPH0870090A (en) * 1994-08-30 1996-03-12 Kawasaki Steel Corp Semiconductor integrated circuit
JPH08279584A (en) * 1995-04-07 1996-10-22 Matsushita Electric Ind Co Ltd Lead frame and semiconductor device

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JPH04223364A (en) * 1990-12-25 1992-08-13 Mitsubishi Electric Corp Semiconductor device
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JP2009032899A (en) * 2007-07-27 2009-02-12 Renesas Technology Corp Semiconductor device
JP2009212211A (en) * 2008-03-03 2009-09-17 Rohm Co Ltd Semiconductor device
JP2008283213A (en) * 2008-07-18 2008-11-20 Panasonic Corp Semiconductor device and manufacturing method of semiconductor device
JP4695672B2 (en) * 2008-07-18 2011-06-08 パナソニック株式会社 Semiconductor device

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