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WO1996028825A1 - Memoire a semi-conducteur - Google Patents

Memoire a semi-conducteur Download PDF

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Publication number
WO1996028825A1
WO1996028825A1 PCT/JP1995/000433 JP9500433W WO9628825A1 WO 1996028825 A1 WO1996028825 A1 WO 1996028825A1 JP 9500433 W JP9500433 W JP 9500433W WO 9628825 A1 WO9628825 A1 WO 9628825A1
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WO
WIPO (PCT)
Prior art keywords
refresh
block
blocks
semiconductor memory
memory
Prior art date
Application number
PCT/JP1995/000433
Other languages
English (en)
Japanese (ja)
Inventor
Kan Takeuchi
Yoshinobu Nakagome
Kazuhiko Kajigaya
Hiroshi Kawamoto
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/000433 priority Critical patent/WO1996028825A1/fr
Publication of WO1996028825A1 publication Critical patent/WO1996028825A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Definitions

  • the present invention relates to a semiconductor memory that consumes a small amount of current during standby, and more particularly to a semiconductor memory that has been subjected to a refresh control capable of minimizing a refresh operation.
  • FIG. 16 shows a method of controlling a refresh operation during standby in a conventional DRAM.
  • a refresh clock is supplied to the self-refresh control circuit at regular intervals. Clocks can be provided externally or automatically generated internally. You. When the clock is applied, the refresh operation is sequentially performed on all the memory cells.
  • the cycle of the clock is set within a range where the information stored in the memory cell is not lost due to the leak current.
  • the clock cycle is given by specifications.
  • a clock is generated internally, a fixed period is generated using, for example, a ring oscillator.
  • Japanese Patent Application Laid-Open No. S64-32489 discloses a semiconductor memory in which the refresh cycle is controlled by error detection of an error correction circuit to reduce power consumption. Disclosure of the invention
  • the conventional DRAM has a problem that the information retention time of the battery is only a few weeks.
  • the interval between refresh operations must be determined according to the memory cell with the largest leak current.
  • the leakage current of a memory cell varies widely within a chip, the refresh interval must be set with a large margin for the average leakage current. Reducing the margin here creates another problem: a large number of defective chips and an increase in bit cost. For these reasons, it has been difficult to reduce the refresh interval beyond the current level and further reduce the current consumption during standby.
  • the integration of DRAM increases, the number of cases where all memory cells in a chip are used decreases. In such a case, it is useless to perform the refresh operation on the unused memory cells. This unnecessary increase in current consumption is particularly important with higher integration of DRAM. Attention was not paid to becoming noticeable.
  • An object of the present invention is to provide a method capable of minimizing a current consumption required for a refresh operation for a semiconductor chip, and to provide a semiconductor memory suitable for a storage device of a portable electronic device ⁇ a memory card. It is in.
  • a cell array is divided into a plurality of blocks, and a circuit for detecting a state of the cell array for each block and a circuit for variably controlling a refresh cycle are provided.
  • the state detection circuit is, for example, an error correction circuit (ECC circuit) that can correct a 1-bit error (Single Error Correction; SEC).
  • ECC circuit error correction circuit
  • SEC Single Error Correction
  • the refresh cycle is gradually extended, and when the ECC circuit detects a 1-bit error, the self-refresh circuit is controlled so that the refresh cycle at that point or a shorter cycle is performed.
  • the state detection circuit is a register that stores a use area of the DRAM cell array, while the control circuit sets the refresh cycle of the unused area to infinity based on information from the state detection circuit. (Ie, do not refresh).
  • the refresh cycle can be set to the minimum necessary according to the ability of each block of the DRAM array.
  • the current consumption required for one refresh can be minimized.
  • the degree of integration of DRAMs increases, the variation in the information retention time of memory cells within a chip increases, and the number of unused areas in a chip increases, the effect of reducing power consumption will increase.
  • consumption during standby A low-current DRAM can be realized, and a memory suitable for a storage device S ⁇ memory card for portable electronic devices that backs up with a battery during standby can be obtained.
  • FIG. 1 is a control system of a refresh operation in the semiconductor memory of the present invention.
  • Figure 2 shows an automatic refresh cycle optimization method using an ECC circuit.
  • FIG. 3 shows a configuration similar to that of FIG. 2, in which an ECC circuit is shared between blocks.
  • FIG. 4 is a diagram showing a method of determining a refresh cycle at the time of testing in the semiconductor memories of FIGS. 2 and 3.
  • FIG. 5 is a more specific circuit configuration example of FIG.
  • FIG. 6 is a more specific circuit configuration example of FIG.
  • FIG. 7 is an operation waveform showing a change in the refresh cycle in FIG.
  • FIG. 8 is an operation waveform showing the fixation of the refresh cycle in FIG.
  • Fig. 9 is a diagram showing an automatic optimization method of the internal power supply voltage using the ECC circuit.
  • FIG. 10 is a specific example of the internal power supply compression generation circuit of FIG.
  • FIG. 11 is a diagram showing a control method of a refresh area by a use area storage register.
  • FIG. 12 is a more specific circuit configuration example of FIG.
  • FIG. 13 is another example of the used area storage register of FIG.
  • FIG. 14 is an example of a system configuration for realizing the method of FIG.
  • FIG. 15 is a diagram showing a control method of a low pressure supply area by a use area storage register.
  • FIG. 16 shows a control system for refresh operation in a conventional semiconductor memory.
  • FIG. 1 is an embodiment showing a basic configuration of a refresh control method in a DRAM of the present invention.
  • the DRAM cell array is divided into multiple blocks, and the refresh cycle is set to an optimal value for each block.
  • Each block is provided with a state detection circuit for detecting the state of the DRAM cell array, and a refresh clock generation circuit for variably controlling a refresh cycle based on information from the state detection circuit.
  • This control circuit controls a self-refresh control system in a normal DRAM.
  • the ordinary refresh control system comprises a self-refresh circuit for generating an address for performing a refresh, and a multiplexer for selecting one of a refresh address and an external input address and sending the selected address to a row decoder.
  • the self-refresh start signal SRS i (i 1, 2, 3, 3,%) From the variable-period refresh clock generation circuit of each block is sent to the self-refresh circuit, and corresponds to the block to be refreshed.
  • the state detection circuit is, for example, an ECC circuit that corrects a 1-bit error.
  • the refresh clock generation circuit gradually extends the refresh cycle at the time of self-refresh, and The period at which the circuit detects a 1-bit error, or a shorter period, is defined as the subsequent refresh period.
  • the state detection circuit is a use area storage register of the DRAM cell array, and the refresh clock generation circuit refreshes only the use area of the cell array based on the information from the register and uses the unused area. Let the refresh period of be infinite. That is, no refresh is performed. According to the present invention, current consumption required for refresh operation can be suppressed to the minimum necessary for each DRAM chip, and there is an effect that a semiconductor memory that is inexpensive, highly integrated, and has low current consumption during standby can be obtained. .
  • FIG. 2 is an embodiment of the present invention using an ECC circuit as the cell array state detection circuit in FIG.
  • the refresh clock generation circuit gradually extends the refresh cycle at the time of self-refresh, and sets the cycle at the time when the ECC circuit detects a 1-bit error or a cycle slightly shorter than that as the subsequent refresh cycle.
  • each block is refreshed at the longest possible cycle in accordance with the ability of the memory cell to retain information. Therefore, the current consumption required for the refresh operation can be suppressed to the minimum necessary, so that there is an effect that a semiconductor memory with small current consumption during standby can be obtained.
  • FIG. 3 is an embodiment of the present invention in which the ECC circuit in FIG. 2 is shared between blocks.
  • FIG. 3 shows a case where the ECC circuit is provided outside the semiconductor chip, it may be provided inside the chip. Data from each block during self-refresh is sent to the ECC circuit, and if a 1-bit error has occurred, a signal indicating the occurrence of the error is returned to the memory chip. Based on the information of the row decoder, it is possible to identify in which block the error has occurred, and to fix the refresh cycle of the block to that value, Alternatively, a period shorter than the value is set. According to the embodiment of the present invention, in addition to the effects described in the embodiment of FIG. 2, the area occupied by the ECC circuit in the chip can be reduced or eliminated, so that a highly integrated memory chip can be obtained. effective.
  • FIG. 4 is an embodiment of the present invention showing a method of determining a refresh cycle at the time of testing in the configuration of FIG. 2 or FIG.
  • CBR indicates a CAS before RAS signal.
  • the pulse width of 813 ⁇ 4 is equivalent to several sets of the self-refresh cycle.
  • the self-refresh operation is repeated for all the memory cells until the ECC circuit detects an error in a state where the power supply voltage is lower than that in normal use.
  • the refresh cycle is determined by the procedure described in FIG.
  • the cycle at this time is the minimum cycle required for the power supply voltage during the test. In other words, the power supply voltage during normal use is a value with a certain margin.
  • the information is not destroyed even if the information holding time is deteriorated by continuing to use the DRAM chip, and the refresh cycle is set to a sufficiently long refresh cycle according to the ability of the chip.
  • a sufficiently long refresh cycle is set within a range that does not cause an error even if the power supply voltage drops during normal use.
  • the register that stores the set refresh cycle is composed of non-volatile memory so that the refresh cycle set at the time of the test is not lost even if the power is turned off. According to the embodiment of the present invention, it is possible to obtain a semiconductor memory having higher reliability and a lower current consumption during standby, taking into account such things as deterioration of a chip during normal use and a reduction in power supply voltage. There is.
  • Fig. 5 shows the variable-period refresh clock generation circuit in Fig. 2. 1 shows an embodiment of the present invention. Here, only one block (block 1) was extracted.
  • the variable cycle refresh clock generation circuit 1 has a 1-bit error occurrence determination register, a refresh cycle determination shift register, and a refresh cycle generation circuit as its main components.
  • the refresh cycle in the DRAM chip of FIG. 2 is controlled as follows. First, the self-refresh start signal SRS is sent from the refresh cycle generation circuit to the self-refresh circuit. In response to this, the self-refresh circuit sequentially generates refresh addresses by the internal counter, and performs the refresh operation of the DRAM cell array block 1. At this time, the ECC circuit outputs a 1-bit error occurrence flag EF indicating whether or not the stored information is correctly held.
  • SRS self-refresh start signal
  • the self-refresh circuit sequentially generates refresh addresses by the internal counter, and performs the refresh operation of the DRAM cell array block 1.
  • the ECC circuit outputs a 1-bit error occurrence flag
  • the above 1-bit error generation flag EF is set to the variable period refresh clock generation circuit. Sent to.
  • the pulse of the self-refresh start signal is delayed by a delay circuit for about the time td required for the refresh operation of the entire DRAM cell array block 1 and becomes a count-up pulse of the refresh cycle determination shift register.
  • the refresh cycle determination shift register is counted up only when the 1-bit error occurrence determination register is in the 0 state and no error is detected by the ECC circuit during the above-described series of refresh operations.
  • the refresh cycle generation circuit outputs the next self-refresh start signal SRS at a longer interval. The next start from the self-refresh start signal generation described above W contract 28825
  • the procedure up to signal generation is repeated until an error is detected during the refresh operation. And the refresh cycle becomes longer and longer. If the refresh cycle becomes longer than the minimum information retention time of the memory cells in block 1, the ECC circuit detects an error and the 1-bit error flag changes from 0 to 1. As a result, the 1-bit error occurrence judgment register changes from 0 to 1, and after that, regardless of the state of the 1-bit error occurrence flag, the 1 state is maintained until the power is turned off. Then, the count-up of the refresh cycle determination shift register stops. Note that as long as the refresh cycle is gradually lengthened, there is little possibility that multiple bits will fail at the same time when the ECC circuit first detects an error. This is because the information retention time of a memory cell varies greatly from cell to cell.
  • FIG. 6 shows a twisted configuration of the variable period refresh clock generation circuit of FIG. 1 is an embodiment of the present invention showing a physical circuit configuration example.
  • the 1-bit error occurrence determination register, the refresh cycle generator that generates multiple refresh cycles, and the refresh cycle determination that selects one of the multiple cycles are shown in FIG. A shift register is provided.
  • the 1-bit error occurrence determination register is composed of an asymmetric flip-flop circuit. That is, one node EJ of the flip-flop circuit is connected to V ss (0 V) via a high resistance. If the 1-bit error occurrence flag EF goes high after a write operation to the DRAM cell array block 1, EJ is short-circuited to Vcc. With this configuration, when power is turned on, EJ is pulled to V ss via a high resistance, so that an imbalance occurs between the two nodes of the flip-flop, and EJ is latched at the mouth level. If the ECC circuit detects an error during the refresh operation after writing to the DRAM cell array, the EF level changes to high level, and EJ changes to high level.
  • the on-resistance of the p-channel transistor that constitutes the flip-flop circuit is designed to be several orders of magnitude smaller than the resistance value of the resistor connected to V ss, so that even if EF returns to the mouth level, EJ Is latched to a high level.
  • the 1-bit error occurrence determination register holds the low level after the power is turned on, and holds the high level until the power is turned off after the ECC circuit detects at least one error.
  • the state of the 1-bit error occurrence determination register may be stored in nonvolatile memory. .
  • the flag may have the same configuration as that of the 1-bit error occurrence determination register, and may have a configuration in which a write enable signal (WE) and a row address are input instead of the EF.
  • WE write enable signal
  • the cycle T O of the oscillation cycle That is, each time one JK flip-flop is connected in series, its output T l, T 2, etc. has twice the period of the input. By selecting one of these periods T O, T 1, T 2,..., The refresh period can be changed widely.
  • the refresh cycle determination shift register in FIG. 6 is configured by connecting in series JK flip-flops in which the K input is fixed at the high level. Every time the clock CT rises, the state of F0 at the high level is sequentially propagated to the outputs F1, F2,... Of the JK flip-flop, and changes from the mouth to the high level. .. FO, F 1, F 2... And the refresh cycle generation circuit T 0, T 1, T 2,.
  • the refresh cycle can be determined according to the position of the break between the low level and the high level of.
  • the refresh cycle is doubled every time the clock CT rises. CT rises after a time ⁇ T required to refresh the DRAM cell array block 1 has elapsed from the rise of the self-refresh start signal SRS.
  • a signal for generating a CT pulse is generated after a delay of T based on the SRS pulse.
  • the signal for generating a CT pulse may be generated based on a signal from a network circuit. That is, it detects that the refresh power counter in the self-refresh circuit has counted up to the top of the block 1 and generates the above-mentioned signal for generating a CT pulse.
  • FIG. 7 shows a case where no error occurs during the refresh operation
  • FIG. 8 shows a case where an error occurs.
  • Fig. 7 for example, consider the change in the refresh cycle after turning on the source.
  • F0, F1, and F2 of the refresh cycle determination register are at high level, low level, and low level, respectively.
  • T 0, T l, and ⁇ 2 of the refresh cycle generation circuit generate clocks with periods of t, 2 t, and 4 t, respectively, with respect to the oscillation cycle t.
  • the logical type of F 0 and T 0 is A
  • the logical product of F 1 and T 1 is A 1
  • the logical product of F 2 and T 2 is A 2.
  • F0 since F0 is at a high level, only A0 of AO, Al, and A2 changes in synchronization with T0.
  • RT rises in response to the rise of AO, and a short pulse is generated by AND logic of the inverted signal RB and the delay signal.
  • the rising cycle of RT is the cycle in which A 0 and A 1 rise at the same time.
  • FIG. 8 is an operation waveform showing that, when an error is detected during the self-refresh operation, the refresh cycle is fixed at that time. For example, as in FIG. 7, F 0 and F 1 sequentially become high level, and an error occurs in a 2 t refresh cycle.
  • EJ When EF changes to a high level, EJ also changes to a high level and is then clamped to a high level. Since EJ is at the high level, the CT pulse does not rise ⁇ T after the rise of SRS. Therefore, F2 remains at the low level, and the refresh cycle is fixed at 2t.
  • the ECC circuit corrects the error and rewrites the DRAM cell array.
  • An ECC circuit that can detect and correct a 1-bit error, for example, is sufficient. This is because the information retention time of the DRAM cell varies, and if the refresh cycle is gradually extended as in the present invention, when the ECC circuit detects an error for the first time, only one bit error is detected. There can be.
  • the refresh cycle is automatically set in accordance with the ability of the memory cell to retain information, so that the semiconductor device that consumes a small amount of current during standby is used. Memory power, 'can be realized.
  • FIGS. 2 to 8 have described the method in which the current consumption during standby can be reduced by extending the refresh cycle until an error that can be corrected occurs for each DRAM cell array block.
  • FIG. 9 shows an embodiment of the present invention in which the current consumption during standby and during operation is reduced by lowering the internal voltage until a correctable error occurs.
  • Refresh clock Self-refresh start signal
  • the self-refresh circuit sequentially generates refresh addresses by an internal counter, and the refresh operation in the DRAM cell array block 1 is performed. If a stored information error is detected by the ECC circuit during a self-refresh operation after at least one write operation to the DRAM cell relay block 1, the 1-bit error flag EF is set to High level, otherwise low level.
  • the node EJ of the 1-bit error determination register is at a low level until a 1-bit error occurs from power-on, and a 1-bit error occurs. Until the power is turned off, it is held at high level.
  • the refresh clock becomes the clock signal CT of the internal voltage decision shift register after a delay of ⁇ T required for the refresh operation of the DRAM cell array block 1 to end.
  • a CT pulse is generated when EJ of the 1-bit error occurrence determination shift register is at low level and no 1-bit error has occurred at all.
  • the internal state of the shift register changes to Fl, F2,... In sequence each time a pulse is input. I will do it.
  • VL decreases as the range of the high level of the nodes F 0, F 1, F 2... Of the internal voltage determination shift register increases.
  • FIG. 10 shows a specific circuit example of the internal power supply voltage generation circuit in FIG. (A) is a reference voltage generation circuit EB that generates a constant reference voltage VR1 regardless of the power supply voltage, and (b) is a voltage conversion circuit TB that generates a variable voltage VR2 based on VR1. .
  • the threshold voltage V th1 of the MOS transistor ME 1 and the threshold voltage V th2 of the MOS transistor ME 2 are designed to be different values in the EB shown in FIG.
  • VR l
  • FIG. 10 (b) is a circuit for generating a variable VR2 based on VR1.
  • One of the multiple inputs from the internal voltage shift register becomes a high level, and one end of the input of the differential amplifier is connected to any one of the connection portions of the resistors connected in series. The other end of the input is connected to reference potential VR1.
  • the input and VR2 of the differential amplifier connected to the series resistor are stabilized at a constant potential. The more the input is connected to the Vss side, the higher the VR2, and the more the input is connected to the Vcc side, the lower the VR2.
  • the minimum internal voltage is set in accordance with the ability of the memory cell to retain information in each DRAM cell array block. Therefore, a semiconductor memory with low current consumption, which is suitable for a storage device of a portable device, a memory card, or the like, can be obtained.
  • Fig. 11 shows that in a DRAM cell array block divided into a plurality of blocks, the self-refresh operation is performed only for the blocks in the used area, and the refresh cycle of the blocks in the unused area is set to infinity. This is one embodiment of the present invention.
  • a register for storing a used area is provided, and based on the information in this register, an upper address register of a self-refresh circuit for designating a block for performing a self-refresh operation is controlled.
  • the refresh operation is performed only in the area where the information needs to be held, so that the current consumption during standby can be minimized.
  • FIG. 12 is an embodiment of the present invention showing a more specific configuration example of the configuration of FIG.
  • the refresh circuit outputs the refresh address by the signal CBR or the self-refresh signal Se1f
  • the refresh of the entire memory cell array is normally performed.
  • a block to which writing has been performed is detected, and a refresh operation is performed only on that block. That is, the used area storage register is controlled by the signal WE designating the write operation and the row address.
  • the block is divided into four, and each block is selected by a part of the address, for example, A0 and A1.
  • a use area storage register for determining whether or not a write operation has been performed, and storing the information.
  • the used area storage register is composed of four flip-flop circuits corresponding to each block. When the power is turned on, all the nodes on the side of the flip-flop circuit to which a high resistance is connected to V ss are at a low level due to the action of the high resistance. In this state, since the address data does not reach the DRAM array block, no operation is performed, including the refresh operation. If DRAM write-lock signal is accessed while write enable signal WE is at high level, the flip-flop circuit of the used area storage register corresponding to the above block is reset. Turn over.
  • FIG. 13 shows an embodiment of the present invention in which the use area storage register in FIG. 12 is configured to be reset by a reset signal.
  • the reset can be performed by setting the reset signal line Reset to a high level.
  • FIG. 14 is an embodiment of the present invention showing a system configuration for controlling the used area storage register in FIG. 13 (b).
  • the memory cells in the used area storage area are refreshed.
  • the refresh operation is performed only for the used block by the control shown in FIG. 12, for example. According to the embodiment of the present invention, it is possible to obtain a system capable of variably controlling the area of the refresh operation only by changing the software.
  • Fig. 15 shows an example of a DRAM cell array block
  • the power supply voltage Vcc does not reach the DRAM array block until the write operation is performed after the power is turned on.
  • a write operation to a block for example, 1 starts (when WE is high and the address specifies block 1)
  • the flip-flop corresponding to block 1 of the used area storage register is inverted, and Vcc is supplied to block 1.
  • an AAS 1 pulse is generated to indicate that block 1 is in the rising state. During this time, for example, a write operation to block 1 is suspended.
  • the present invention since only the used blocks are activated, it is possible to reduce current consumption during operation and standby. As described above, according to the present invention, the current consumption required for the refresh operation in the DRAM can be minimized, so that a semiconductor memory suitable for a storage device of a portable device ⁇ a memory card can be provided. can get.

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Abstract

Mémoire RAM dynamique à haute densité, à faible coût, dans laquelle le courant servant à la régénération est réduit, utilisable dans un dispositif à mémoire ou dans une carte à mémoire d'appareil portatif. Cette mémoire RAM dynamique est constituée d'un groupement de cellules de mémoire divisé en plusieurs blocs, d'un circuit (tel qu'un circuit de correction d'erreur ou un registre mémoire des zones utilisées) servant à repérer l'état de chaque bloc, et d'un circuit de commande permettant de faire varier la fréquence des régénérations. Ce circuit de commande allonge l'intervalle entre deux régénérations jusqu'à ce que le circuit de correction d'erreur détecte une erreur susceptible de correction, ce qui permet d'obtenir l'intervalle optimal entre deux régénérations pour chaque bloc, et d'avoir un intervalle infini, c'est-à-dire aucune régénération, pour une zone non utilisée. Ce système permet de réduire au minimum, automatiquement, la fréquence des régénérations pour chaque bloc, et ainsi de réduire au minimum l'intensité du courant d'attente.
PCT/JP1995/000433 1995-03-15 1995-03-15 Memoire a semi-conducteur WO1996028825A1 (fr)

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Cited By (14)

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JP2002025299A (ja) * 2000-07-10 2002-01-25 Hitachi Ltd エラーレート判定方法と半導体集積回路装置
JP2002056671A (ja) * 2000-08-14 2002-02-22 Hitachi Ltd ダイナミック型ｒａｍのデータ保持方法と半導体集積回路装置
US6693838B2 (en) * 2002-04-15 2004-02-17 Renesas Technology Corp. Semiconductor memory device equipped with refresh timing signal generator
WO2004093089A1 (fr) * 2003-04-15 2004-10-28 International Business Machines Corporation Dispositif memoire a semi-conducteur dynamique
US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
JP2005004947A (ja) * 2003-05-20 2005-01-06 Nec Electronics Corp メモリ装置及びメモリのエラー訂正方法
WO2005045845A1 (fr) * 2003-11-07 2005-05-19 Infineon Technologies Ag Rafraichissement de cellules dynamiques a faible retention
US6925021B2 (en) 2001-03-08 2005-08-02 Micron Technology, Inc. Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
US7072237B2 (en) 2002-04-11 2006-07-04 Micron Technology, Inc. Method and system for low power refresh of dynamic random access memories
JP2008186584A (ja) * 2008-04-25 2008-08-14 Elpida Memory Inc 半導体記憶装置及びそのリフレッシュ制御方法
JP2008251066A (ja) * 2007-03-29 2008-10-16 Nec Corp メモリ制御方法、メモリシステム、およびプログラム
CN100587834C (zh) * 2003-02-19 2010-02-03 飞思卡尔半导体公司 存储器和用于刷新存储器阵列的方法
US8549366B2 (en) 2007-07-18 2013-10-01 Fujitsu Limited Memory refreshing circuit and method for memory refresh
CN104615503A (zh) * 2015-01-14 2015-05-13 广东省电子信息产业集团有限公司 降低对存储器接口性能影响的闪存错误检测方法及装置

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JP4627411B2 (ja) * 2003-05-20 2011-02-09 ルネサスエレクトロニクス株式会社 メモリ装置及びメモリのエラー訂正方法
US7095669B2 (en) 2003-11-07 2006-08-22 Infineon Technologies Ag Refresh for dynamic cells with weak retention
WO2005045845A1 (fr) * 2003-11-07 2005-05-19 Infineon Technologies Ag Rafraichissement de cellules dynamiques a faible retention
JP2008251066A (ja) * 2007-03-29 2008-10-16 Nec Corp メモリ制御方法、メモリシステム、およびプログラム
US8549366B2 (en) 2007-07-18 2013-10-01 Fujitsu Limited Memory refreshing circuit and method for memory refresh
JP2008186584A (ja) * 2008-04-25 2008-08-14 Elpida Memory Inc 半導体記憶装置及びそのリフレッシュ制御方法
CN104615503A (zh) * 2015-01-14 2015-05-13 广东省电子信息产业集团有限公司 降低对存储器接口性能影响的闪存错误检测方法及装置

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