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TWI849757B - 電子封裝件及其封裝基板與製法 - Google Patents

電子封裝件及其封裝基板與製法 Download PDF

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TWI849757B
TWI849757B TW112105985A TW112105985A TWI849757B TW I849757 B TWI849757 B TW I849757B TW 112105985 A TW112105985 A TW 112105985A TW 112105985 A TW112105985 A TW 112105985A TW I849757 B TWI849757 B TW I849757B
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electrical contact
conductive bump
pad
conductive
contact pad
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TW112105985A
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TW202435379A (zh
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葉展佑
白裕呈
葉遠平
倪元昌
何孟柔
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矽品精密工業股份有限公司
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Priority to TW112105985A priority Critical patent/TWI849757B/zh
Priority to CN202310171704.4A priority patent/CN118522700A/zh
Priority to US18/325,846 priority patent/US20240282689A1/en
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Publication of TWI849757B publication Critical patent/TWI849757B/zh
Publication of TW202435379A publication Critical patent/TW202435379A/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

一種電子封裝件及其封裝基板與製法，其在封裝基板之電性接觸墊上設有導電凸墊，以當電子元件採用覆晶方式透過銲錫材接合該封裝基板時，該導電凸墊可引導銲錫材之流動，故能避免銲錫材未有效接觸該電性接觸墊而發生空銲之問題。

Description

電子封裝件及其封裝基板與製法
本發明係有關一種半導體封裝製程，尤指一種電子封裝件及其封裝基板與製法。
隨著電子產業的蓬勃發展，電子產品在型態上趨於輕薄短小，在功能上則朝高性能、高功能、高速化的研發方向。此外，為滿足半導體裝置之高積集度(Integration)及微型化(Miniaturization)需求，故於封裝製程中，常常採用具有高密度及細間距之線路的封裝基板。
如圖1所示，習知半導體封裝件1係於一具有複數電性接觸墊100之封裝基板10上藉由銲錫凸塊13覆晶接合一半導體晶片11，再以底膠14包覆該些銲錫凸塊13。
惟，部分銲錫凸塊130於回銲過程中，容易溢流至其它處而橋接相鄰之兩電性接觸墊100，導致該半導體晶片11之電性短路。
再者，部分銲錫凸塊131於回銲過程中容易因受該半導體晶片11擠壓而偏位，導致該銲錫凸塊131發生空銲而無法準確連接該電性接觸墊100，致使該半導體晶片11之電性斷路。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種封裝基板，係包括：佈線結構，係具有相對之第一表面與第二表面，且包含有絕緣層及設於該絕緣層上之佈線層；線路層，係嵌埋於該佈線結構之第二表面之絕緣層中以電性連接該佈線層，其中，該線路層係具有複數外露於該絕緣層之電性接觸墊；以及導電凸墊，係設於該複數電性接觸墊之至少一者上，且該導電凸墊之寬度係小於該電性接觸墊之寬度，其中，形成該導電凸墊之材質係不同於形成該電性接觸墊之材質。
本發明亦提供一種封裝基板之製法，係包括：提供一具有金屬層之承載件；於該金屬層上形成導電凸墊，其中，形成該導電凸墊之材質係不同於形成該金屬層之材質；形成線路層於該金屬層上，且該線路層具有複數電性接觸墊，以令該複數電性接觸墊之至少一者包覆該導電凸墊，其中，形成該導電凸墊之材質係不同於形成該電性接觸墊之材質；形成佈線結構於該金屬層上，該佈線結構具有相對之第一表面與第二表面，且包含有形成於該金屬層與該線路層上之絕緣層及設於該絕緣層上以電性連接該線路層之佈線層；以及移除該承載件及其上之金屬層，以外露該線路層之電性接觸墊與該導電凸墊，其中，該導電凸墊之寬度係小於該電性接觸墊之寬度。
前述之封裝基板及其製法中，形成該導電凸墊之材質係為鎳材，且形成該電性接觸墊之材質係為銅材。
前述之封裝基板及其製法中，該導電凸墊係嵌入該電性接觸墊中。
前述之封裝基板及其製法中，該絕緣層於該電性接觸墊處形成一凹部，且該導電凸墊位於該凹部中。例如，該導電凸墊與該凹部之壁面之間的距離係大於該電性接觸墊的寬度的1/3以上。
前述之封裝基板及其製法中，該絕緣層於該複數電性接觸墊之相鄰兩者之間的寬度係大於該電性接觸墊的寬度的1/3以上。
前述之封裝基板及其製法中，該導電凸墊之墊面係齊平該佈線結構之第二表面。
前述之封裝基板及其製法中，該導電凸墊之墊面係低於該佈線結構之第二表面。
本發明亦提供一種電子封裝件，係包括：前述之封裝基板；以及電子元件，係藉由複數導電凸塊設於該複數電性接觸墊上，其中，至少一該導電凸塊係結合該導電凸墊。
本發明另提供一種電子封裝件之製法，係包括：提供一前述之封裝基板；以及將電子元件藉由複數導電凸塊設於該複數電性接觸墊上，其中，至少一該導電凸塊係結合該導電凸墊。
前述之電子封裝件及其製法中，該導電凸塊係為銲錫材料。
由上可知，本發明之電子封裝件及其封裝基板與製法，主要藉由將該導電凸墊設於該電性接觸墊上且該墊面不高於該絕緣層，以當該電子元件採用覆晶方式接合該封裝基板時，該導電凸墊於回銲該導電凸塊時可引導銲錫材之流動，故相較於習知技術，本發明之電子封裝件於製作過程中能 避免該導電凸塊未有效接觸該電性接觸墊而發生空銲之問題，且避免該導電凸塊連接相鄰之兩個電性接觸墊而發生短路之問題。
1:半導體封裝件
10:封裝基板
100,210:電性接觸墊
11:半導體晶片
13,130,131:銲錫凸塊
14:底膠
2:電子封裝件
2a,3a:封裝基板
20,30:導電凸墊
20a,30a:墊面
21:線路層
210:電性接觸墊
22:佈線結構
22a:第一表面
22b:第二表面
220:絕緣層
221:佈線層
23:絕緣保護層
26:電子元件
26a:作用面
26b:非作用面
260:電極墊
27:導電凸塊
9:承載件
90:板體
91:金屬層
92:金屬塊體
S:凹部
D,R,X:寬度
L:共平面
h:高度差
t:距離
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2F係為本發明之電子封裝件之製法之剖面示意圖。
圖3A至圖3B係為本發明之封裝基板之另一製法之剖面示意圖。
圖4係為本發明之封裝基板之局部剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2F係為本發明之電子封裝件2之製法之剖面示意圖。
如圖2A所示，於一承載件9之相對兩側上均形成複數導電凸墊20。
於本實施例中，該承載件9係包含一板體90及形成於該板體90兩側上之金屬層91。例如，該板體90為半導體材質(如矽或玻璃)，其上以例如塗佈方式依序形成有一如鈦/銅之金屬層91。
再者，該導電凸墊20係為如鎳之金屬體，其以圖案化方式佈設於該金屬層91上。例如，形成該金屬層91之材質係不同於形成該導電凸墊20之材質。
如圖2B所示，形成一線路層21於該承載件9之金屬層91上，且令該線路層21包覆該導電凸墊20。
於本實施例中，該線路層21係具有複數電性接觸墊210，以令該複數電性接觸墊210之至少一者接觸包覆該導電凸墊20。
再者，該線路層21係採用電鍍金屬(如銅材)或其它方式製作，且形成該線路層21之材質係不同於形成該導電凸墊20之材質。
如圖2C所示，於該承載件9兩側之金屬層91上分別形成一佈線結構22，且令該佈線結構22電性連接該線路層21。
於本實施例中，各該佈線結構22係定義有相對之第一表面22a及第二表面22b，以令該佈線結構22以其第二表面22b結合於該承載件9上。
再者，該佈線結構22係包含至少一形成於該金屬層91與該線路層21上之絕緣層220、及形成於該絕緣層220上以電性連接該線路層21 之佈線層221，如線路重佈層(redistribution layer，簡稱RDL)規格。例如，該絕緣層220係為介電層，如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、具玻纖之預浸材(Prepreg，簡稱PP)或其它等介電材，且形成該佈線層221之材質係為銅。
又，於該佈線結構22之第一表面22a上可依需求形成一如綠漆、油墨或其它防銲材之絕緣保護層23，以包覆該第一表面22a上之佈線層221，且令該佈線層221之外表面係外露於該絕緣保護層23。例如，該絕緣保護層23之外表面係齊平該佈線層221之外表面。
如圖2D及圖2E所示，移除該承載件9之板體90，以外露出該金屬層91，再移除該金屬層91，以獲取複數個封裝基板2a，其外露該佈線結構22之第二表面22b及該導電凸墊20與該線路層21，以令該線路層21嵌埋於該絕緣層220中，且該導電凸墊20係嵌入該電性接觸墊210中並凸出該電性接觸墊210，使該絕緣層220於該電性接觸墊210處形成凹部S。
於本實施例中，該導電凸墊20之寬度R係小於該電性接觸墊210之寬度D，且該導電凸墊20之墊面20a係齊平該佈線結構22之第二表面22b(或絕緣層220之表面)，如圖2E所示之共平面L。
再者，藉由蝕刻方式移除該金屬層91，將一併蝕刻移除該線路層21之部分材質，以令該線路層21凹入該佈線結構22之第二表面22b(或絕緣層220之表面)，使該導電凸墊20凸出該電性接觸墊210。
又，如圖3A及圖3B所示，於另一實施例中，若於圖2A所示之製程前，先形成一材質同於該金屬層91之金屬塊體92，則當蝕刻移除該金屬層91時，將一併蝕刻移除該金屬塊體92，以令該導電凸墊30凹入該佈線 結構22之第二表面22b(或絕緣層220之表面)，如圖3B所示之封裝基板3a具有高度差h，使該導電凸墊30之墊面30a低於該佈線結構22之第二表面22b(或絕緣層220之表面)，但該導電凸墊30仍凸出該電性接觸墊210。
如圖2F所示，配置至少一電子元件26於該封裝基板2a之佈線結構22之第二表面22b上，以形成一電子封裝件2，且該電子元件26藉由導電凸塊27電性連接該導電凸墊20與該電性接觸墊210。
所述之電子元件26係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該電子元件26係為半導體晶片，其具有相對之作用面26a與非作用面26b，該作用面26a具有複數電極墊260，以令該電子元件26採用覆晶方式以其電極墊260藉由該些導電凸塊27結合至該電性接觸墊210上。
所述之導電凸塊27係為銲錫材料，其結合該電極墊260與該電性接觸墊210，以包覆該導電凸墊20。
因此，本發明之電子封裝件2之製法，主要藉由將該導電凸墊20設於該電性接觸墊210上且該墊面20a不高於該絕緣層220，以當該電子元件26採用覆晶方式接合該封裝基板2a,3a時，該導電凸墊20於回銲該導電凸塊27時可引導銲錫材之流動，故相較於習知技術，本發明之電子封裝件2於製作過程中能避免該導電凸塊27未有效接觸該電性接觸墊210而發生空銲之問題，且能避免該導電凸塊27連接相鄰之兩個電性接觸墊210而發生短路之問題。
較佳地，如圖4所示，該導電凸墊20與該絕緣層220之凹部S之壁面之間的距離t係大於該電性接觸墊210的寬度D的1/3以上，以於回銲該導電凸塊27時，該銲錫材更容易流至該電性接觸墊210上。
較佳地，該絕緣層220於相鄰兩電性接觸墊210之間的寬度X係大於該電性接觸墊210的寬度D的1/3以上，以於回銲該導電凸塊27時，該銲錫材無法流動至相鄰之電性接觸墊210上，故更能避免該導電凸塊27未有效接觸該電性接觸墊210而發生空銲之問題，且更能避免該導電凸塊27連接相鄰之兩個電性接觸墊210而發生短路之問題。
本發明亦提供一種封裝基板2a,3a，係包括：一佈線結構22、一線路層21以及至少一導電凸墊20,30。
所述之佈線結構22係具有相對之第一表面22a與第二表面22b，且包含至少一絕緣層220、及設於該絕緣層220上之佈線層221。
所述之線路層21係嵌埋於該佈線結構22之第二表面22b之絕緣層220中以電性連接該佈線層221，其中，該線路層21係具有複數外露於該絕緣層220之電性接觸墊210。
所述之導電凸墊20,30係設於該複數電性接觸墊210之至少一者上，且該導電凸墊20,30之寬度R係小於該電性接觸墊210之寬度D，其中，形成該導電凸墊20,30之材質係不同於形成該電性接觸墊210之材質。
於一實施例中，形成該導電凸墊20,30之材質係為鎳材，且形成該電性接觸墊210之材質係為銅材。
於一實施例中，該導電凸墊20,30係嵌入該電性接觸墊210中。
於一實施例中，該絕緣層220於該電性接觸墊210處形成一凹部S，且該導電凸墊20,30位於該凹部S中。例如，該導電凸墊20,30與該凹部S之壁面之間的距離t係大於該電性接觸墊210的寬度D的1/3以上。
於一實施例中，該絕緣層220於該複數電性接觸墊210之相鄰兩者之間的寬度X係大於該電性接觸墊210的寬度D的1/3以上。
於一實施例中，該導電凸墊20之墊面20a係齊平該佈線結構22之第二表面22b。
於一實施例中，該導電凸墊30之墊面30a係低於該佈線結構22之第二表面22b。
本發明亦提供一種電子封裝件2，係包括：一封裝基板2a,3a以及至少一藉由複數導電凸塊27設於該複數電性接觸墊210上之電子元件26。
所述之導電凸塊27係結合該導電凸墊20,30。
於一實施例中，該導電凸塊27係為銲錫材料。
綜上所述，本發明之電子封裝件及其封裝基板與製法，係藉由將該導電凸墊設於該電性接觸墊上且該導電凸墊之墊面不高於該絕緣層，以當該電子元件採用覆晶方式接合該封裝基板時，該導電凸墊於回銲該導電凸塊時可引導銲錫材之流動，故本發明之電子封裝件於製作過程中能避免該導電凸塊未有效接觸該電性接觸墊而發生空銲之問題，且避免該導電凸塊連接相鄰之兩個電性接觸墊而發生短路之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇 下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:封裝基板
20:導電凸墊
21:線路層
210:電性接觸墊
22:佈線結構
22a:第一表面
22b:第二表面
220:絕緣層
221:佈線層
23:絕緣保護層
26:電子元件
26a:作用面
26b:非作用面
260:電極墊
27:導電凸塊
S:凹部

Claims (20)

  1. 一種封裝基板，係包括：佈線結構，係具有相對之第一表面與第二表面，且包含有絕緣層及設於該絕緣層上之佈線層；線路層，係嵌埋於該佈線結構之第二表面之絕緣層中以電性連接該佈線層，其中，該線路層係具有複數外露於該絕緣層之電性接觸墊；以及導電凸墊，係嵌設於該複數電性接觸墊之至少一者中並凸出該電性接觸墊，且該導電凸墊之寬度係小於該電性接觸墊之寬度，且形成該導電凸墊之材質係不同於形成該電性接觸墊之材質。
  2. 如請求項1所述之封裝基板，其中，形成該導電凸墊之材質係為鎳材，且形成該電性接觸墊之材質係為銅材。
  3. 如請求項1所述之封裝基板，其中，該導電凸墊係嵌入該電性接觸墊中。
  4. 如請求項1所述之封裝基板，其中，該絕緣層於該電性接觸墊處形成一凹部，且該導電凸墊位於該凹部中。
  5. 如請求項4所述之封裝基板，其中，該導電凸墊與該凹部之壁面之間的距離係大於該電性接觸墊的寬度的1/3以上。
  6. 如請求項1所述之封裝基板，其中，該絕緣層於該複數電性接觸墊之相鄰兩者之間的寬度係大於該電性接觸墊的寬度的1/3以上。
  7. 如請求項1所述之封裝基板，其中，該導電凸墊之墊面係齊平該佈線結構之第二表面。
  8. 如請求項1所述之封裝基板，其中，該導電凸墊之墊面係低於該佈線結構之第二表面。
  9. 一種電子封裝件，係包括：如請求項1至8任一項所述之封裝基板；以及電子元件，係藉由複數導電凸塊設於該複數電性接觸墊上，其中，至少一該導電凸塊係結合該導電凸墊。
  10. 如請求項9所述之電子封裝件，其中，該導電凸塊係為銲錫材料。
  11. 一種封裝基板之製法，係包括：提供一具有金屬層之承載件；於該金屬層上形成導電凸墊，其中，形成該導電凸墊之材質係不同於形成該金屬層之材質；形成線路層於該金屬層上，且該線路層具有複數電性接觸墊，以令該複數電性接觸墊之至少一者包覆該導電凸墊，其中，形成該導電凸墊之材質係不同於形成該電性接觸墊之材質；形成佈線結構於該金屬層上，該佈線結構具有相對之第一表面與第二表面，且包含有形成於該金屬層與該線路層上之絕緣層及設於該絕緣層上以電性連接該線路層之佈線層；以及移除該承載件及其上之金屬層，以外露該線路層之電性接觸墊與該導電凸墊，其中，該導電凸墊之寬度係小於該電性接觸墊之寬度。
  12. 如請求項11所述之封裝基板之製法，其中，形成該導電凸墊之材質係為鎳材，且形成該電性接觸墊之材質係為銅材。
  13. 如請求項11所述之封裝基板之製法，其中，該導電凸墊係嵌入該電性接觸墊中。
  14. 如請求項11所述之封裝基板之製法，其中，該絕緣層於該電性接觸墊處形成一凹部，且該導電凸墊位於該凹部中。
  15. 如請求項14所述之封裝基板之製法，其中，該導電凸墊與該凹部之壁面之間的距離係大於該電性接觸墊的寬度的1/3以上。
  16. 如請求項11所述之封裝基板之製法，其中，該絕緣層於該複數電性接觸墊之相鄰兩者之間的寬度係大於該電性接觸墊的寬度的1/3以上。
  17. 如請求項11所述之封裝基板之製法，其中，該導電凸墊之墊面係齊平該佈線結構之第二表面。
  18. 如請求項11所述之封裝基板之製法，其中，該導電凸墊之墊面係低於該佈線結構之第二表面。
  19. 一種電子封裝件之製法，係包括：提供一如請求項1至8任一項所述之封裝基板；以及將電子元件藉由複數導電凸塊設於該複數電性接觸墊上，其中，至少一該導電凸塊係結合該導電凸墊。
  20. 如請求項19所述之電子封裝件之製法，其中，該導電凸塊係為銲錫材料。
TW112105985A 2023-02-18 2023-02-18 電子封裝件及其封裝基板與製法 TWI849757B (zh)

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