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TWI455271B - 半導體元件結構及其製法 - Google Patents

半導體元件結構及其製法 Download PDF

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TWI455271B
TWI455271B TW100118060A TW100118060A TWI455271B TW I455271 B TWI455271 B TW I455271B TW 100118060 A TW100118060 A TW 100118060A TW 100118060 A TW100118060 A TW 100118060A TW I455271 B TWI455271 B TW I455271B
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layer
conductive
semiconductor device
device structure
forming
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TW201248815A (en
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趙俊杰
盧俊宏
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矽品精密工業股份有限公司
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Priority to TW100118060A priority Critical patent/TWI455271B/zh
Priority to CN2011101540450A priority patent/CN102800633A/zh
Priority to US13/242,359 priority patent/US20120299177A1/en
Publication of TW201248815A publication Critical patent/TW201248815A/zh
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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Description

半導體元件結構及其製法
本發明係有關於一種半導體元件結構及其製法，尤指一種半導體元件之線路結構及其製法。
按，隨著科技的快速發展，各種新的產品不斷推陳出新，為了滿足消費著方便使用及攜帶容易之需求，現今各式電子產品無不朝向輕、薄、短、小發展。
而現今之電子產品除了要有輕、薄、短、小之特性外，亦希望電子產品能兼具高效能、低耗電、多功能等產品特性，故業界遂發展出覆晶接合之封裝結構(Flip chip packaged structure)，該封裝結構係將一半導體晶片主動面朝下，並以複數銲錫凸塊接置於主動面之電極墊上，而連接於於一封裝基板之電性連接墊，之後再填充底膠(Under fill)於晶片與封裝基板所形成之間隙中，以完成一覆晶接合之封裝結構。此較習知之以金屬線連接半導體晶片與封裝結構之打線式封裝結構，其具有高效能及薄小之特性。
惟前述之覆晶式封裝結構於當半導體晶片逐漸縮小時，其將不敷使用，原因在於當半導體晶片繼續微型化及高功效時，其半導體晶片之面積亦逐漸縮小，且該主動面亦須容納更多電極墊，則電極墊之面積亦相對縮小，故將該半導體晶片以銲錫凸塊接置於封裝基板時，則因半導體晶片、底膠、銲錫凸塊、封裝基板等材質之熱膨脹係數(CTE)差異過大，而造成更縮小化之銲錫凸塊造成斷裂，使得覆晶式封裝結構產生電性可靠度不佳之問題。
於此，業界遂開發出將有電性之半導體晶片接置於一矽載板，並將該矽載板再接合至封裝基板上，使半導體晶片間接電性連接於封裝基板，而半導體晶片與矽載板之熱膨脹係數接近，故不會有銲錫凸塊斷裂的問題。其中該矽載板須先形成矽穿孔(Through-Silicon Via,TSV)，再於該矽穿孔中填充有導電材料，以將半導體晶片接置於其上。
請參閱第1圖，係為習知具矽穿孔之晶片堆疊封裝結構，如圖所示，係於一封裝基板10上以銲球11電性連接具矽穿孔120之矽質內層板12，而該矽穿孔120中係填充有金屬材料，且於該內層板12上接置一般之半導體晶片13，以成為堆疊結構。
而業界形成金屬材料於係穿孔之方式如第7638867號美國專利所揭示，其係利用銲錫材料以網版印刷(stencil printing)方式填充於矽穿孔中，而當矽穿孔之孔徑越趨狹小時，金屬材料並無法完全填入矽穿孔中，而造成填充金屬材料之矽穿孔中產生孔洞，而導致可靠度不佳之問題；更甚者，金屬材質並未填入矽穿孔中，則會有上、下層電子元件無法電性連接之問題。
因此，鑒於上述之問題，如何提供一種簡化之製程以製作半導體元件結構，俾偍升整體封裝製程效率及降低製作成本，實已成為目前亟欲解決之課題。
鑑於上述習知技術之種種缺失，本發明揭露一種半導體元件結構，係包括：具有複數開孔之板體；形成於該板體表面及該開孔表面上的絕緣層；以及由形成於該開孔中之導電塊及與該導電塊接觸之導電層所構成之重佈線路，其中，該導電層係形成於該板體表面之部分絕緣層上。
依上述之半導體元件結構，該導電塊與該導電跡線齊平。
依上所述，本發明之半導體元件結構復可包括形成於該板體表面上之絕緣層及重佈線路上之第一絕緣保護層，且該第一絕緣保護層具有複數第一絕緣保護層開孔，以外露出部份重佈線路而成為複數接觸墊。
如上所述，本發明之半導體元件結構復可包括金屬保護層，係形成於各該接觸墊上。
為得到前述之半導體元件結構，本發明復提供一種半導體元件結構之製法，係包括：於一具有複數開孔之板體表面及該些開孔中形成絕緣層；於該絕緣層上形成導電層；於該開孔中之導電層上形成導電塊，且該導電塊與該板體表面上之導電層齊平；於該導電塊及部分導電層上利用光阻及圖案化製程形成圖案化線路阻層，俾藉由該圖案化線路阻層構成重佈線路圖案，且外露出部分導電層；蝕刻移除該外露之部分導電層，以外露出該絕緣層並令被遮蔽之導電層部分形成導電跡線；以及移除該阻層，以由該導電塊及導電跡線構成重佈線路。
依上述之半導體元件結構之製法，復包括於該外露之絕緣層及重佈線路上形成第一絕緣保護層，且令該第一絕緣保護層具有複數第一絕緣保護層開孔，以外露出部份重佈線路而成為複數接觸，且於各該接觸墊上形成金屬保護層。
依上述之半導體元件結構及其製法，形成該板體之材料係為具有矽材質之板體。
由上可知，本發明之半導體元件結構及其製法，係於具有複數開孔的板體中先形成絕緣層、導電層及導電塊，之後圖案化該導電層以形成重佈線路，其中，習知技術之金屬材料並無法完全填入矽穿孔中形成導電塊，而造成填充金屬材料之矽穿孔中產生孔洞，而導致可靠度不佳之問題，或更甚者，金屬材質並未填入矽穿孔中，而形成斷路。因此藉由本發明之半導體元件結構及其製法能簡化整體之製程及節省材料成本，亦可提高產品結構之可靠度目的。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“頂面”、“底面”、“一”、“上”及“下”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2F圖，係為本發明所揭露之半導體元件結構之製法。
如第2A圖所示，首先，提供具有複數開孔200之板體20，形成該板體20之材料係例如含矽材質之晶片，其可應用於多晶片堆疊結構之內層板，但不以此為限。且第2A’圖所示之另一非限制性實施例中，該開孔200之底部係連接導電通孔26之端面。於該板體20之表面上及該些開孔200表面上依序形成絕緣層21及導電層22。
如第2B圖所示，以該導電層22作為電鍍之電流傳導路徑，於該開孔200中之導電層22上電鍍形成導電塊230，且該導電塊230可與該板體20表面上之導電層22齊平。
如第2C圖所示，於該導電塊230及部分導電層22上形成圖案化線路阻層24，俾藉由該圖案化線路阻層24構成重佈線路圖案，且該圖案化線路阻層24外露出部份之導電層22。亦即全面施加一阻層於導電塊230及導電層22上，經由圖案化製程以將阻層形成圖案化線路阻層24，即後續欲形成導電跡線之導電層22上具有阻層。
如第2D圖所示，先蝕刻移除該外露於圖案化線路阻層24之部分導電層22，以外露出其下之絕緣層21，並令被圖案化線路阻層24遮蔽之導電層22部分形成導電跡線220。接著，再移除該圖案化線路阻層24，以外露出該導電跡線220，以由該導電塊230及導電跡線220構成重佈線路23。此外，復可於該重佈線路23上形成至少一增層結構25，該增層結構25具有至少一介電層250、設於該介電層250上之線路層251、及設於該介電層250中且電性連接該線路層251與該重佈線路23的導電盲孔252，如第2D’圖所示。
如第2E圖所示，接著，移除該板體20之底面，亦即以研磨或蝕刻未形成該絕緣層21及導電層22之表面，以露出該開孔200底部之導電塊230，在本實施例中，該導電塊230作該板體20上、下表面之導電路徑。
如第2F圖所示，復可於該絕緣層21及重佈線路23上形成具有複數第一絕緣保護層開孔270a之第一絕緣保護層27a，且該些第一絕緣保護層開孔270a並外露出部份之重佈線路23，以令該些外露之重佈線路23作為接觸墊221，又於各該接觸墊221上形成金屬保護層28，如UBM層(凸塊底部金屬層)。另一方面，該重佈線路23和金屬保護層28亦可形成於該增層結構25上。
此外，於該板體20底面形成具有複數第二絕緣保護層開孔270b之第二絕緣保護層27b，且各該第二絕緣保護層開孔270b外露出各該導電塊230之端面，並於各該第二絕緣保護層開孔270b中之導電塊230上形成植球墊29，以令各該導電通孔26電性連接至各該植球墊29。又該板體20底面亦可如其相對表面一樣，形成有增層結構於板體20底面及導電塊230表面(圖未示)，之後再形成第二絕緣保護層27b和植球墊29。
請參閱第2F’圖，於另一態樣中，若該板體20之開孔200之底部係連接導電通孔26，如第2A’圖所示，則該第二絕緣保護層開孔270b係外露出各該導電通孔26，植球墊29則係形成於該第二絕緣保護層開孔270b中之導電通孔26上。
本發明復提供一種半導體元件結構，係包括：板體20、絕緣層21及重佈線路23。
所述之板體20，係具有複數開孔200，而形成該板體20之材料係例如為含矽之材質板體。
所述之絕緣層21，係形成於該開設有該開孔200之板體20表面及該開孔200表面上。
所述之重佈線路23，係由形成於該開孔200中之導電塊230及與該導電塊230接觸之導電跡線220所構成，其中，該導電跡線220係形成於該部分絕緣層21上，且該導電跡線220復延伸形成於該開孔200中之絕緣層21與導電塊230之間，又該導電塊230與該板體20表面之導電跡線220齊平。
此外，該半導體元件結構復可包括第一絕緣保護層27a，係形成於該板體20表面上之絕緣層21及重佈線路23上，且具有複數第一絕緣保護層開孔270a，以外露出部份重佈線路23而成為複數接觸墊221。
本發明之半導體元件結構及其製法，係於具有複數開孔的板體中先形成絕緣層、導電層，且再於該開孔中形成導電塊，且所形成之導電塊與該板體上之導電層齊平，之後於該導電層上形成圖案化之圖案化線路阻層，然後蝕刻移除未為該圖案化線路阻層覆蓋之導電層，並令被遮蔽之導電層部分形成導電跡線，接著移除該圖案化線路阻層，以由該導電塊及導電跡線構成重佈線路，本發明製法及所得之半導體元件結構，因該導導電塊係由以電鍍方式形成，因而能免除習知技術之金屬材料並無法完全填入矽穿孔中形成導電塊，而造成填充金屬材料之矽穿孔中產生孔洞，而導致可靠度不佳之問題，或更甚者，金屬材質並未填入矽穿孔中，而形成斷路。因此藉由本發明之半導體元件結構及其製法能簡化整體之製程及節省材料成本，亦可提高產品結構之可靠度目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．封裝基板
11．．．銲球
12．．．內層板
120．．．矽穿孔
13．．．半導體晶片
20．．．板體
200．．．開孔
21．．．絕緣層
22．．．導電層
220．．．導電跡線
221．．．接觸墊
23．．．重佈線路
230．．．導電塊
24．．．圖案化線路阻層
25．．．增層結構
250．．．介電層
251．．．線路層
252．．．導電盲孔
26．．．導電通孔
27a．．．第一絕緣保護層
270a．．．第一絕緣保護層開孔
27b．．．第二絕緣保護層
270b．．．第二絕緣保護層開孔
28．．．金屬保護層
29．．．植球墊
第1圖係為習知具矽穿孔之晶片堆疊封裝結構的剖視示意圖；以及
第2A至2F圖係為本發明半導體元件結構製法剖視示意圖，其中，第2A’圖係第2A圖之另一實施態樣；第2D’圖係於該重佈線路上形成增層結構之示意圖；第2F’圖係根據第2A’圖所得之半導體元件結構。
20．．．板體
21．．．絕緣層
22．．．導電層
220．．．導電跡線
230．．．導電塊
23．．．重佈線路

Claims (12)

  1. 一種半導體元件結構，係包括：板體，係具有複數開孔；絕緣層，係形成於該板體表面及該開孔表面上；以及重佈線路，係由形成於該開孔中之導電塊及與該導電塊接觸之導電跡線所構成，其中，該導電跡線係形成於該板體表面之部分絕緣層上。
  2. 如申請專利範圍第1項所述之半導體元件結構，其中，形成該板體之材料係為具有矽材質之板體。
  3. 如申請專利範圍第1項所述之半導體元件結構，其中，該導電塊與該導電跡線齊平。
  4. 如申請專利範圍第1項所述之半導體元件結構，其中，該導電跡線復延伸形成於該開孔中之絕緣層與導電塊之間。
  5. 如申請專利範圍第1項所述之半導體元件結構，復包括至少一增層結構設置於重佈線路上。
  6. 如申請專利範圍第1項所述之半導體元件結構，復包括第一絕緣保護層，係形成於該板體表面上之絕緣層及重佈線路上，且具有複數第一絕緣保護層開孔，以外露出部份重佈線路。
  7. 如申請專利範圍第6項所述之半導體元件結構，復包括金屬保護層，係形成於該外露之重佈線路上。
  8. 一種半導體元件結構之製法，係包括：於一具有複數開孔之板體表面及該些開孔中形成絕緣層；於該絕緣層上形成導電層；於該開孔中之導電層上形成導電塊，且該導電塊與該板體表面上之導電層齊平；於該導電塊及部分導電層上形成圖案化線路阻層，俾藉由該圖案化線路阻層構成重佈線路圖案，且外露出部分導電層；蝕刻移除該外露之部分導電層，以外露出該絕緣層並令被遮蔽之導電層部分形成導電跡線；以及移除該阻層，以由該導電塊及導電跡線構成重佈線路。
  9. 如申請專利範圍第8項所述之半導體元件結構之製法，其中，形成該板體之材料係為矽。
  10. 如申請專利範圍第8項所述之半導體元件結構之製法，復包括形成至少一增層結構於重佈線路上。
  11. 如申請專利範圍第8項所述之半導體元件結構之製法，復包括於該外露之絕緣層及重佈線路上形成第一絕緣保護層，且令該第一絕緣保護層具有複數第一絕緣保護層開孔，以外露出部份重佈線路。
  12. 如申請專利範圍第11項所述之半導體元件結構之製法，復包括於該外露之重佈線路上形成金屬保護層。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US9373564B2 (en) 2014-08-07 2016-06-21 Industrial Technology Research Institute Semiconductor device, manufacturing method and stacking structure thereof
KR20160122020A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 기판 및 이를 구비하는 반도체 패키지
US9666530B1 (en) * 2015-12-28 2017-05-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850102A (en) * 1996-04-03 1998-12-15 Kabushiki Kaisha Toshiba Semiconductor device having a second insulating layer which includes carbon or fluorine at a density lower than a first insulating layer
JP2000040740A (ja) * 1998-07-22 2000-02-08 Sony Corp 有機樹脂系絶縁膜を有する電子装置の製造方法
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6921980B2 (en) * 2001-02-16 2005-07-26 Sharp Kabushiki Kaisha Integrated semiconductor circuit including electronic component connected between different component connection portions
TW200633246A (en) * 2005-03-01 2006-09-16 Advanced Semiconductor Eng Semiconductor package having and optical device and the method of making the same
JP2007295008A (ja) * 2007-07-30 2007-11-08 Dainippon Printing Co Ltd 電子部品内蔵配線基板の製造方法
JP2008300636A (ja) * 2007-05-31 2008-12-11 Meiko:Kk プリント配線板及びその製造方法、並びに、このプリント配線板を用いた電子部品収容基板及びその製造方法
JP2009278050A (ja) * 2008-05-19 2009-11-26 Dainippon Printing Co Ltd 電子モジュール、配線板、電子モジュールの製造方法、配線板の製造方法
US20100171194A1 (en) * 2005-10-29 2010-07-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
TW201113992A (en) * 2009-10-07 2011-04-16 Xintec Inc Chip package and fabrication method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4053257B2 (ja) * 2001-06-14 2008-02-27 新光電気工業株式会社 半導体装置の製造方法
US7232754B2 (en) * 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
CN101414595B (zh) * 2007-10-18 2012-08-08 欣兴电子股份有限公司 封装基板及其制法
CN101577233B (zh) * 2008-05-05 2011-12-07 相丰科技股份有限公司 集成电路元件的封装结构及其制造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850102A (en) * 1996-04-03 1998-12-15 Kabushiki Kaisha Toshiba Semiconductor device having a second insulating layer which includes carbon or fluorine at a density lower than a first insulating layer
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP2000040740A (ja) * 1998-07-22 2000-02-08 Sony Corp 有機樹脂系絶縁膜を有する電子装置の製造方法
US6921980B2 (en) * 2001-02-16 2005-07-26 Sharp Kabushiki Kaisha Integrated semiconductor circuit including electronic component connected between different component connection portions
TW200633246A (en) * 2005-03-01 2006-09-16 Advanced Semiconductor Eng Semiconductor package having and optical device and the method of making the same
US20100171194A1 (en) * 2005-10-29 2010-07-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
JP2008300636A (ja) * 2007-05-31 2008-12-11 Meiko:Kk プリント配線板及びその製造方法、並びに、このプリント配線板を用いた電子部品収容基板及びその製造方法
JP2007295008A (ja) * 2007-07-30 2007-11-08 Dainippon Printing Co Ltd 電子部品内蔵配線基板の製造方法
JP2009278050A (ja) * 2008-05-19 2009-11-26 Dainippon Printing Co Ltd 電子モジュール、配線板、電子モジュールの製造方法、配線板の製造方法
TW201113992A (en) * 2009-10-07 2011-04-16 Xintec Inc Chip package and fabrication method thereof

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