TWI845109B - Non-volatile memory device - Google Patents

Abstract

A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.

Description

Non-volatile memory device

The present invention relates to a semiconductor device. More specifically, the present invention relates to a non-volatile memory device.

Since non-volatile memory can repeatedly perform operations such as storing, reading, and erasing data, and the stored data will not be lost after the non-volatile memory is turned off, non-volatile memory has been widely used in personal computers and electronic devices.

It is known that the structure of non-volatile memory has a stacked gate structure, including a tunneling oxide layer, a floating gate, a coupling dielectric layer, and a control gate sequentially disposed on a substrate. When programming or erasing operations are performed on such a flash memory element, appropriate voltages are applied to the source region, the drain region, and the control gate, respectively, so that electrons are injected into the floating gate, or electrons are pulled out of the floating gate.

In the programming and erasing operations of non-volatile memory, a larger gate-coupling ratio (GCR) between the floating gate and the control gate usually means a lower operating voltage required for operation, thus significantly improving the operating speed and efficiency of the flash memory. However, during the programming or erasing operation, electrons must flow through the tunnel oxide layer set under the floating gate to be injected into the floating gate or taken out of the floating gate. This process usually damages the structure of the tunnel oxide layer, thereby reducing the reliability of the memory device.

In order to improve the reliability of memory devices, an erase gate can be used and integrated into the memory device. By applying a positive voltage to the erase gate, the erase gate can pull electrons out of the floating gate. Therefore, since the electrons in the floating gate are pulled out by flowing through the tunnel oxide layer set on the floating gate, rather than flowing through the tunnel oxide layer set under the floating gate, the reliability of the memory device is further improved.

However, even if incorporating the erase gate into the memory element can successfully improve the reliability of the memory element, the misalignment of the erase gate usually causes a significant variation in the coupling ratio between the erase gate and the underlying floating gate, which increases the variation in the required erase voltage, thereby degrading the electrical consistency between memory elements.

As the demand for efficient memory devices increases, there remains a need to provide an improved memory device that can efficiently erase stored data.

The present invention provides a non-volatile memory device that can effectively erase stored data with improved electrical consistency.

According to some embodiments of the present disclosure, a non-volatile memory device is disclosed. The non-volatile memory device includes at least one memory cell, and at least one memory cell includes a substrate, an auxiliary gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The auxiliary gate structure is disposed on the substrate and includes a gate dielectric layer. The tunneling dielectric layer is disposed on the substrate on one side of the auxiliary gate structure. The floating gate is disposed on the tunneling dielectric layer and includes two first uppermost edges, two first sidewalls, and two second sidewalls. The two first uppermost edges are opposite to each other and arranged along a first direction. The two first side walls are opposite to each other and arranged along the first direction, and the two first side walls are respectively connected to the two first uppermost edges. The two second side walls are opposite to each other and arranged along the second direction different from the first direction. The upper gate structure covers the auxiliary gate structure and the floating gate, and at least one first uppermost edge of the floating gate is embedded in the upper gate structure. Part of the upper gate structure extends beyond the two second side walls of the floating gate in the second direction, and the said part of the upper gate structure is arranged on the substrate.

By using a non-volatile memory device according to the disclosed embodiment, even if an alignment error occurs between the upper gate structure and the floating gate thereunder, the change in the required voltage applied to the upper gate structure, such as the change in the erase voltage, will be reduced or even negligible.

In order to make the above features and advantages of the present disclosure easier to understand, the embodiments are described in detail below with reference to the drawings.

For those having ordinary knowledge in the art, the above and other purposes of the present disclosure will undoubtedly become apparent after reading the detailed description of the preferred embodiments shown in the following figures.

102: Isolation structure

110: First memory area

112: Second memory area

114: The third memory area

116: Fourth memory area

200: Lining

202: Gate dielectric layer

204: Auxiliary gate

206: Insulation layer

208: Sacrifice layer

210: Stack structure

211: Side wall

212: Isolation material layer

213: Side wall

214: Dielectric layer

216: Dielectric layer

218: Tunneling dielectric layer

220a: Patterned conductive layer

220a_2: Side wall

220b: Patterned conductive layer

220b_0: Top

220b_1: Inner surface

220b_2: External surface

220b_3: Side wall

221_1: Vertical part

221_2: Horizontal part

222: Source region

224: Floating gate

224a: floating gate

224a_0: Top

224a_1: Side wall

224a_2: Side wall

224b: floating gate

224b_1: Vertical section

224b_2: Horizontal part

225_0: Top

225_1: Inner surface

225_2: External surface

226a_1: First top edge

234: Upper gate dielectric layer

235: Upper gate pole

235_0: Top

236: Upper gate structure

238: Thin dielectric layer

239: Middle layer

239_0: Top

240:Intermediate structure

240a: Intermediate structure

240b: Intermediate structure

242: Drain area

260: Top dielectric layer

260_0: Top

262: Gap wall

270a: Conformal layer

270b: Stacking conformal layers

270b_1: Lower level

270b_2: Upper level

272a: Interstitial wall

272b: Interstitial wall

R1: Region

R2: Region

R3: Region

R4: Region

X: Direction

Y: Direction

Z: Direction

The purpose of the following figures is to make the present disclosure easier to understand, and these figures will be incorporated into and constitute part of the specification. The figures illustrate embodiments of the present disclosure, and together with the paragraphs of the implementation method, the working principle of the invention is explained.

Figure 1 is a schematic top view of a non-volatile memory device according to an embodiment of the present disclosure.

FIG. 2 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section lines A-A’, B-B’ and C-C’ of FIG. 1 according to some embodiments of the present disclosure, wherein the upper gate structure covers the floating gate and the intermediate structure.

FIG. 3 is an enlarged cross-sectional view of region R1 of the non-volatile memory element shown in FIG. 2 in some embodiments of the present disclosure.

FIG. 4 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section lines A-A’, B-B’ and C-C’ of FIG. 1 according to other embodiments of the present disclosure, wherein the top dielectric layer covers the floating gate.

FIG. 5 is an enlarged cross-sectional view of region R2 of the non-volatile memory element shown in FIG. 4 in some embodiments of the present disclosure.

FIG. 6 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section lines A-A’, B-B’ and C-C’ of FIG. 1 according to other embodiments of the present disclosure, wherein the floating gate is an L-type floating gate.

FIG. 7 is an enlarged cross-sectional view of region R3 of the non-volatile memory element shown in FIG. 6 in some embodiments of the present disclosure.

Figure 8 is a top view schematic diagram of a non-volatile memory device according to another embodiment of the present disclosure.

FIG. 9 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section lines A-A’, B-B’ and C-C’ of FIG. 8 according to some other embodiments of the present disclosure, wherein the source region is exposed from the middle structure.

FIG. 10 is an enlarged cross-sectional view of region R4 of the non-volatile memory element shown in FIG. 9 in some other embodiments of the present disclosure.

Figures 11 to 14 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 1 to 3 according to some embodiments of the present disclosure.

Figures 15 to 17 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 4 to 5 according to some embodiments of the present disclosure.

Figures 18 and 19 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 1 to 3 according to some other embodiments of the present disclosure.

Figures 20 and 21 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 4 and 5 according to some other embodiments of the present disclosure.

Figures 22 to 26 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 6 to 7 according to some embodiments of the present disclosure.

Figures 27 to 30 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 8 to 10 according to some embodiments of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "down", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. With the different orientations of the semiconductor device (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principle of the invention disclosed herein is defined by the scope of the patent application and can therefore also be applied to other embodiments. In addition, in order not to obscure the spirit of the present disclosure, certain details will be omitted, and these omitted details belong to the knowledge scope of a person with ordinary knowledge in the relevant technical field.

FIG. 1 is a top view of a non-volatile memory device according to an embodiment of the present disclosure. Referring to FIG. 1 , the non-volatile memory device may be a NOR flash memory device, which includes at least one memory cell, for example, four memory cells respectively accommodated in a first memory area 110, a second memory area 112, a third memory area 114, and a fourth memory area 116. The structures in the first memory area 110 and the second memory area 112 are mirror images of each other, and the structures in the third memory area 114 and the fourth memory area 116 are mirror images of each other. According to one embodiment of the present disclosure, the non-volatile memory device includes more than four memory cells, and these memory cells can be arranged in an array having a plurality of rows and columns.

Referring to FIG. 1, the non-volatile memory element includes a substrate 200 and an isolation structure 102. The substrate 200 may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The isolation structure 102 may be composed of an insulating material and is used to define an active region of the memory cell.

Each memory cell includes a source region 222 and a drain region 242 disposed in an active region defined by the isolation structure 102. The source region 222 and the drain region 242 may be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 242 is different from the conductivity type of the substrate 200, or from the conductivity type of a doped well (not shown) for accommodating the source region 222 and the drain region 242. The source region 222 may be disposed on one side of the active region, and the drain region 242 may be disposed on the other side of the active region. According to some embodiments of the present disclosure, the source region 222 is a continuous region extending along the Y direction and is shared by memory cells in the same row.

Each memory cell may further include a stacking structure disposed on the substrate 200 and adjacent to the drain region 242. The stacking structure may extend along the Y direction and be shared by the memory cells in the same row. The stacking structure includes an auxiliary gate 204, an insulating layer 206, and an upper gate structure 236, which are sequentially stacked upward along the Z direction. The auxiliary gate 204 may be composed of a conductive material such as polysilicon or metal, and the auxiliary gate 204 may serve as a word line configured to turn on/off the channel region of the memory cells disposed in the same row.

The isolation material layer 212 can be disposed on the side walls of the auxiliary gate 204 and the insulating layer 206 to insulate the auxiliary gate 204 from other conductive components. The isolation material layer 212 can be a single-layer, double-layer or multi-layer spacer disposed on each side wall of the auxiliary gate 204, but is not limited thereto.

Each memory cell also includes a floating gate 224 disposed on the substrate 200 and adjacent to the source region 222. Therefore, the floating gate 224 is disposed on one side of the auxiliary gate 204, and the drain region 242 is disposed on the other side of the auxiliary gate 204. The floating gate 224 is composed of a conductive material, such as polysilicon or other semiconductors. The floating gates 224 are separated from each other so that current cannot be directly transmitted between the floating gates 224. Since the floating gates 224 are separated from each other, each floating gate 224 can be independently programmed or erased to determine the state of each memory cell, such as state "1" or state "0".

The intermediate structure 240 is disposed in the gap between adjacent floating gates 224 to surround the circumference of the floating gates 224. According to different requirements, the intermediate structure 240 may include an insulating structure configured to prevent leakage current between adjacent floating gates 224, or the intermediate structure 240 may include a control gate structure configured to inject hot carriers (e.g., electrons) from the channel into the floating gate 224.

FIG. 2 is a cross-sectional schematic diagram of a non-volatile memory element corresponding to the section lines A-A’, B-B’ and C-C’ of FIG. 1 according to some embodiments of the present disclosure, wherein the upper gate structure covers the floating gate and the middle structure. Referring to the section line AA’ of FIG. 2, the drain region 242 is respectively disposed in the first memory region 110 and the second memory region 112. The source region 222 is disposed at the boundary between the first memory region 110 and the second memory region 112.

For the memory cell in the first memory region 110, the gate dielectric layer 202 is disposed between the substrate 200 and the auxiliary gate 204. By biasing the auxiliary gate 204 with a predetermined voltage, the carrier channel under the gate dielectric layer 202 can be turned on/off. The insulating layer 206 can be selectively disposed between the auxiliary gate 204 and the upper gate structure 236 to prevent leakage current therebetween.

The upper gate structure 236 includes an upper gate dielectric layer 234 and an upper gate 235 stacked in sequence. The upper gate dielectric layer 234 is a dielectric layer that allows electrons to pass through by a F-N tunneling mechanism (Fowler-Nordheim tunneling mechanism). The upper gate 235 can be composed of a conductive material, such as polysilicon or metal. The top surface of the upper gate structure 236 (corresponding to the top surface 235_0 of the upper gate 235) is higher than the top surface of the floating gate 224a. In addition, the upper gate structure 236 may further extend toward the auxiliary gate 204, so that a portion of the upper gate structure 236 may extend beyond the sidewall of the auxiliary gate 204, thereby covering the top surface 224a_0 of the floating gate 224a.

The floating gate 224a includes two opposing first sidewalls 224a_1 arranged along the X direction. The first sidewall 224a_1 may be a vertical or inclined sidewall, rather than a curved surface. The top surface 224a_0 of the floating gate 224a is a flat or slightly inclined surface, rather than a curved surface. It should be noted that the floating gate 224a shown in FIG. 2 may be a rectangular floating gate, because the outline of the floating gate 224a in the cross section AA' is similar to a rectangle.

The tunnel dielectric layer 218 is disposed on the substrate 200 and is at least located between the substrate 200 and the floating gate 224a. The material of the tunnel dielectric layer 218 is, for example, silicon oxide or other layers that allow hot electrons in the carrier channel to penetrate.

As described above, the intermediate structure 240a may include an insulating structure, such as an intermediate substrate structure, or the intermediate structure 240b may include a control gate structure, such as a control gate structure (the control gate structure may cover the sidewalls 224a_1, 224a_2 of the floating gate 224a to provide additional coupling to the floating gate). The intermediate structures 240a, 240b (e.g., the intermediate substrate structure or the control gate structure) include a thin dielectric layer 238 and an intermediate layer 239. The thin dielectric layer 238 is disposed on the first sidewall 224a_1 of the floating gate 224a, and the intermediate layer 239 is disposed in the gap between adjacent floating gates 224a. According to some embodiments of the present disclosure, the top surface 239_0 of the intermediate layer 239 of the intermediate structure 240a, 240b is lower than the top surface 224a_0 of the floating gate 224a.

According to different requirements, the upper gate structure 236 can be used as an erase gate structure, which is configured to pull electrons out of the floating gate 224a through the uppermost corner and/or uppermost edge of the floating gate 224a, or not only as an erase gate structure, but also as a control gate structure, which is configured to attract hot carriers from the carrier channel into the floating gate 224a. On the one hand, when the intermediate structure 240b is configured as a control gate structure, the upper gate structure 236 can only be used as an erase gate structure, rather than a control gate structure. On the other hand, when the intermediate structure 240a is configured as an insulating structure, the upper gate structure 236 can serve as an erase gate structure and a control gate structure.

Referring to the cross section BB' of FIG. 2, the auxiliary gate 204, the upper gate structure 236 and the intermediate structures 240a, 240b (e.g., the intermediate substrate structure or the control gate structure) are also disposed on the isolation structure 102. A portion of the intermediate structures 240a, 240b may be disposed between the upper gate structure 236 extending from the sidewall of the auxiliary gate 204 and the isolation structure 102, or the portion of the intermediate structure may be disposed between the upper gate structure 236 and the substrate 200.

Referring to the cross section CC' of FIG. 2, the floating gate 224a includes two opposite second sidewalls 224a_2 arranged along the Y direction. The second sidewall 224a_2 may be a vertical or inclined sidewall. The upper portion of the second sidewall 224a_2 of the floating gate 224a may be covered by the upper gate structure 236, and the lower portion of the second sidewall 224a_2 of the floating gate 224 may be covered by the intermediate structures 240a, 240b (e.g., the intermediate substrate structure or the control gate structure). According to some embodiments of the present disclosure, 60% to 95% of the surface area of each second sidewall 224a_2 is covered by the intermediate layer 239, so the contact area between the upper gate structure 236 and the second sidewall 224a_2 is small. In addition, due to the presence of the intermediate structures 240a and 240b, the bottom surface of the upper gate structure 236 extending beyond the second sidewall 224a_2 of the floating gate 224 can be separated from the isolation structure 102, the tunnel dielectric layer 218 and the substrate 200.

According to some embodiments of the present disclosure, the non-volatile memory element may also include other components, such as through holes, bit lines, interlayer dielectrics, etc., and the structure shown in FIG. 2 may be further modified according to actual needs.

FIG. 3 is an enlarged cross-sectional view of a region R1 of a non-volatile memory device such as that shown in FIG. 2 according to some embodiments of the present disclosure. Referring to FIG. 3 , the floating gate 224a includes two first uppermost edges 226a_1, which are opposite to each other and arranged along a first direction (e.g., X direction). By applying a bias to the upper gate structure 236, most of the electrons stored in the floating gate 224a can be pulled out through the first uppermost edge 226a_1 embedded in the upper gate structure 236. The first sidewall 224a_1 of the floating gate 224a is disposed along a first direction such as the X direction, and the first sidewall 224a_1 is respectively connected to the first uppermost edge 226a_1. The second sidewall (not shown) of the floating gate 224a is disposed along a second direction (such as the Y direction), and is covered by a dielectric intermediate layer 239 composed of a dielectric material, or by a conductive intermediate layer 239 serving as a control gate (i.e., a coupling gate). Since 65% to 95% of the second sidewall (i.e., the sidewall perpendicular to the Y direction) is covered by the middle layer 239, and the two first uppermost edges 226a_1 are both higher than the lowest bottom surface of the upper gate 235, even if there is an alignment deviation between the upper gate 235 and the floating gate 224a, the coupling ratio between the upper gate structure 236 and the floating gate 224a thereunder will not change significantly. Therefore, the electrical consistency between non-volatile memory components can be improved.

In the following paragraphs, other embodiments of the present disclosure are further described, and for the sake of brevity, only the main differences between the embodiments are described.

FIG. 4 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section line A-A', the section line B-B' and the section line C-C' of FIG. 1 according to other embodiments of the present disclosure, wherein the top dielectric layer covers the floating gate. Referring to the section AA' of FIG. 4, the structure shown in FIG. 4 is similar to the structure shown in FIG. 2, the main difference being that the top dielectric layer 260 is further disposed on the top surface 224a_0 of the floating gate 224a. In the section AA' of FIG. 4, the top dielectric layer 260 does not extend beyond the first sidewall 224a_1 of the floating gate 224a. In the cross section CC' of Figure 4, the top dielectric layer 260 does not extend beyond the second sidewall 224a_2 of the floating gate 224a.

FIG. 5 is an enlarged cross-sectional view of a region R2 of a non-volatile memory device according to some embodiments of the present disclosure, such as that shown in FIG. 4. Referring to FIG. 5, the first uppermost edge 226a_1 of the floating gate 224a is not covered by the top dielectric layer 260, so that at least one of the first uppermost edge 226a_1 of the floating gate 224a can still directly contact the upper gate structure 236. In other words, from a top view, the area of the top surface 260_0 of the top dielectric layer 260 is smaller than the area of the top surface 224a_0 of the floating gate 224a. Due to the presence of the top dielectric layer 260, part of the upper gate structure 236 disposed on the floating gate 224a is disposed away from the top surface 224a_0 of the floating gate 224a. Therefore, the coupling ratio caused by the gate structure 236 disposed on the top dielectric layer 260 can be reduced, thereby improving the electrical consistency between non-volatile memory elements.

FIG. 6 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section line A-A', the section line B-B' and the section line C-C' of FIG. 1 according to other embodiments of the present disclosure, wherein the floating gate is an L-type floating gate. Referring to the section AA' of FIG. 6, the structure shown in FIG. 6 is similar to the structure shown in FIG. 2, the main difference being that the floating gate 224b is an L-type floating gate including a vertical portion 224b_1 and a horizontal portion 224b_2. The vertical portion 224b_1 and the horizontal portion 224b_2 may have substantially the same thickness and composition. The top surface 225_0 of the vertical portion 224b_1 is higher than the top surface of the intermediate structure 240a, 240b (i.e., the intermediate substrate structure or the control gate structure), or higher than the top surface 239_0 of the intermediate layer 239. The horizontal portion 224b_2 is covered by the intermediate layer 239.

FIG. 7 is an enlarged cross-sectional view of a region R3 of a non-volatile memory device such as that shown in FIG. 6 according to some embodiments of the present disclosure. Referring to FIG. 7, a floating gate 224b includes an inner surface 225_1 and an outer surface 225_2 opposite to the inner surface 225_1. The outer surface 225_2 faces the intermediate structures 240a, 240b. A vertical portion 224b_1 of the floating gate 224b includes a top surface 225_0 and two opposite first uppermost edges 226a_1 disposed along a first direction (e.g., X direction). The width of the top surface 225_0 in the X direction is 1/20 to 1/3 of the width of the bottom surface of the floating gate 224b. One or both of the first uppermost edges 226a_1 may be covered by the upper gate structure 236. Because the width of the top surface 225_0 in the X direction is much smaller than the bottom width of the floating gate 224b, and 65% to 95% of the second sidewall (i.e., the sidewall perpendicular to the Y direction) of the floating gate 224b is covered by the intermediate layer 239, even if there is an alignment deviation between the upper gate 235 and the floating gate 224b, the coupling ratio between the upper gate structure 236 and the floating gate 224b thereunder will not change significantly. Therefore, the electrical consistency between non-volatile memory elements can be improved.

FIG. 8 is a top view schematic diagram of a non-volatile memory device of another embodiment of the present disclosure. Referring to FIG. 8, the structure shown in FIG. 8 is similar to the structure shown in FIG. 1, the main difference being that the floating gate 224 is an L-shaped floating gate instead of a rectangular floating gate along the section line AA', and the source region 222 of the non-volatile memory device is not covered by the intermediate structure 240. Therefore, the intermediate structure 240 in the first memory region 110 is separated from the intermediate structure 240 in the second memory region 112, and the intermediate structure 240 in the third memory region 114 is separated from the intermediate structure 240 in the fourth memory region 116.

FIG. 9 is a cross-sectional schematic diagram of a non-volatile memory device corresponding to the section lines A-A’, B-B’ and C-C’ of FIG. 8 according to some other embodiments of the present disclosure, wherein the source region is exposed from the intermediate structure. Referring to the section AA’ of FIG. 9, the floating gate 224b is an L-shaped floating gate similar to the floating gate 224b shown in FIG. 6. The top surface of the horizontal portion 224b_2 of the floating gate 224b is covered by the intermediate structures 240a and 240b, and the end of the horizontal portion 224b_2 is far away from the floating gate 224b, and the end is exposed from the intermediate structures 240a and 240b. In addition, the intermediate structures 240a and 240b have curved surfaces.

Referring to the cross section BB' of FIG. 9, a portion of the upper gate structure 236 covers the curved surface of the middle structure 240a, 240b, and thus has a curved bottom surface.

FIG. 10 is an enlarged cross-sectional view of region R4 of the non-volatile memory device shown in FIG. 9 according to some other embodiments of the present disclosure. Referring to FIG. 10, similar to the structure shown in FIG. 7, the vertical portion 224b_1 of the floating gate 224b includes a top surface 225_0 and two opposite first uppermost edges 226a_1 arranged along a first direction (e.g., X direction). The width of the top surface 225_0 in the X direction is 1/20 to 1/3 of the width of the bottom surface of the floating gate 224b. One or both of the first uppermost edges 226a_1 may be covered by the upper gate structure 236. In addition, the intermediate structures 240a and 240b not only cover the outer surface 225_2 of the floating gate 224b, but also cover the second sidewall (not shown) of the floating gate 224b arranged along the Y direction. According to some embodiments of the present disclosure, the topmost points of the intermediate structures 240a and 240b and the top surface 225_0 of the floating gate 224b can be substantially at the same height. Because the width of the top surface 225_0 in the X direction is much smaller than the bottom width of the floating gate 224b, and more than 95% of the outer surface 225_2 and more than 95% of the second sidewall (i.e., the sidewall perpendicular to the Y direction) of the floating gate 224b are covered by the intermediate structure 240a, 240b, even if there is an alignment deviation between the upper gate 235 and the floating gate 224b, the coupling ratio between the upper gate structure 236 and the floating gate 224b thereunder will not change significantly. Therefore, the electrical consistency between non-volatile memory elements can be improved.

Figures 11 to 14 are cross-sectional views of different stages of a method for manufacturing a non-volatile memory device in Figures 1 to 3 according to some embodiments of the present invention. In Figures 11 to 14, cross-section AA', cross-section BB' and cross-section CC' correspond to the section line A-A', section line B-B' and section line C-C' of Figure 1, respectively.

Referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 11, the structure formed in this manufacturing stage includes at least a substrate 200, at least one stacked structure 210, an isolation material layer 212, a tunnel dielectric layer 218 and a patterned conductive layer 220a.

According to some embodiments of the present disclosure, substrate 200 may be a semiconductor substrate having a suitable conductivity type, such as p-type or n-type. The composition of substrate 200 may include silicon, germanium, gallium nitride or other suitable semiconductor materials, but is not limited thereto.

At least one stacking structure 210 is on the substrate 200. For example, two stacking structures 210 are disposed on the substrate 200 and are laterally spaced apart from each other. Each stacking structure 210 includes a gate dielectric layer 202, an auxiliary gate 204, an insulating layer 206, and a sacrificial layer 208 stacked in sequence. Each stacking structure 210 includes a first sidewall 211 and a second sidewall 213, and the first sidewalls 211 of the stacking structures 210 face each other. The auxiliary gate 204 is composed of a conductive material, and the auxiliary gate 204 is configured to open/close a carrier channel in the substrate 200 under the auxiliary gate 204 when a suitable voltage is applied. The insulating layer 206 is composed of an insulating material, such as silicon oxide or silicon oxynitride, but not limited thereto, and is used to electrically isolate the auxiliary gate 204 from the layers disposed on the auxiliary gate 204. The sacrificial layer 208 is the topmost layer in the stacked structure 210, which is a temporary layer configured to be removed before a subsequent process of forming a gate structure (e.g., an upper gate structure) on the auxiliary gate 204.

The isolation material layer 212 is formed on the sidewalls 211 and 213 of the stacked structure 210. The material of the isolation material layer 212 is, for example, silicon oxide/silicon nitride/silicon oxide or silicon nitride/silicon oxide. The method for forming the isolation material layer 212 includes, for example, first sequentially forming a dielectric layer 214 and a dielectric layer 216 covering each stacked structure 210 on the substrate 200, and then removing a portion of the dielectric layer 214 and the dielectric layer 216 to form the isolation material layer 212 on the sidewalls of each stacked structure 210. The material of the dielectric layer 214 is, for example, silicon nitride, and the material of the dielectric layer 216 is, for example, silicon oxide. The method for forming the dielectric layer 214 and the dielectric layer 216 is, for example, chemical vapor deposition. The method for removing part of the dielectric layer 214 and the dielectric layer 216 is, for example, anisotropic etching.

The tunnel dielectric layer 218 is formed on the substrate 200 at least between the stacked structures 210, or further formed on the substrate 200 on both sides of the stacked structure 210. The material of the tunnel dielectric layer 218 is, for example, silicon oxide, or other layers that allow hot electrons to penetrate through the tunneling effect. The formation method of the tunnel dielectric layer 218 is, for example, thermal oxidation or deposition, but is not limited thereto.

Referring to the cross section AA' of FIG. 11, the patterned conductive layer 220a is formed in the gap between the stacked structures 210 and covers the sidewalls 211 of each stacked structure 210. The method of forming the patterned conductive layer 220a may include the following steps: First, a conductive layer (not shown) is formed on the substrate 200, and the material of the conductive layer is, for example, doped polysilicon, polycrystalline silicide or other suitable conductive materials. When the material of the conductive layer is doped polysilicon, its formation method includes, for example, after forming an undoped polysilicon layer by chemical vapor deposition, performing an ion implantation step; or performing a chemical vapor deposition method using an in-situ dopant implantation method. Then, an etching process, such as an isotropic etching process or an etch-back process, is performed to etch the conductive layer. Therefore, the conductive layer can be patterned to form a plurality of conductive blocks (not shown) arranged along the X direction. In this manufacturing stage, the conductive blocks cover the sidewalls 211 and 213 of each stacked structure 210. Then, the conductive block disposed on the sidewall 213 adjacent to the stacking structure 210 is removed by lithography and etching processes. In this way, only the patterned conductive layer 220a disposed on the first sidewall 211 of the stacking structure 210 is retained. In addition, the patterned conductive layer 220a disposed on the first sidewall 211 of the stacking structure 210 may have a rectangular outline from a top view. The height of the patterned conductive layer 220a may be appropriately controlled by performing an etching back process.

Referring to the cross section BB' of FIG. 11, the patterned conductive layer does not exist in a predetermined area on the substrate 200. Referring to the cross section CC' of FIG. 11, the patterned conductive layer 220a may have a vertical or inclined side wall 220a_2.

FIG. 12 is a cross-sectional schematic diagram of some embodiments of the present disclosure at a manufacturing stage after FIG. 11, wherein a spacer is formed on a patterned conductive layer. After the structure shown in FIG. 11 is manufactured, a plurality of spacers 262 composed of a dielectric material are formed to cover the top surface of the patterned conductive layer 220a and the sidewalls 211, 213 of the stacked structure 210.

FIG. 13 is a cross-sectional schematic diagram of some embodiments of the present disclosure at a manufacturing stage subsequent to FIG. 12, in which a floating gate is formed. After the structure shown in FIG. 12 is manufactured, an etching process is performed on the patterned conductive layer using the spacer 262 as an etching mask. Therefore, the patterned conductive layer is further patterned to form a plurality of floating gates 224a adjacent to the first sidewall 211 of the stacked structure 210. Thereafter, a source region 222 is formed in the substrate 200 between two adjacent floating gates 224a. The method of forming the source region 222 includes, for example, performing an ion implantation process using the spacer 262 as an etching mask. Depending on the requirements of the device, the implanted dopant can be n-type or p-type. The source region 222 can be considered a shared source region because the source region 222 is shared by two adjacent memory cells. Afterwards, the spacer 262 can be stripped.

FIG. 14 is a cross-sectional schematic diagram of some embodiments of the present disclosure at a manufacturing stage subsequent to FIG. 13, wherein an intermediate structure is formed in a gap between two adjacent floating gates. After the structure shown in FIG. 13 is manufactured, referring to the cross section AA' of FIG. 14, intermediate structures 240a, 240b can be formed in the gap between two adjacent floating gates 224a. The intermediate structures 240a, 240b include a thin dielectric layer 238 and an intermediate layer 239. The thin dielectric layer 238 is disposed on the first sidewall 224a_1 of the floating gate 224a, and the intermediate layer 239 is disposed in the gap between the adjacent floating gates 224a. The thickness of the thin dielectric layer 238 (i.e., in the X direction) is less than the thickness of the intermediate layer 239 (i.e., in the Z direction). For example, the thickness ratio of the thin dielectric layer 238 to the intermediate layer 239 is 0.01 to 0.2. According to some embodiments of the present disclosure, the top surface of the intermediate structure 240a, 240b is lower than the top surface 224a_0 of the floating gate 224a.

Referring to the cross section CC' of FIG. 14, the floating gate 224a includes two opposite second sidewalls 224a_2 arranged along the Y direction. Each second sidewall 224a_2 may be a vertical or inclined sidewall. The upper portion of the second sidewall 224a_2 of the floating gate 224a may be covered by an upper gate structure formed subsequently, and the lower portion of the second sidewall 224a_2 of the floating gate 224 is covered by the intermediate structures 240a, 240b (e.g., an intermediate substrate structure or a control gate structure). According to some embodiments of the present disclosure, 60% to 95% of the surface area of each second sidewall 224a_2 is covered by the intermediate layer 239, so the contact area between the upper gate structure and the second sidewall 224a_2 formed subsequently is small. In addition, due to the presence of the intermediate structure 240, the bottom surface of the upper gate structure 236 extending beyond the second sidewall 224a_2 of the floating gate 224 can be separated from the isolation structure 102, the tunnel dielectric layer 218 and the substrate 200.

Afterwards, the upper gate structure and other components can be formed to obtain a non-volatile memory device similar to the structure shown in Figures 1 to 3.

Figures 15 to 17 are cross-sectional views of various stages of the manufacturing method of the non-volatile memory device of Figures 4 to 5 for manufacturing some embodiments of the present disclosure. In Figures 15 to 17, the cross-section AA', the cross-section BB' and the cross-section CC' correspond to the cross-section line A-A', the cross-section line B-B' and the cross-section line C-C' of Figure 1, respectively. In addition, since the manufacturing process of the embodiments shown in Figures 15 to 17 is similar to the manufacturing process of the embodiments shown in Figures 11 to 14, for the sake of brevity, only the main differences between the embodiments are described.

Referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 15, the structure formed at this manufacturing stage is similar to the structure shown in FIG. 11, with the main difference that the top dielectric layer 260 is disposed on the patterned conductive layer 220a. Because the top dielectric layer 260 is formed after the conductive layer is fully deposited as shown in FIG. 11 and before the conductive layer is patterned to form a conductive block (not shown), the sidewalls of the patterned conductive layer 220a are not covered by the top dielectric layer 260. The thickness of the top dielectric layer 260 is 1/3 to 1/10 of the thickness of the patterned conductive layer 220a.

FIG. 16 is a cross-sectional schematic diagram of some embodiments of the present disclosure at a manufacturing stage after FIG. 15, wherein the spacers are formed on the patterned conductive layer. After the structure shown in FIG. 15 is manufactured, a plurality of spacers 262 composed of dielectric material are formed to cover the top surface of the top dielectric layer 260 and the sidewalls 211, 213 of the stacked structure 210.

Referring to the cross-sections AA', BB' and CC' of FIG. 17, the structure formed at this manufacturing stage is similar to the structure shown in FIG. 13, with the main difference being that the top dielectric layer 260 is disposed between the spacer 262 and the floating gate 224a. Then, the spacer 262 can be stripped. Thereafter, the upper gate structure and other components can be formed to obtain a non-volatile memory element similar to the structure shown in FIGS. 4 to 5.

Figures 18 and 19 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 1 to 3 according to some other embodiments of the present invention. The manufacturing process shown in Figures 18 to 19 is similar to the manufacturing process shown in Figures 11 to 14. For the sake of brevity, only the main differences between the embodiments are described.

Referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 18, the structure formed at this manufacturing stage is similar to the structure shown in FIG. 11, the main difference being that the additional stacking structure 210 extending along the Y direction is disposed on the substrate 200 between two adjacent stacking structures 210. Due to the presence of the additional stacking structure 210, the additional stacking structure 210 can be used to prevent the patterned conductive layer 220a from being formed in the area already occupied by the additional stacking structure 210.

FIG. 19 is a cross-sectional schematic diagram of some other embodiments of the present disclosure at a manufacturing stage after FIG. 18. After manufacturing the structure shown in FIG. 18, the patterned conductive layer disposed on the second sidewall 213 of the stacked structure 210 is removed to form a floating gate 224a.

Afterwards, the intermediate structures 240a, 240b shown in FIG. 2 may be fabricated to replace the additional stacked structure 210 disposed between the two adjacent floating gates 224a. Then, the upper gate structure and other components may be formed to obtain a non-volatile memory device similar to the structure shown in FIGS. 1 to 3.

Figures 20 and 21 are cross-sectional views of different stages of a method for manufacturing the non-volatile memory device of Figures 4 and 5 according to some other embodiments of the present disclosure. The manufacturing process shown in Figures 20 and 21 is similar to the manufacturing process shown in Figures 18 and 19. For the sake of brevity, only the main differences between the embodiments are described.

Referring to the cross-sections AA', BB' and CC' of FIG. 20, the structure formed at this manufacturing stage is similar to the structure shown in FIG. 18, with the main difference being that the top dielectric layer 260 is disposed on the patterned conductive layer 220a. Because the top dielectric layer 260 is formed after the overall deposition of the conductive layer (not shown) and before the conductive layer is patterned to form a conductive block (not shown), the sidewalls of the patterned conductive layer 220a are not covered by the top dielectric layer 260. The thickness of the top dielectric layer 260 is 1/3 to 1/10 of the thickness of the patterned conductive layer 220a.

FIG. 21 is a cross-sectional schematic diagram of some embodiments of the present disclosure at a manufacturing stage after FIG. 20. After manufacturing the structure shown in FIG. 20, the patterned conductive layer 220a disposed on the second sidewall 213 of the stacked structure 210 is stripped to form a floating gate 224a.

Afterwards, the additional stack structure 210 can be replaced by the intermediate structures 240a, 240b shown in FIG. 4. Then, the upper gate structure and other components can be formed to obtain a non-volatile memory device similar to the structure shown in FIGS. 4 to 5.

Figures 22 to 26 are cross-sectional views of different stages of the manufacturing method of the non-volatile memory device of Figures 6 to 7 used in some embodiments of the present disclosure. In Figures 22 to 26, the cross-section AA', the cross-section BB' and the cross-section CC' correspond to the cross-section line A-A', the cross-section line B-B' and the cross-section line C-C' of Figure 1, respectively. In addition, the manufacturing process shown in Figures 22 to 26 can be regarded as derived from the manufacturing process shown in Figures 11 to 14. For the sake of brevity, only the main differences between the embodiments are described.

Referring to the cross sections AA', BB' and CC' of FIG. 22, a plurality of patterned conductive layers 220b are formed on the substrate 200. In the cross section AA' of FIG. 22, the patterned conductive layer 220b is a continuous layer extending in the X direction and covering the stacked structure 210. The patterned conductive layer 220b includes an inner surface 220b_1 and an outer surface 220b_2 opposite to each other. In the cross section BB' of FIG. 22, no patterned conductive layer 220b exists. Therefore, from a top view, as shown in FIG. 8, each patterned conductive layer 220b is strip-shaped and extends in the X direction, and the patterned conductive layers 220b are separated from each other along the Y direction. Then, after forming the patterned conductive layer 220b, a full deposition is performed to form a conformal layer 270a covering the patterned conductive layer 220b and the substrate 200. In the cross section CC' of FIG. 22, the sidewall 220b_3 of the patterned conductive layer 220b is covered by the conformal layer 270a.

Then, referring to the cross sections AA', BB' and CC' of FIG. 23, the conformal layer 270a is etched by an anisotropic etching process, thereby forming a spacer 272a on the side walls 211 and 213 of the stacked structure 210. In the cross section CC' of FIG. 22, the side wall of the patterned conductive layer 220b is covered by the spacer 272a. The spacer 272a in this embodiment can be formed without performing any lithography process.

Thereafter, referring to the cross section AA' of FIG. 24, the spacer 272a is used as an etching mask to etch the patterned conductive layer, thereby forming an L-shaped patterned conductive layer on the sidewalls 211 and 213 of the stacked structure 210. Each L-shaped patterned conductive layer includes a vertical portion 221_1 and a horizontal portion 221_2. By using the spacer 272a as an etching mask, no additional lithography process is required to define the contour of the L-shaped patterned conductive layer. Then, a source region 222 is formed in the substrate 200, and the source region 222 is disposed between two adjacent spacers 272a on the first sidewall 211 of the stacked structure 210.

Afterwards, referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 25, the spacer and the sacrificial layer are removed. In this way, the top surface 220b_0 of the vertical portion 221_1 of the patterned conductive layer 220b can protrude from the top surface of the remaining stacked structure 210. In addition, in the cross-section CC' of FIG. 25, the side wall 220b_3 of the patterned conductive layer 220b is exposed.

Afterwards, referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 26, the patterned conductive layer disposed on the second sidewall 213 adjacent to the stacking structure 210 is etched by performing lithography and etching processes. Therefore, the floating gate 224b is formed on the first sidewall 211 of the stacking structure 210. Then, the intermediate structures 240a and 240b are formed in the gap between the two adjacent stacking structures 210. In the cross-section AA' and the cross-section CC', the height of the intermediate structures 240a and 240b can be appropriately controlled to cover 65% to 95% of the sidewall of the floating gate 224b.

Afterwards, the upper gate structure and other components can be formed to obtain a non-volatile memory device similar to the structure shown in Figures 6 to 7.

Figures 27 to 30 are cross-sectional views of different stages of the manufacturing method of the non-volatile memory device of Figures 8 to 10 used in some embodiments of the present disclosure. In Figures 27 to 30, the cross-section AA', the cross-section BB' and the cross-section CC' correspond to the cross-section line A-A', the cross-section line B-B' and the cross-section line C-C' of Figure 8, respectively. In addition, since the manufacturing process of the embodiments shown in Figures 27 to 30 is similar to the manufacturing process of the embodiments shown in Figures 22 to 26, for the sake of brevity, only the main differences between the embodiments are described.

Referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 27, the structure formed in this manufacturing stage is similar to the structure shown in FIG. 22, the main difference being that the stacked conformal layer 270b including the lower layer 270b_1 and the upper layer 270b_2 is used to replace the conformal layer 270a shown in FIG. 22. According to some embodiments of the present disclosure, the lower layer 270b_1 is a composite dielectric layer including silicon oxide/silicon nitride/silicon oxide, but not limited thereto. The upper layer 270b_2 is a conductive layer including polysilicon or metal, but not limited thereto.

Then, referring to the cross sections AA', BB' and CC' of FIG. 28, the conformal layer 270b is etched by an anisotropic etching process, thereby forming a spacer 272b on the side walls 211 and 213 of the stacked structure 210. In the cross section CC' of FIG. 28, the side wall 220b_3 of the patterned conductive layer 220b is covered by the spacer 272b. The spacer 272b in this embodiment can be formed without performing an additional lithography process.

Thereafter, referring to the cross section AA' of FIG. 29, the spacer 272b is used as an etching mask to etch the patterned conductive layer, thereby forming an L-shaped patterned conductive layer on the sidewalls 211 and 213 of the stacked structure 210. Each L-shaped patterned conductive layer includes a vertical portion 221_1 and a horizontal portion 221_2. By using the spacer 272b as an etching mask, no additional lithography process is required to define the contour of the L-shaped patterned conductive layer. Then, a source region 222 is formed in the substrate 200, and the source region 222 is located between two adjacent spacers 272b on the sidewall 211 of the stacked structure 210.

Thereafter, referring to the cross-section AA', cross-section BB' and cross-section CC' of FIG. 26, the patterned conductive layer and the spacer disposed adjacent to the second sidewall 213 of the stacking structure 210 are etched by performing lithography and etching processes. Therefore, the floating gate 224b and the intermediate structures 240a, 240b are formed on the first sidewall 211 of the stacking structure 210. In other words, the intermediate structures 240a, 240b are formed by the original stacking conformal layer 270a, as shown in FIG. 27. In the cross-section AA' and the cross-section CC', the height of the intermediate structures 240a, 240b can be appropriately controlled to cover 65% to 95% of the sidewall of the floating gate 224b.

Afterwards, the upper gate structure and other components can be formed to obtain a non-volatile memory device similar to the structure shown in Figures 8 to 10.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

102: Isolation structure

110: First memory area

112: Second memory area

200: Lining

202: Gate dielectric layer

204: Auxiliary gate

206: Insulation layer

218: Tunneling dielectric layer

222: Source region

224a_1: Side wall

224a_2: Side wall

224b: floating gate

224b_1: Vertical section

224b_2: Horizontal part

234: Upper gate dielectric layer

235: Upper gate pole

236: Upper gate structure

238: Thin dielectric layer

239: Middle layer

239_0: Top

240a: Intermediate structure

240b: Intermediate structure

242: Drain area

R3: Region

Claims (21)

A non-volatile memory element includes at least one memory cell, wherein the at least one memory cell includes: a substrate; an auxiliary gate structure, disposed on the substrate and including a gate dielectric layer; a tunnel dielectric layer, disposed on the substrate on one side of the auxiliary gate structure; a floating gate, disposed on the tunnel dielectric layer and including: two first uppermost edges, opposite to each other and arranged along a first direction; two first side walls, opposite to each other and arranged along the first direction, wherein the two first side walls are respectively connected to the two first uppermost edges; and two second side walls, opposite to each other and arranged along the first direction. Arranged in a second direction, wherein the second direction is different from the first direction; an upper gate structure, covering the auxiliary gate structure and the floating gate, wherein at least one of the two first uppermost edges of the floating gate is embedded in the upper gate structure, wherein a portion of the upper gate structure extends beyond the two second side walls of the floating gate in the second direction, and the two second side walls are covered by an intermediate structure, wherein the portion of the upper gate structure is disposed on the substrate, and the intermediate structure is disposed between the portion of the upper gate structure and the substrate. A non-volatile memory device as described in item 1 of the patent application, wherein one of the first side walls of the floating gate faces the auxiliary gate structure, and the first side wall facing the auxiliary gate structure is covered by the auxiliary gate structure. A non-volatile memory device as described in item 2 of the patent application, wherein the other of the first side walls is opposite to the auxiliary gate structure, and the first side wall opposite to the auxiliary gate structure is a vertical or inclined side wall. A non-volatile memory device as described in item 1 of the patent application, wherein the two first uppermost edges of the floating gate are higher than the top surface of the auxiliary gate structure. A non-volatile memory device as described in item 1 of the patent application, wherein the bottom surface of the portion of the upper gate structure disposed on the substrate is lower than the two first uppermost edges of the floating gate. As described in item 1 of the patent application scope, the non-volatile memory element, wherein the at least one memory unit further includes a control gate structure, and a portion of the control gate structure covers the two second side walls of the floating gate. A non-volatile memory device as described in item 6 of the patent application, wherein the portion of the control gate structure is covered by the portion of the upper gate structure extending beyond the two second side walls of the floating gate. A non-volatile memory device as described in item 6 of the patent application, wherein the top surface of the control gate structure is lower than the top surface of the upper gate structure. A non-volatile memory device as described in Item 8 of the patent application, wherein the top surface of the control gate structure is covered by the upper gate structure. A non-volatile memory device as described in item 6 of the patent application, wherein the top surface of the control gate structure is lower than the two first uppermost edges. As described in item 1 of the patent application scope, the at least one memory unit further includes a top dielectric layer disposed on the floating gate, wherein the top surface of the top dielectric layer is covered by the upper gate structure. A non-volatile memory device as described in item 11 of the patent application, wherein the area of the top surface of the top dielectric layer is smaller than the area of the top surface of the floating gate. As described in item 1 of the patent application scope, the non-volatile memory element, wherein the floating gate further includes a vertical portion and a horizontal portion, wherein the top surface of the vertical portion is higher than the top surface of the horizontal portion. A non-volatile memory device as described in claim 13, wherein the vertical portion of the floating gate includes the two first uppermost edges. A non-volatile memory device as described in item 13 of the patent application, wherein the at least one memory unit further includes a control gate structure covering the top surface of the horizontal portion of the floating gate. As described in item 1 of the patent application scope, the at least one memory cell includes a first memory cell and a second memory cell, the first memory cell and the second memory cell each include the auxiliary gate structure and the floating gate, and the non-volatile memory cell further includes a source region, the source region is shared by the first memory cell and the second memory cell, and the source region is covered by the upper gate structure. A non-volatile memory device as described in claim 16, wherein the first memory unit and the second memory unit present a mirror image to each other. A non-volatile memory element as described in item 16 of the patent application, wherein the upper gate structure fills the gap between the floating gate of the first memory unit and the floating gate of the second memory unit. The non-volatile memory element as described in item 16 of the patent application scope further includes a control gate structure shared by the first memory unit and the second memory unit, wherein the control gate structure covers the source region. As described in item 19 of the patent application, a portion of the control gate structure covers the two second side walls of each floating gate, and the portion of the control gate structure is disposed between the upper gate structure and the substrate. The non-volatile memory element as described in item 19 of the patent application further includes an isolation structure disposed in the substrate, wherein the portion of the upper gate structure extending beyond the two second side walls of the floating gate is disposed on the isolation structure.

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