TWI605572B - Non-volatile memory and manufacturing method thereof - Google Patents

Description

Non-volatile memory and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a non-volatile memory and a method of fabricating the same.

Non-volatile memory has been widely used in personal computers and electronic devices because it has the advantages of allowing data to be stored, read, erased, etc., and the stored data does not disappear after power-off.

A typical non-volatile memory is designed to have a stacked gate-Gate structure including a tunneling oxide layer, a floating gate, and a gate dielectric layer sequentially disposed on the substrate. And control gate (Control Gate). When programming or erasing the flash memory device, apply appropriate voltages to the source region, the drain region, and the control gate to inject electrons into the polysilicon floating gate or to remove electrons from the polysilicon. Pull out in the floating gate.

In the operation of non-volatile memory, the larger the Gate-Coupling Ratio (GCR) between the floating gate and the control gate, the lower the operating voltage required for its operation will be. The operating speed and efficiency of flash memory will be greatly improved. The method of increasing the gate coupling ratio includes increasing the floating gate and controlling The overlap area between the gates, the thickness of the dielectric layer between the floating gate and the control gate, and the dielectric constant of the dielectric layer between the floating gate and the control gate (Dielectric Constant; k) and so on.

However, as integrated circuits are moving toward miniaturized components with higher degree of accumulation, it is necessary to reduce the memory cell size of non-volatile memory to increase its accumulation. Wherein, reducing the size of the memory cell can be achieved by reducing the gate length of the memory cell and the spacing of the bit lines. However, the smaller the gate length shortens the channel length under the tunneling oxide layer, which is likely to cause abnormal electrical penetration between the drain and the source, which will seriously affect the memory cell. Electrical performance. Moreover, when the memory cells are programmed and erased, the electrons repeatedly traverse the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in a decrease in the reliability of the memory device.

The present invention provides a non-volatile memory and a method of fabricating the same that can operate at a low operating voltage, thereby increasing the reliability of the semiconductor component.

The present invention provides a non-volatile memory and a method of manufacturing the same, which can improve the degree of integration of components.

The invention provides a non-volatile memory having a first memory cell disposed on a substrate. The first memory cell has a stacked gate structure, a floating gate, a tunneling dielectric layer, an erase gate dielectric layer, an auxiliary gate dielectric layer, a source region, a drain region, a control gate, and a gate dielectric The electrical layer, wherein the stacked gate structure has a gate dielectric layer, an auxiliary gate, an insulating layer, and an erase gate sequentially disposed on the substrate. Floating gate is set at The sidewalls of the first side of the gate structure are stacked, and the top of the floating gate has a corner portion, and the erase gate covers the corner portion. A tunneling dielectric layer is disposed between the floating gate and the substrate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The auxiliary gate dielectric layer is disposed between the auxiliary gate and the floating gate. The source region and the drain region are respectively disposed in the substrate on both sides of the stacked gate structure and the floating gate, wherein the source region is adjacent to the floating gate, and the drain region is adjacent to the second side of the stacked gate structure, first The side is opposite the second side. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate and between the control gate and the erase gate.

In an embodiment of the invention, the non-volatile memory further has a second memory cell. The second memory cell is disposed on the substrate, and the structure of the second memory cell is the same as the structure of the first memory cell, and the second memory cell is mirrored with the first memory cell to share the source region or the drain region.

In an embodiment of the invention, the first memory cell shares a control gate with the second memory cell, and the control gate fills an opening between the first memory cell and the second memory cell.

In an embodiment of the invention, the non-volatile memory further has a third memory cell. The third memory cell is disposed on the substrate, and the structure of the third memory cell is the same as that of the first memory cell, sharing the source region, the auxiliary gate, the erase gate, and the control gate, and the control gate is filled Between a memory cell and a third memory cell.

In an embodiment of the invention, the tunneling dielectric layer is further disposed between the control gate and the source region.

In an embodiment of the invention, the material of the auxiliary gate dielectric layer includes Cerium oxide / tantalum nitride, tantalum oxide / tantalum nitride / tantalum oxide or tantalum oxide.

In an embodiment of the invention, the material of the insulating layer comprises yttrium oxide. The material of the inter-gate dielectric layer includes yttria/tantalum nitride/yttria or tantalum nitride/yttria or other high dielectric constant materials (dielectric constant k>4).

In an embodiment of the invention, the material of the tunneling dielectric layer comprises yttrium oxide, and the thickness of the tunneling dielectric layer is between 60 angstroms and 200 angstroms.

In an embodiment of the invention, the material of the gate dielectric layer comprises yttrium oxide, and the thickness of the thyristor layer is less than or equal to the thickness of the tunneling dielectric layer. The material of the eraser dielectric layer includes yttrium oxide, and the thickness of the eraser dielectric layer is between 100 angstroms and 180 angstroms.

In an embodiment of the invention, the angle of the corner portion of the floating gate is less than or equal to 90 degrees.

The present invention provides a method of producing a non-volatile memory comprising the following steps. First, a substrate is provided. Next, at least two stacked structures are formed on the substrate, and each stacked structure sequentially includes a gate dielectric layer, an auxiliary gate, an insulating layer, and a sacrificial layer from the substrate. Then, an auxiliary gate dielectric layer is formed on sidewalls of the stacked structure to form a tunneling dielectric layer on the substrate between the stacked structures. A floating gate is formed on a sidewall of the first side of the stacked structure, wherein a top of the floating gate has a corner portion adjacent to the sacrificial layer. A layer of material is formed on the substrate to fill the gap between the stacked structures. After removing the sacrificial layer, a portion of the material layer, a portion of the insulating layer, and a portion of the auxiliary gate dielectric layer are removed to form an opening that exposes at least the corner portion of the floating gate. An eraser dielectric layer is formed on at least a corner portion of the floating gate. Forming an erase gate filling the opening on the substrate, The corner portion of the gate covered floating gate is erased. The material layer is removed, and a dielectric layer between the gates is formed on the floating gate and the erase gate. A control gate is formed on the floating gate.

In an embodiment of the invention, the step of forming a floating gate on a sidewall of the first side of the stacked structure includes: forming a conductor spacer on a sidewall of the first side of the stacked structure; and patterning the conductor spacer to form Floating gate. In an embodiment of the invention, the step of forming a conductor spacer on the sidewall of the first side of the stacked structure includes: forming a conductor layer on the substrate; and performing an anisotropic etching process on the conductor layer.

In an embodiment of the invention, the method for fabricating the non-volatile memory further includes: forming a source region in a substrate between the conductor spacers; and forming a drain in the substrate on the second side of the stacked structure The first side is opposite to the second side.

In the non-volatile memory of the present invention and the method of manufacturing the same, the two memory cells adjacent in the X direction (row direction) have the same structure and are, for example, mirrored, share the source region or the drain region, and share the control gate. . The two memory cells adjacent in the Y direction (column direction) have the same structure, sharing the source region, the auxiliary gate (word line), the erase gate, and the control gate. Therefore, the degree of integration of components can be improved.

In the non-volatile memory of the present invention and the method of manufacturing the same, the auxiliary gate is disposed in parallel with the erase gate, so that the degree of integration of the elements can be improved.

In the non-volatile memory of the present invention, the thickness of the gate dielectric layer under the auxiliary gate is relatively thin, and when operating the memory cell, a smaller voltage can be used to turn on/off the channel region under the auxiliary gate, that is, Reduce the operating voltage.

In the non-volatile memory of the present invention and the method of manufacturing the same, the control gate covers the floating gate, and the area between the control gate and the floating gate can be increased, and Increased coupling ratio of memory components.

In the non-volatile memory of the present invention and the method of manufacturing the same, since the floating gate is provided with a corner portion, the erase gate covers the corner portion. The angle of the corner portion is less than or equal to 90 degrees, and the electric field is concentrated by the corner portion, the erase voltage can be lowered, and the electrons can be efficiently pulled out from the floating gate to increase the speed of erasing the data.

The above described features and advantages of the invention will be apparent from the following description.

100, 200‧‧‧ base

102‧‧‧Isolation structure

104‧‧‧Active Area

110, 112, 114, 116, MC‧‧‧ Recall

120‧‧‧Stack gate structure

122‧‧‧gate dielectric layer

124‧‧‧Auxiliary gate

126‧‧‧Insulation

128, 236‧‧‧ erasing the gate

130‧‧‧Auxiliary gate dielectric layer

132, 234‧‧‧ Wipe the gate dielectric layer

140, 224, FG0, FG1‧‧‧ floating gate

141, 226‧‧‧ corner

142, 218‧‧‧ tunneling dielectric layer

146, 222‧‧‧ source area

148, 242‧‧ ‧ bungee area

150, 240‧‧‧Control gate

152, 238‧‧‧ Inter-gate dielectric layer

160, 244‧‧ ‧ interlayer insulation

162, 246‧‧ ‧ plug

164, 248‧‧‧ bit line

202, 214, 216‧‧ dielectric layers

204‧‧‧Conductor layer

206‧‧‧Insulation

208‧‧‧sacrificial layer

210‧‧‧Stack structure

212‧‧‧Separation material layer

220‧‧‧ conductor spacer

228‧‧‧Material layer

230, 232‧‧‧ openings

1A is a top view of a non-volatile memory in accordance with an embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

2A to FIG. 2I are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to an embodiment of the invention.

Fig. 3A is a schematic diagram showing an example of a program operation of a memory cell.

Fig. 3B is a schematic diagram showing an example of an erase operation on a memory cell.

Fig. 3C is a schematic diagram showing an example of a reading operation on a memory cell.

1A is a top view of a non-volatile memory in accordance with an embodiment of the present invention. FIG. 1B is a non-volatile according to an embodiment of the invention. Schematic diagram of the profile of sexual memory. FIG. 1B is a cross-sectional view taken along line AA' of FIG. 1A.

Referring to FIG. 1A and FIG. 1B, the non-volatile memory includes a plurality of memory cells MC. These memory cells MC are arranged in a row/column array.

The non-volatile memory is disposed on the substrate 100. A plurality of isolation structures 102 regularly arranged in the substrate 100 are provided, for example, to define an active region 104 having a lattice shape. The isolation structure 102 is, for example, a shallow trench isolation structure.

Each memory cell MC includes a stacked gate structure 120, an auxiliary gate dielectric layer 130, an erase gate dielectric layer 132, a floating gate 140, a tunneling dielectric layer 142, a source region 146, a drain region 148, and control. Gate 150 and gate dielectric layer 152. In addition, the substrate 100 further has an interlayer insulating layer 160, a plug 162 and a bit line 164.

The stacked gate structure 120 is sequentially formed from the substrate 100 by a gate dielectric layer 122, an auxiliary gate (word line) 124, an insulating layer 126, and an erase gate 128. The gate dielectric layer 122 is disposed, for example, between the auxiliary gate 124 and the substrate 100. The material of the gate dielectric layer 122 is, for example, hafnium oxide. The thickness of the gate dielectric layer 122 is, for example, less than or equal to the thickness of the tunnel dielectric layer 142.

The auxiliary gate 124 is disposed between the gate dielectric layer 122 and the insulating layer 126, for example. The erase gate 128 is, for example, disposed on the insulating layer 126. The auxiliary gate 124 and the erase gate 128 extend, for example, in the Y direction. The material of the auxiliary gate 124 and the erase gate 128 is, for example, a conductor material such as doped polysilicon. The insulating layer 126 is disposed, for example, between the auxiliary gate 124 and the erase gate 128. The material of the insulating layer 126 is, for example, cerium oxide.

The auxiliary gate dielectric layer 130 is disposed, for example, between the floating gate 140 and the auxiliary gate 124. The material of the auxiliary gate dielectric layer 130 is, for example, hafnium oxide/tantalum nitride/yttria or tantalum nitride/yttria. The thickness of the auxiliary gate dielectric layer 130 is, for example, greater than or equal to the thickness of the erase gate dielectric layer 132. The erase gate dielectric layer 132 is disposed, for example, between the erase gate 128 and the floating gate 140. The material of the erase gate dielectric layer 132 is, for example, ruthenium oxide. The thickness of the erase gate dielectric layer 132 is, for example, between 100 angstroms and 180 angstroms. The erase gate dielectric layer 132 is, for example, disposed between the erase gate 128 and the auxiliary gate 124.

The floating gate 140 is, for example, a sidewall disposed on a first side of the stacked gate structure 120, and the top of the floating gate 140 has a corner portion 141. The erase gate 128 covers the corner portion 141 of the floating gate 140. The angle of the corner portion 141 is less than or equal to 90 degrees. The material of the floating gate 140 is, for example, a conductor material such as doped polysilicon. The floating gate 140 may be composed of one or more conductor layers.

The tunneling dielectric layer 142 is disposed, for example, between the floating gate 140 and the substrate 100. The tunneling dielectric layer 142 is disposed, for example, between the control gate 150 and the source region 146. The material of the tunneling dielectric layer 142 is, for example, yttrium oxide. The thickness of the tunneling dielectric layer 142 is between 60 angstroms and 200 angstroms.

The source region 146 is, for example, disposed in the substrate 100 beside the floating gate 140. The drain region 148 is, for example, disposed in the substrate 100 on the second side of the stacked gate structure 120, with the first side being opposite the second side. The source region 146 and the drain region 148 are, for example, doped regions containing N-type or P-type dopants, depending on the design of the terminal elements.

The control gate 150 is, for example, disposed in the source region 146 and the floating gate 140 on. The control gate 150 extends, for example, in the Y direction (column direction). The material of the control gate 150 is, for example, a conductor material such as doped polysilicon. The inter-gate dielectric layer 152 is disposed, for example, between the control gate 150 and the floating gate 140. The material of the inter-gate dielectric layer 152 is, for example, tantalum oxide/tantalum nitride/yttria or tantalum nitride/yttria or other high dielectric constant material (k>4).

The interlayer insulating layer 160 is disposed on the substrate 100 and covers the first memory cell 110 and the second memory cell 112, for example. The material of the interlayer insulating layer 160 is, for example, ruthenium oxide, phosphorous glass, borophosphon glass or other suitable dielectric material. The plug 162 is disposed, for example, in the interlayer insulating layer 160, and the plug 162 is electrically connected to the drain region 148. The material of the plug 162 is, for example, a conductor material such as aluminum or tungsten. The bit line 164 is disposed, for example, on the interlayer insulating layer 160, and the bit line 164 is electrically connected to the drain region 148 by the plug 162. The material of the bit line 164 is, for example, a conductor material such as aluminum, tungsten or copper.

In the X direction (row direction), a plurality of memory cells MC are connected in series by a source region 146 or a drain region 148. For example, the structure of the memory cell 110 is the same as that of the memory cell 112, and the memory cell 110 is mirrored with the memory cell 112, sharing the source region 146 or the drain region 148; the structure of the memory cell 114 and the memory cell 116 The structure is the same, and the memory cell 114 is mirrored with the memory cell 116, sharing the source region 146 or the drain region 148. At the same time, the memory cell 110 and the memory cell 112 share the control gate 150, and the control gate 150 fills the memory cell 110 and the memory cell 112; the memory cell 114 shares the control gate 150 with the memory cell 116, and controls the gate 150. Fill between memory cell 114 and memory cell 116.

In the Y direction (column direction), a plurality of memory cells MC are sourced by the source region 146, The helper gate (word line) 124, the erase gate 128, and the control gate 150 are connected in series. That is, in the column direction, the plurality of memory cells MC share the same source region 146, the auxiliary gate (word line) 124, the erase gate 128, and the control gate 150. For example, the structure of the memory cell 110 is the same as that of the memory cell 114. The structure of the memory cell 112 is the same as that of the memory cell 116. The control gate 150 fills the structure of the memory cell 110 and the memory cell 114 and the memory cell 112. Between memory cells 116. The memory cells 114 of the same column share the same source region 146, the auxiliary gate (word line) 124, the erase gate 128, and the control gate 150 with the first memory cell 110.

In the above non-volatile memory, the two memory cells MC adjacent in the X direction (row direction) have the same structure and are, for example, mirrored, share the source region 146 or the drain region 148, and share the control gate 150. . The two memory cells MC adjacent in the Y direction (column direction) have the same structure, and share the source region 146, the auxiliary gate (word line) 124 (124a), the erase gate 128, and the control gate 150. Therefore, the degree of integration of components can be improved.

In the above non-volatile memory, the auxiliary gate and the erase gate are arranged in a stacked gate structure, so that the degree of integration of components can be improved.

In the above non-volatile memory, the thickness of the gate dielectric layer 122 is relatively thin, and when operating the memory cell, a smaller voltage can be used to turn on/off the channel region under the auxiliary gate 124, that is, the operating voltage can be lowered. . The control gate 150 covers the floating gate 140, which can increase the area sandwiched between the control gate 150 and the floating gate 140, and improve the coupling ratio of the memory element. Since the floating gate 140 has the corner portion 141. The gate 128 is wiped to cover the corner portion 141, and the angle of the corner portion 141 is smaller than Or equal to 90 degrees, the electric field is concentrated by the corner portion 141, and the erasing voltage can be reduced to efficiently pull the electrons out of the floating gate 140, thereby increasing the speed at which the data is erased.

2A-2H are schematic cross-sectional views showing a process of fabricating a non-volatile memory according to an embodiment of the invention.

Referring to Figure 2A, a substrate 200 is first provided. Next, a dielectric layer 202, a conductor layer 204, an insulating layer 206, and a sacrificial layer 208 are sequentially formed on the substrate 200. The material of the dielectric layer 202 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method. The material of the conductor layer 204 is, for example, doped polysilicon or polycrystalline metal. When the material of the conductor layer 204 is doped polysilicon, the formation method is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and performing an ion implantation step to form; or in-situ A method of implanting a dopant is formed by chemical vapor deposition. The material of the insulating layer 206 is, for example, cerium oxide, and the forming method thereof is, for example, a chemical vapor deposition method. The material of the sacrificial layer 208 includes a different etching selectivity from the material of the insulating layer 206, such as tantalum nitride, and the forming method thereof is, for example, chemical vapor deposition.

Next, the sacrificial layer 208, the insulating layer 206, the conductor layer 204, and the dielectric layer 202 are patterned to form at least two stacked structures 210. The method for forming the at least two stacked structures 210 is, for example, forming a patterned photoresist layer (not shown) on the substrate 200. The method for forming the patterned photoresist layer is, for example, forming a layer of photoresist material on the entire substrate 200. Then, it is formed by exposure and development. Then, a portion of the sacrificial layer 208, the insulating layer 206, the conductor layer 204, and the dielectric layer 202 are removed by using the patterned photoresist layer as a mask to form at least two stacked structures 210. Next, the patterned photoresist layer is removed. The method of removing the patterned photoresist layer is, for example, a wet de-resisting method or a dry de-resisting method. The dielectric layer 202 serves as a gate dielectric layer. The conductor layer 204 serves as an auxiliary gate (word line).

Referring to FIG. 2B, the sidewall of the stacked structure 210 forms a layer of isolation material 212. The material of the isolating material layer 212 is, for example, hafnium oxide/tantalum nitride/yttria or tantalum nitride/yttria. The method for forming the isolation material layer 212 is, for example, sequentially forming a dielectric layer 214 and a dielectric layer 216 covering the stacked structures 210 on the substrate 200, and then removing a portion of the dielectric layer 214 and the dielectric layer 216 to form a stacked structure. The sidewalls of 210 form a layer of isolation material 212. The material of the dielectric layer 214 is, for example, tantalum nitride, and the material of the dielectric layer 216 is, for example, tantalum oxide. The method of forming the dielectric layer 214 and the dielectric layer 216 is, for example, a chemical vapor deposition method. A method of removing a portion of the dielectric layer 214 and the dielectric layer 216 is, for example, an anisotropic etching method.

Next, a tunneling dielectric layer 218 is formed on the substrate 200 between the stacked structures 210. The material of the tunneling dielectric layer 218 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method.

Referring to FIG. 2C, a conductor spacer 220 is formed on a sidewall of the stacked structure 210. The method of forming the conductor spacer 220 includes the following steps. A layer of conductor (not shown) is formed on the substrate 200. The material of the conductor layer is, for example, doped polysilicon or polycrystalline metal. When the material of the conductor layer is doped polysilicon, the formation method is, for example, formation of an undoped polysilicon layer by chemical vapor deposition, followed by ion implantation step; or in-situ implantation The method of doping is formed by chemical vapor deposition. Then, part of the conductor layer is removed. Remove part of the conductor layer The method is, for example, an anisotropic etching method or an etch back method.

Next, a source region 222 is formed in the substrate 200 between the conductor spacers 220. That is, the source region 222 is formed in the substrate 200 beside the conductor spacer 220 on the first side of the stacked structure 210. The method of forming the source region 222 is performed by, for example, using the conductor spacer 2220 on the first side as a mask to perform an ion implantation process. The implanted dopant can be either an N-type or a P-type dopant depending on the design of the component.

Referring to FIG. 2D, the conductor spacers 220 are patterned to form the floating gates 224. The method of patterning the conductor spacers 220 is as follows. A patterned photoresist layer (not shown) is formed on the substrate 200. The method of forming the patterned photoresist layer is formed, for example, by forming a layer of a photoresist material on the entire substrate 200, followed by exposure and development. With the patterned photoresist layer as a mask, a portion of the first side conductor spacer 220 is removed to form a block, and the conductor spacer 220 on the second side of each stacked structure 210 is removed, wherein the second side and the second side One side is opposite. Thereafter, the patterned photoresist layer is removed. The top of this floating gate 224 has a corner portion 226. Next, a portion of the floating gate 224 is removed such that the corner portion 226 is adjacent to the sacrificial layer 208. That is, the corner portion 226 is highly dropped between the heights of the sacrificial layers 208.

A layer of material 228 is then formed over the substrate 200 to fill the gap between the stacked structures 210. The material of the material layer 228 is, for example, ruthenium oxide, and the formation method thereof is, for example, a chemical vapor deposition method.

Referring to FIG. 2E, the sacrificial layer 208 is removed, and a portion of the dielectric layer 214 is removed to form the opening 230. The method of removing the sacrificial layer 208 and the portion of the dielectric layer 214 is, for example, a wet etching method or a dry etching method.

Referring to FIG. 2F, a portion of the material layer 228, a portion of the insulating layer 206, and a portion of the dielectric layer 216 are removed to form an opening 232. The opening 232 exposes at least the corner portion 226 of the floating gate 224. A method of removing a portion of the material layer 228, a portion of the insulating layer 206, and a portion of the dielectric layer 216 is, for example, a wet etching method or a dry etching method. At this time, the isolation material layer 212 between the floating gate 224 and the conductor layer 204 serves as an auxiliary gate dielectric layer.

Referring to FIG. 2G, an erase gate dielectric layer 234 is formed on the substrate 200. The material of the erase gate dielectric layer 234 is, for example, hafnium oxide. The method of forming the gate dielectric layer 234 is, for example, a chemical vapor deposition method. An erase gate 236 filling the opening 232 is formed on the substrate 200. The erase gate 236 is formed by forming a conductor layer (not shown) filling the opening 232 on the substrate 200, and then removing a portion of the conductor layer outside the opening 232. The material of the conductor layer is, for example, doped polysilicon or polycrystalline metal. When the material of the conductor layer is doped polysilicon, the formation method is, for example, formation of an undoped polysilicon layer by chemical vapor deposition, followed by ion implantation step; or in-situ implantation The method of doping is formed by chemical vapor deposition. A method of removing a portion of the conductor layer outside the opening 232 is, for example, an etch back method or a chemical mechanical polishing method.

Referring to FIG. 2H, a portion of the erase gate dielectric layer 234 is removed and the material layer 228 is removed. A method of removing a portion of the erase gate dielectric layer 234 and the material layer 228 is, for example, a wet etching method or a dry etching method.

Then, an inter-gate dielectric layer 238 is formed on the substrate 200, and the inter-gate dielectric layer 238 covers the floating gate 224 and the erase gate 236. Material of the dielectric layer 238 of the gate Including cerium oxide / tantalum nitride / cerium oxide. The method of forming the inter-gate dielectric layer 238 is, for example, sequentially forming a hafnium oxide layer, a tantalum nitride layer, and another layer of hafnium oxide by chemical vapor deposition. The material of the inter-gate dielectric layer 238 may also be tantalum nitride/yttria or other high dielectric constant material (k>4).

Then, a control gate 240 is formed on the floating gate 224. The material of the control gate 240 is, for example, doped polysilicon or polycrystalline metal. The control gate 240 is formed by, for example, forming a conductor layer (not shown) on the substrate, and then patterning the conductor layer to form the control gate 240. The method of forming the conductor layer is, for example, a chemical vapor deposition method.

Next, a drain region 242 is formed in the substrate 200 next to the second side of the stacked structure 210. The method of forming the drain region 242 is, for example, an ion implantation process. The implanted dopant can be either an N-type or a P-type dopant depending on the design of the component. The doping dopant and the doping concentration of the source region 222 and the drain region 242 may be the same or different.

Referring to FIG. 2I, an interlayer insulating layer 244 is formed on the substrate 200. The material of the interlayer insulating layer 244 is, for example, cerium oxide, phosphoric glass, borophosphon glass or other suitable dielectric material, and the forming method thereof is, for example, a chemical vapor deposition method. Then, a plurality of plugs 246 electrically connected to the drain regions 242 are formed in the interlayer insulating layer 244. The material of the plug 246 is, for example, a conductor material such as aluminum or tungsten.

The step of forming the plug 246 in the interlayer insulating layer 244 is as follows. A portion of the interlayer insulating layer 244 is first removed to form an opening that exposes the drain region 242. Next, a layer of conductive material (not shown) filled with openings is formed on the substrate 200. Thereafter, a portion of the conductor material layer is removed by chemical mechanical polishing or etch back until the layer is exposed Inter-insulating layer 244. The method of forming the opening is, for example, a lithography technique.

Next, a bit line 248 is formed on the interlayer insulating layer 244. Bit line 248 is electrically coupled to drain region 242 by plug 246. The material of the bit line 248 is, for example, a conductor material such as aluminum, tungsten or copper. The bit line 248 is formed by, for example, forming a conductor layer (not shown) on the substrate 200, and then patterning the conductor layer to form the bit line 248. The method of forming the conductor layer is, for example, a physical vapor deposition method or a chemical vapor deposition method.

In the method of manufacturing a non-volatile memory of the present invention, two memory cells adjacent in the X direction (row direction) have the same structure and are, for example, mirrored, share a source region or a drain region, and share a control gate. . The two memory cells adjacent in the Y direction (column direction) have the same structure, sharing the source region, the gate dielectric layer, the auxiliary gate (word line), the insulating layer, the erase gate, and the control gate. Therefore, the degree of integration of components can be improved.

In the method of manufacturing a non-volatile memory of the present invention, the formed auxiliary gate and the erase gate constitute a stacked structure, so that the degree of integration of the elements can be improved.

In the above method for manufacturing a non-volatile memory, the gate dielectric layer under the auxiliary gate is formed to have a thin thickness, and when the memory cell is operated, a smaller voltage can be used to turn on/off the auxiliary gate under the gate. In the channel area, the operating voltage can be reduced. The formed control gate covers the floating gate, which can increase the area sandwiched between the control gate and the floating gate, and improve the coupling ratio of the memory component. Since the floating gate has a corner portion. Wiping the gate to cover the corner portion, and the angle of the corner portion is less than or equal to 90 degrees, and the electric field is concentrated by the corner portion, thereby reducing the erasing voltage and efficiently pulling the electrons from the floating gate to improve the erasing The speed of the data.

Next, the operation mode of the non-volatile memory of the present invention will be described, including Stylized, erased, and read data modes. Fig. 3A is a schematic diagram showing an example of a program operation of a memory cell. Fig. 3B is a schematic diagram showing an example of an erase operation on a memory cell. Fig. 3C is a schematic diagram showing an example of a reading operation on a memory cell.

Referring to FIG. 3A, during the stylization operation, a voltage Vwlp is applied to the auxiliary gate WL0 of the selected memory cell to form a channel in the substrate under the auxiliary gate, and the voltage Vwlp is, for example, 0.6 to 1.2 volts. The auxiliary gate WL1 of the unselected memory cell applies a voltage of 0 volts. The voltage Vsp is applied to the source region S; the voltage Vcgp is applied to the control gate CG; the erase gate EP0 of the selected memory cell and the erase gate EP1 of the unselected memory cell are applied with the voltage Vegp. The voltage Vsp is, for example, 3 to 7 volts; the voltage Vcgp is, for example, 5 to 9 volts; and the voltage Vegp is, for example, 3 to 7 volts. Under such a bias voltage, the electrons are moved from the drain to the source, and the floating gate FG0 of the selected memory cell is injected in the source-side hot electron injection mode. Since the auxiliary gate WL1 of the unselected memory cell applies a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gate FG1 of the unselected memory cell, so the unselected memory cells are not programmed.

Referring to FIG. 3B, when the erase operation is performed, the voltage Vcge is applied to the control gate CG; the voltage Vege is applied to the erase gate EP0 of the selected memory cell; and the erase gate EP1 of the unselected memory cell is applied with 0 volts. Voltage. The voltage Vege is, for example, 6 to 12 volts; the voltage Vcge is, for example, -8 to 0 volts. By using the voltage difference between the control gate CG and the erase gate EP0, the FN tunneling effect is induced, and the floating gate FG0 stored in the memory cell is electronically pulled out and removed.

Referring to FIG. 3C, when the read operation is performed, a voltage Vcc is applied to the auxiliary gate WL0 of the selected memory cell; a voltage of 0-Vcc is applied to the control gate CG; The erase gate EP0 of the fixed memory cell applies a voltage of 0-Vcc; the erase gate EP1 of the unselected memory cell applies a voltage of 0-Vcc. Among them, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the memory cell can be judged by detecting the channel current of the memory cell.

In the method of operating the non-volatile memory of the present invention, when a stylizing operation is performed, a low voltage is applied to the auxiliary gate, so that a channel can be formed in the substrate under the auxiliary gate, and the source side is injected with hot electrons. Mode, writing electrons to the floating gate. When erasing is performed, the erase electrode is used to erase the data, and the electrons are removed through the eraser dielectric layer, thereby reducing the number of times the electrons pass through the tunnel dielectric layer, thereby improving reliability. In addition, since the floating gate has a corner portion. Wiping the gate to cover the corner portion, and the angle of the corner portion is less than or equal to 90 degrees, and the electric field is concentrated by the corner portion, and the electrons can be efficiently pulled out from the floating gate to increase the speed of erasing the data.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

120‧‧‧Stack gate structure

122‧‧‧gate dielectric layer

124‧‧‧Auxiliary gate

126‧‧‧Insulation

128‧‧‧Erase the gate

130‧‧‧Auxiliary gate dielectric layer

132‧‧‧Erase the gate dielectric layer

140‧‧‧Floating gate

141‧‧‧ Corner

142‧‧‧Tunnel dielectric layer

146‧‧‧ source area

148‧‧‧Bungee Area

150‧‧‧Control gate

152‧‧‧Interruptor dielectric layer

160‧‧‧Interlayer insulation

162‧‧‧ plug

164‧‧‧ bit line

MC‧‧‧ memory cell

Claims (18)

A non-volatile memory comprising: a first memory cell disposed on a substrate, the first memory cell comprising: a stacked gate structure comprising a gate dielectric layer and an auxiliary gate sequentially disposed on the substrate a pole, an insulating layer, and an erase gate; a floating gate disposed on a sidewall of the first side of the stacked gate structure, and a top portion of the floating gate has a corner portion, the erase gate package And covering the corner portion; the tunneling dielectric layer is disposed between the floating gate and the substrate; the erase gate dielectric layer is disposed on the erase gate and the floating gate An auxiliary gate dielectric layer is disposed between the auxiliary gate and the floating gate; a source region and a drain region are respectively disposed on the stacked gate structure and the floating gate In the substrate of the side, wherein the source region abuts the floating gate, the drain region abuts a second side of the stacked gate structure, the first side being opposite the second side a control gate disposed on the source region and the floating gate; and a gate dielectric layer disposed on the control gate Between said floating gate and said control gate electrode and the erase gate. The non-volatile memory as described in claim 1 of the patent scope further includes: a second memory cell disposed on the substrate, the structure of the second memory cell is the same as the structure of the first memory cell, and the second memory cell is mirrored and configured to be shared with the first memory cell The source region or the drain region. The non-volatile memory of claim 2, wherein the first memory cell shares the control gate with the second memory cell, and the control gate fills the first memory An opening between the cell and the second memory cell. The non-volatile memory according to claim 1, further comprising: a third memory cell disposed on the substrate, the structure of the third memory cell being the same as the structure of the first memory cell, The source region, the auxiliary gate, the erase gate, and the control gate are shared, and the control gate fills between the first memory cell and the third memory cell. The non-volatile memory of claim 1, wherein the tunneling dielectric layer is further disposed between the control gate and the source region. The non-volatile memory of claim 1, wherein the thickness of the auxiliary gate dielectric layer is greater than or equal to the thickness of the eraser gate dielectric layer. The non-volatile memory according to claim 1, wherein the material of the auxiliary gate dielectric layer comprises yttrium oxide/yttria, yttrium oxide/yttria/yttria or yttrium oxide. The non-volatile memory of claim 1, wherein the material of the insulating layer comprises cerium oxide. The non-volatile memory according to claim 1, wherein the material of the inter-gate dielectric layer comprises yttrium oxide/yttria/yttria or tantalum nitride/yttria or other high dielectric constant. Material (k>4). The non-volatile memory of claim 1, wherein the material of the tunneling dielectric layer comprises yttrium oxide, and the thickness of the tunneling dielectric layer is between 60 angstroms and 200 angstroms. The non-volatile memory of claim 1, wherein the material of the gate dielectric layer comprises ruthenium oxide, and the thickness of the gate dielectric layer is less than or equal to the thickness of the tunnel dielectric layer. The non-volatile memory of claim 1, wherein the material of the eraser dielectric layer comprises ruthenium oxide, and the thickness of the eraser dielectric layer is between 100 angstroms and 180 angstroms. . The non-volatile memory of claim 1, wherein the corner portion angle is less than or equal to 90 degrees. The non-volatile memory of claim 1, wherein the eraser dielectric layer is disposed between the erase gate and the auxiliary gate. A method for manufacturing a non-volatile memory, comprising: providing a substrate; forming at least two stacked structures on the substrate, each of the stacked structures sequentially including a gate dielectric layer, an auxiliary gate, and an insulating layer from the substrate And a sacrificial layer; forming an auxiliary gate dielectric layer on the sidewall of the stacked structure; forming a tunneling dielectric layer on the substrate between the stacked structures; Forming a floating gate on a sidewall of the first side of the stacked structure, wherein a top of the floating gate has a corner portion adjacent to the sacrificial layer; forming a material layer on the substrate, filling Filling a gap between the stacked structures; after removing the sacrificial layer, removing a portion of the material layer, a portion of the insulating layer, and a portion of the auxiliary gate dielectric layer to form at least an exposed portion An opening of the corner portion of the floating gate; forming a wiper dielectric layer on at least the corner portion of the floating gate; forming a erase gate filling the opening on the substrate a pole, wherein the erase gate covers the corner portion of the floating gate; removing the material layer; forming a gate dielectric layer on the floating gate and the erase gate And forming a control gate on the floating gate. The method of manufacturing a non-volatile memory according to claim 15, wherein the step of forming the floating gate on a sidewall of the first side of the stacked structure comprises: the A sidewall of one side forms a conductor spacer; and the conductor spacer is patterned to form the floating gate. The method of manufacturing a non-volatile memory according to claim 16, wherein the step of forming the conductor spacer on a sidewall of the first side of the stacked structure comprises: forming a conductor on the substrate a layer; and performing an anisotropic etching process on the conductor layer. The method of manufacturing the non-volatile memory of claim 16, further comprising: forming a source region in the substrate between the conductor spacers; and on the second side of the stacked structure A drain region is formed in the substrate, the first side being opposite to the second side.