TWI715447B - Method for fabricating backplane - Google Patents

Abstract

A method for fabricating a backplane includes following steps: providing active device substrates, wherein each of the active device substrates includes a base, an active device disposed on a first surface of the base, an insulating layer disposed on the active device, a pad group electrically connected to the active device and a spacer disposed on the insulating layer and located outside the pad group; connecting the first active device substrate and the second active device substrate by a sealant, wherein a spacer of the first active device substrate props against an insulating layer of the second active device substrate, a spacer of the second active device substrate props against an insulating layer of the first active device substrate, and the spacer of the first active device substrate and the spacer of the second active device substrate are staggered; When the sealant connects the first active device substrate and the second active device substrate, a first circuit structure and a second circuit structure are formed on a second surface of the first active device substrate and a second surface of the second active device substrate, respectively; Removing the sealant to separate the first active device substrate from the second active device substrate and form a first backplane and a second backplane.

Description

Manufacturing method of backplane

The invention relates to a manufacturing method of a backplane.

The light emitting diode display panel includes an active device substrate and a plurality of micro light emitting diodes transferred on the active device substrate. Inheriting the characteristics of light-emitting diodes, light-emitting diode display panels have the advantages of power saving, high efficiency, high brightness, and fast response time. In addition, compared with organic light-emitting diode display panels, light-emitting diode display panels also have the advantages of long light-emitting life and no image burn-in. Therefore, LED display panels are regarded as the next generation of display technology.

The light emitting diode display panel includes a micro light emitting diode arranged on the front surface of the active device substrate and a circuit structure electrically connected to the micro light emitting diode. In order to realize a seamless spliced display, multiple light-emitting diode display panels used for splicing into a spliced display need to have an ultra-narrow frame or even no frame. Therefore, the circuit structure needs to be arranged on the back surface of the active device substrate of the light emitting diode display panel. Generally speaking, in the manufacturing process of a light emitting diode display panel, an active device and a pad for electrical connection with the micro light emitting diode are first formed on the front surface of the base of the active device substrate; then, a protective layer is formed , To cover the active components and the pads; later, when the active components and the pads are covered by the protective layer, a circuit structure is formed on the back surface of the base of the active component substrate. However, in the above-mentioned manufacturing process, additional materials must be used as the protective layer for the active components and the pads, which is not conducive to reducing the manufacturing cost.

The present invention provides a method for manufacturing a back plate, which helps reduce manufacturing costs.

A method of manufacturing a backplane of the present invention includes the following steps: providing a plurality of active device substrates, wherein each active device substrate includes a base having a first surface and a second surface opposite to each other, and a substrate disposed on the first surface of the base Active component, an insulating layer disposed on the active component, a pad group disposed on the insulating layer and electrically connected to the active component, and a spacer disposed on the insulating layer and located outside the pad group; a sealant is used to connect a plurality of The first active device substrate of the active device substrate and the second active device substrate of the plurality of active device substrates, wherein the first surface of the first active device substrate faces the first surface of the second active device substrate, and the distance between the first active device substrates The object presses against the insulating layer of the second active element substrate, the spacer of the second active element substrate presses against the insulating layer of the first active element substrate, and the spacer of the first active element substrate and the spacer of the second active element substrate are staggered In the case where the sealant connects the first active device substrate and the second active device substrate, a first circuit structure is formed on the second surface of the base of the first active device substrate; the sealant connects the first active device substrate and In the case of the second active device substrate, a second circuit structure is formed on the second surface of the base of the second active device substrate; after the first circuit structure and the second circuit structure are formed, the sealant is removed so that the first The active device substrate is separated from the second active device substrate to form a first back plate and a second back plate. The first back plate includes a first active device substrate and a first active device substrate disposed on the second surface of the first active device substrate. The circuit structure, and the second backplane includes a second active device substrate and a second circuit structure disposed on the second surface of the second active device substrate.

In an embodiment of the present invention, the above-mentioned manufacturing method of the backplane further includes: forming a first protective layer to cover the first circuit structure after forming the first circuit structure and before forming the second circuit structure.

In an embodiment of the present invention, the manufacturing method of the backplane described above further includes: after forming the second circuit structure and before separating the first active device substrate from the second active device substrate, forming a second protective layer to cover The second line structure.

In an embodiment of the present invention, the manufacturing method of the backplane described above further includes: removing the first protection layer after forming the second protection layer and before separating the first active device substrate from the second active device substrate.

In an embodiment of the present invention, the manufacturing method of the backplane described above further includes: after removing the first protective layer and before separating the first active device substrate from the second active device substrate, forming a third protective layer to Cover the first line structure.

In an embodiment of the present invention, the above-mentioned method for separating the first active device substrate and the second active device substrate includes: covering the first circuit structure and the second circuit structure on the third protective layer and the second protective layer, respectively In this case, the part of the first active element substrate where the sealant is provided and the part of the second active element substrate where the sealant is provided are cut off.

In an embodiment of the present invention, the height of the spacer of each active device substrate is greater than twice the thickness of the pads of the pad group of the active device substrate.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable range of deviation or standard deviation based on optical properties, etching properties, or other properties, instead of using one standard deviation for all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

1A to 1J are schematic diagrams of a manufacturing process of a back plate according to an embodiment of the invention.

1A, first, a plurality of active device substrates 100 are provided, wherein each active device substrate 100 includes a base 110 having a first surface 111 and a second surface 112 opposite to each other, and a base 110 disposed on the first surface 111 of the base 110 The active device T, the insulating layer 194 disposed on the active device T, the pad group 196 disposed on the insulating layer 194 and electrically connected to the active device T, and the space disposed on the insulating layer 194 and located outside the pad group 196物198.

In this embodiment, each active device substrate 100 may optionally include a buffer layer 120. The buffer layer 120 is disposed on the first surface 111 of the base 110. The active device T may be disposed on the buffer layer 120, but the present invention does not Limit this.

The active device T includes a thin film transistor having a semiconductor pattern 130, a gate electrode 150, a gate insulating layer 140 disposed between the gate electrode 150 and the semiconductor pattern 130, and two different electrical properties from the semiconductor pattern 130. The source 172 and the drain 174 are connected. For example, in this embodiment, the semiconductor pattern 130 may be disposed on the buffer layer 120, the gate insulating layer 140 may be disposed on the semiconductor pattern 130 and the buffer layer 120, and the gate 150 may be disposed on the gate insulating layer 140. An interlayer dielectric layer 160 may be disposed on the gate 150 and the gate insulating layer 140, and the source electrode 172 and the drain electrode 174 may be disposed on the first interlayer dielectric layer 160.

In short, in this embodiment, the gate 150 may be disposed above the semiconductor pattern 130, and the thin film transistor may be a top gate type. However, the present invention is not limited to this. In other embodiments, the thin film transistor may also be a bottom gate type or other types.

In addition, in this embodiment, each active device substrate 100 can also optionally include a second interlayer dielectric layer 180 and a transfer pattern 192, wherein the second interlayer dielectric layer 180 is disposed on the source electrode 172 and the drain electrode 174 And the first interlayer dielectric layer 160, and the transfer pattern 192 is disposed on the second interlayer dielectric layer 180 and electrically connected to the drain electrode 174. In this embodiment, the insulating layer 194 may be disposed on the transfer pattern 192 and the second interlayer dielectric layer 180, and a plurality of pads 196a, 196b of the pad group 196 may be disposed on the insulating layer 194, one of the pads 196a can be electrically connected to the active device T through the transfer pattern 192. However, the present invention is not limited to this. In other embodiments, the pad 196a of the pad set 196 may also be electrically connected to the active device T in other ways.

For example, in this embodiment, the material of the base 110 of the active device substrate 100 can be glass, quartz, organic polymers, opaque/reflective materials (for example, wafers, ceramics, or other applicable materials) Or other materials; the material of the pads 196a, 196b can be metal, metal oxide, a combination of metal and metal oxide, or other materials; the material of the insulating layer 194 can be an organic material or other materials; the material of the spacer 198 can be Organic photoresist or other materials; but the invention is not limited to this.

In this embodiment, no active device T is provided under the spacer 198 of each active device substrate 100. For example, in this embodiment, the bottom surface of the spacer 198 may be a polygon, and the spacer 198 may be a pyramid. However, the present invention is not limited to this, and the bottom surface of the spacer 198 and/or the spacer 198 may also have other shapes. For example, in another embodiment, the bottom surface of the spacer 198 may be circular, and the spacer 198 may be a truncated cone.

1A, the above-mentioned multiple active device substrates 100 include a first active device substrate 100-1 and a second active device substrate 100-2 that are separated from each other. Please refer to FIGS. 1A and 1B. Then, a sealant 200 will be used to connect the first active device substrate 100-1 and the second active device substrate 100-2, wherein the first surface of the first active device substrate 100-1 111 faces the first surface 111 of the second active device substrate 100-2, the spacers 198 of the first active device substrate 100-1 abut the insulating layer 194 of the second active device substrate 100-2, and the second active device substrate 100- The spacer 198 of 2 abuts the insulating layer 194 of the first active device substrate 100-1, and the spacer 198 of the first active device substrate 100-1 is staggered from the spacer 198 of the second active device substrate 100-2. In other words, after the first active device substrate 100-1 and the second active device substrate 100-2 are assembled using the sealant 200, the spacers 198 of the first active device substrate 100-1 will not interact with the second active device substrate 100- The spacers 198 of 2 overlap.

In this embodiment, the height H of the spacer 198 of each active device substrate 100 is greater than twice the thickness D of the pad 196a. Thereby, when the first active device substrate 100-1 and the second active device substrate 100-2 are assembled, the pad group 196 of the first active device substrate 100-1 and the second active device substrate 100-2 can maintain a proper gap , So that the pad group 196 of the first active device substrate 100-1 and the second active device substrate 100-2 will not damage each other.

2 is a schematic top view of the base 110, pixels PX, and spacers 198 of the active device substrate 100 according to an embodiment of the invention.

1A and FIG. 2, in this embodiment, a plurality of active device substrates 100 are manufactured using the same set of photomasks, and the plurality of spacers 198 of the plurality of active device substrates 100 are arranged in the same manner in each On the substrate 110. In other words, if the first surface 111 of the first active device substrate 100-1 and the first surface 111 of the second active device substrate 100-2 both face the observer, the observer can find that the first active device substrate 100-1 The arrangement of the spacers 198 is substantially the same as the arrangement of the spacers 198 of the second active device substrate 100-2.

3 is a schematic top view of the base 110 and its spacers 198 of the first active device substrate 100-1 and the base 110 and its spacers 198 of the second active device substrate 100-2 according to an embodiment of the present invention.

1B, the first active device substrate 100-1 and the second active device substrate 100-2 are assembled into a temporary structure (ie, the first active device substrate 100-1 and the second active device substrate 100-2 shown in FIG. 1B And sealant 200), and FIG. 3 shows the spacers 198 of the first active device substrate 100-1 and the spacers 198 of the second active device substrate 100-2 of the temporary structure, with solid lines The spacer 198 of the first active device substrate 100-1 is represented, and the spacer 198 of the second active device substrate 100-2 is represented by a dotted line.

1B and 3, in this embodiment, although the first active device substrate 100-1 and the second active device substrate 100-2 are manufactured using the same set of photomasks, and the first active device substrate 100-1 The spacers 198 and the spacers 198 of the second active device substrate 100-2 are arranged on the respective base 110 in the same manner, but since the spacers 198 of each active device substrate 100 are arranged in a special way, the first After an active device substrate 100-1 and a second active device substrate 100-2 are assembled, the spacers 198 of the first active device substrate 100-1 and the spacers 198 of the second active device substrate 100-2 will be staggered with respect to each other. Compete against each other.

The following illustrates one of the possible special arrangements of spacers 198 in conjunction with FIG. 2.

2, the plurality of spacers 198 on the outermost periphery of the active device substrate 100 define a range AA. The range AA has a first center axis X1 and a second center axis X2, wherein the first center axis X1 and the second center axis X2 They respectively extend in the first direction d1 and the second direction d2 and are perpendicular to each other. In particular, the spacers 198 are not provided on the first central axis X1 and the second central axis X2, and the plurality of spacers 198 respectively located on both sides of the first central axis X1 are not arranged in a mirror image, and are respectively located on the second central axis X2 The multiple spacers 198 on both sides are not arranged in a mirror image. With the above-mentioned special arrangement of the spacers 198, after the first active device substrate 100-1 and the second active device substrate 100-2 are assembled, the spacers 198 of the first active device substrate 100-1 and the second active device substrate 100 The spacers 198 of -2 will be staggered and not against each other.

1A and FIG. 2, in this embodiment, the active device substrate 100 includes a plurality of pixels PX arranged in the range AA, each pixel PX includes a plurality of sub-pixels SPX, each sub-pixel SPX has The active device T and the pad group 196 electrically connected to the active device T. Please refer to FIG. 2, the multiple pixels PX of the active device substrate 100 are arranged in an X∙Y matrix, X and Y are positive integers greater than 1, and the multiple pixels PX arranged in the X∙Y matrix are included in the first X pixel rows C sequentially arranged in the direction d1 and Y pixel rows R sequentially arranged in the second direction d2, wherein a plurality of pixels PX of each pixel row C are sequentially arranged in the second direction d2, and The pixels PX of each pixel row R are arranged in sequence in the first direction d1.

In this embodiment, X and Y are odd numbers. In the odd-numbered pixel column R, the spacer 198 is placed at the corner of the odd-numbered (1, 3, 5...) pixel PX; in the even-numbered picture In the element array R, spacers 198 are placed at the corners of even-numbered (2, 4, 6...) pixels PX. For example, X=15, Y=9, in the pixel rows R of 1, 3, 5, 7, and 9, the spacers 198 are placed at 1, 3, 5, 7, 9, 11, and 13 , The upper right corner of the 15 pixels PX; in the second, fourth, sixth, and eighth pixel column R, the spacer 198 is placed at the second, fourth, sixth, eighth, tenth, 12th, and 14th pixel PX But the present invention is not limited to this.

As shown in FIG. 3, in this embodiment, using the special arrangement of the spacers 198 described above, after the first active device substrate 100-1 and the second active device substrate 100-2 are assembled, the first active device substrate 100-1 The spacers 198 of the second active device substrate 100-2 and the spacers 198 of the second active device substrate 100-2 are staggered with each other and will not abut each other.

It should be noted that FIG. 2 is only an example of one possible special arrangement of the spacers 198, and FIG. 2 is not used to limit the arrangement of the spacers 198. In other embodiments, the spacers 198 can also be arranged on the base 110 in other special ways, so that after the first active device substrate 100-1 and the second active device substrate 100-2 are assembled, the first active device substrate 100- The spacer 198 of 1 and the spacer 198 of the second active device substrate 100-2 do not abut against each other. The following paragraphs will be accompanied by other illustrations to illustrate.

1B, after the first active device substrate 100-1 and the second active device substrate 100-2 are assembled, the pads 196a, 196b of the first active device substrate 100-1 and the second active device substrate 100-2 The pads 196a and 196b are sealed in a space enclosed by the sealant 200, and are not easily damaged by subsequent manufacturing processes. In other words, during the manufacturing process of the backplane, the first active device substrate 100-1 and the second active device substrate 100-2 are used as a protective layer for each other, and no additional materials are needed in this step. For the protective layer.

1C, next, when the sealant 200 connects the first active device substrate 100-1 and the second active device substrate 100-2, on the second surface 112 of the base 110 of the first active device substrate 100-1 A first circuit structure 210 is formed thereon.

For example, in this embodiment, the first circuit structure 210 includes a first barrier protection layer 211 disposed on the second surface 112 of the first active device substrate 100-1, and a first barrier protection layer 211. The fan-out wiring 212 on the upper side, the second barrier protection layer 213 provided on the first barrier protection layer 211 and the fan-out wiring 212, and the second barrier protection layer 213 are provided on the second barrier protection layer 213 and are electrically connected to the fan-out wiring 212的接垫214. However, the present invention is not limited to this, and in other embodiments, the first circuit structure 210 may also have other structures.

Please refer to FIG. 1D. Next, a first protective layer 310 is formed to cover the first circuit structure 210. For example, in this embodiment, the first circuit structure 210 includes a metal oxide sub-layer 311 disposed on the first circuit structure 210 and an insulating sub-layer 312 disposed on the metal oxide sub-layer 311. In this embodiment, the material of the metal oxide sub-layer 311 is, for example, Indium-Zinc Oxide (IZO), and the material of the insulating sub-layer 312 is, for example, silicon nitride (SiNx), but the invention is not limited to this. .

1E, then, when the sealant 200 is connected to the first active device substrate 100-1 and the second active device substrate 100-2 and the first protective layer 310 covers the first circuit structure 210, the second active device A second circuit structure 220 is formed on the second surface 112 of the base 110 of the substrate 100-2.

For example, in this embodiment, the second circuit structure 220 includes a first barrier protection layer 221 disposed on the second surface 112 of the second active device substrate 100-2, and a first barrier protection layer 221. The fan-out wiring 222 on the upper side, the second barrier protection layer 223 provided on the first barrier protection layer 221 and the fan-out wiring 222, and the second barrier protection layer 223 provided on the second barrier protection layer 223 and electrically connected to the fan-out wiring 222的接垫224. However, the present invention is not limited to this, and in other embodiments, the second circuit structure 220 may also have other structures.

1F, then, a second protective layer 320 is formed to cover the second circuit structure 220. For example, in this embodiment, the second protective layer 320 is, for example, a hard glue layer, but the invention is not limited to this.

Please refer to FIG. 1F and FIG. 1G, and then, the first protective layer 310 is removed. For example, in this embodiment, the first protection layer 310 can be removed by an etching process, but the invention is not limited to this.

Please refer to FIG. 1H, and then, a third protection layer 330 is formed to cover the first circuit structure 210. For example, in this embodiment, the third protective layer 330 is, for example, a hard glue layer, but the invention is not limited to this.

Please refer to FIG. 1I and FIG. 1J, then, the sealant 200 is removed to separate the first active device substrate 100-1 from the second active device substrate 100-2. For example, in this embodiment, when the third protective layer 330 and the second protective layer 320 respectively cover the first circuit structure 210 and the second circuit structure 220, the first active device substrate 100-1 can be cut off. A part of the sealant 200 and a part of the second active device substrate 100-2 are provided with the sealant 200. When the first active device substrate 100-1 is provided with a part of the sealant 200 and the second active device substrate 100- When a part of 2 where the sealant 200 is provided is cut off, naturally, the first active device substrate 100-1 and the second active device substrate 100-2 that are originally connected to each other can be separated. However, the present invention is not limited to this. In other embodiments, the first active device substrate 100-1 and the second active device substrate 100-2 are separated.

1J, here, the first backplane 10-1 and the second backplane 10-2 are completed, where the first backplane 10-1 includes a first active device substrate 100-1 and a first active device substrate 100-1. The first circuit structure 210 on the second surface 112 of the device substrate 100-1, and the second backplane 10-2 includes a second active device substrate 100-2 and a second surface disposed on the second active device substrate 100-2 112 on the second line structure 220.

In this embodiment, after the first back plate 10-1 and the second back plate 10-2 are completed, the first back plate 10-1 and the second back plate 10-2 can be respectively processed and driven by the side wires Chip bonding process and micro light emitting diode (µLED) transposition process.

Specifically, in the side wiring process of the first backplane 10-1, side wires (not shown) can be formed on the sidewalls (not shown) of the base 110 of the first active device substrate 100-1 , Wherein the sidewall of the substrate 110 is connected between the first surface 111 of the substrate 110 and the second surface 112 of the substrate 110. The active device T disposed on the first surface 111 of the first active device substrate 100-1 and the pads 214 disposed on the second surface 112 of the first active device substrate 100-1 can be disposed on the sidewalls of the base 110 The side wires are electrically connected to each other. In the driving chip bonding process, the driving chip (not shown) is electrically connected to the pad 214 on the second surface 112 of the first active device substrate 100-1. In the micro light emitting diode (µLED) transposition process of the first backplane 10-1, the micro light emitting diode (µLED) can be transposed on the first surface 111 of the first active device substrate 100-1 and It is electrically connected to the pads 196a and 196b provided on the first surface 111 of the first active device substrate 100-1. After completing the side wire process of the first backplane 10-1, the driving chip bonding process, and the micro light emitting diode (µLED) transposition process, the first backplane 10-1 and the micro light emitting diodes and side The side wire and the driving chip can form a miniature light emitting diode display panel.

Similarly, in the side wiring process of the second backplane 10-2, side wires (not shown) can be formed on the sidewalls (not shown) of the base 110 of the second active device substrate 100-2. The sidewall of the substrate 110 is connected between the first surface 111 of the substrate 110 and the second surface 112 of the substrate 110. The active device T disposed on the first surface 111 of the second active device substrate 100-2 and the pads 224 disposed on the second surface 112 of the second active device substrate 100-2 can be disposed on the sidewall of the base 110 The side wires are electrically connected to each other. In the driving chip bonding process, the driving chip (not shown) is electrically connected to the pads 224 on the second surface 112 of the second active device substrate 100-2. In the micro light emitting diode (µLED) transposition process of the second backplane 10-2, the micro light emitting diode (µLED) can be transposed on the first surface 111 of the second active device substrate 100-2 and It is electrically connected to the pads 196a and 196b provided on the first surface 111 of the second active device substrate 100-2. After completing the side wire process of the second backplane 10-2, the driving chip bonding process, and the micro light emitting diode (µLED) transposition process, the second backplane 10-2 and the micro light emitting diodes and side The side wire and the driving chip can form a miniature light emitting diode display panel.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, refer to the foregoing embodiment, and the following embodiments will not be repeated.

4 is a schematic top view of a base 110, pixels PX, and spacers 198 of another active device substrate 100A according to an embodiment of the invention.

The active device substrate 100A of FIG. 4 is similar to the active device substrate 100 of FIG. 2. 4, the multiple pixels PX of the active device substrate 100A are arranged in an X∙Y matrix, X and Y are positive integers greater than 1, and the multiple pixels PX arranged in the X∙Y matrix are included in the first A plurality of pixel rows C arranged in sequence in the direction d1 and a plurality of pixel columns R arranged in sequence in the second direction d2, wherein the plurality of pixels PX of each pixel row C are sequentially arranged in the second direction d2 And the pixels PX of each pixel row R are sequentially arranged in the first direction d1. The difference from the active device substrate 100 of FIG. 2 is that in the embodiment of FIG. 4, X and Y are even numbers; the first central axis X1 is located between two adjacent pixel rows R, and the adjacent two pixel rows There is no spacer 198 on one corner of each pixel PX of one of R; the second central axis X2 is located between two adjacent pixel rows C, and each pixel of one of the two adjacent pixel rows C There is no spacer 198 on one corner of the plain PX. For example, X=16, Y=10, the first central axis X1 is located between the adjacent fifth pixel row R and the sixth pixel row R, and each picture of the sixth pixel row R There is no spacer 198 in the upper right corner of the pixel PX; the second central axis X2 is located between the adjacent 8th pixel row C and the 9th pixel row C, and the upper right of each pixel PX in the 8th pixel row C The corners are not provided with spacers 198, but the present invention is not limited to this.

5 is a schematic top view of the base 110, the pixels PX, and the spacers 198 of the active device substrate 100B according to another embodiment of the present invention.

The active device substrate 100B of FIG. 5 is similar to the active device substrate 100 of FIG. 2. The difference between the two is: in the embodiment of FIG. 5, the arrangement density of the spacers 198 is reduced according to actual requirements.

6 is a schematic top view of the base 110, pixels PX, and spacers 198 of the active device substrate 100C according to another embodiment of the present invention.

The active device substrate 100C of FIG. 6 is similar to the active device substrate 100 of FIG. 2. The difference between the two is: in the embodiment of FIG. 6, in the odd-numbered pixel column R, the spacer 198 is placed in the corner of the even-numbered (2, 4, 6...) pixel PX; In the pixel column R of, spacers 198 are placed at the corners of odd number (1, 3, 5...) pixels PX. For example, X=15, Y=9, in the pixel rows R of the second, fourth, sixth, and eighth, the spacers 198 are placed on the first, third, fifth, seventh, nineteenth, 11th, 13th, and 15th pixel columns. The upper right corner of a pixel PX; in the pixel column R of 1, 3, 5, 7, and 9, the spacer 198 is placed at the 2, 4, 6, 8, 10, 12, and 14 pixel PX But the present invention is not limited to this.

FIG. 7 shows the repeating unit U and the spacer 198 according to an embodiment of the present invention.

Referring to FIG. 7, spacers 198 can be arranged around and/or corners of any repeating unit U. The repeating unit U can be a sub-pixel SPX, a pixel PX, a combination of multiple sub-pixels SPX, or multiple pixels. The combination of PX. For example, in the embodiment of FIG. 7, three pixels PX are used as the repeating unit U, and the spacer 198 is arranged at the corner of two pixels PX of the repeating unit U, but the present invention does not take this as limit.

FIG. 8 shows a repeating unit U and a spacer 198 according to another embodiment of the present invention. In the embodiment of FIG. 8, the repeating unit U may be a pixel PX including a plurality of sub-pixels SPX, and the spacer 198 may be disposed at the corner of the plurality of sub-pixels SPX of the same pixel PX.

FIG. 9 shows a repeating unit U and a spacer 198 according to another embodiment of the present invention. In the embodiment of FIG. 9, the repeating unit U may be a combination of multiple pixels PX, and the spacers 198 may be disposed at multiple corners of the combination of multiple pixels PX.

10-1: The first backplane 10-2: The second backplane 100, 100A, 100B, 100C: active component substrate 100-1: The first active component substrate 100-2: The second active component substrate 110: Base 111: first surface 112: second surface 120: buffer layer 130: semiconductor pattern 140: gate insulation 150: gate 160: The first interlayer dielectric layer 172: Source 174: Dip pole 180: second interlayer dielectric layer 192: Transfer pattern 194: Insulation layer 196: Pad set 196a, 196b: pad 198: Spacer 200: sealant 210: The first line structure 211, 221: first barrier protection layer 212, 222: fan-out routing 213, 223: second barrier protection layer 214, 224: pad 220: Second line structure 310: The first protective layer 311: metal oxide sublayer 312: Insulator layer 320: second protective layer 330: The third protective layer AA: Range C: Pixel row D: thickness d1: first direction d2: second direction H: height PX: pixel R: pixel column SPX: Sub-pixel T: Active component U: repeat unit X1: the first central axis X2: second central axis

1A to 1J are schematic diagrams of a manufacturing process of a back plate according to an embodiment of the invention. 2 is a schematic top view of the base 110, pixels PX, and spacers 198 of the active device substrate 100 according to an embodiment of the invention. 3 is a schematic top view of the base 110 and its spacers 198 of the first active device substrate 100-1 and the base 110 and its spacers 198 of the second active device substrate 100-2 according to an embodiment of the present invention. 4 is a schematic top view of a base 110, pixels PX, and spacers 198 of another active device substrate 100A according to an embodiment of the invention. 5 is a schematic top view of the base 110, the pixels PX, and the spacers 198 of the active device substrate 100B according to another embodiment of the present invention. 6 is a schematic top view of the base 110, pixels PX, and spacers 198 of the active device substrate 100C according to another embodiment of the present invention. FIG. 7 shows the repeating unit U and the spacer 198 according to an embodiment of the present invention. FIG. 8 shows a repeating unit U and a spacer 198 according to another embodiment of the present invention. FIG. 9 shows a repeating unit U and a spacer 198 according to another embodiment of the present invention.

100: Active component substrate

100-1: The first active component substrate

100-2: The second active component substrate

110: Base

111: first surface

112: second surface

120: buffer layer

130: semiconductor pattern

140: gate insulation

150: gate

160: The first interlayer dielectric layer

172: Source

174: Dip pole

180: second interlayer dielectric layer

192: Transfer pattern

194: Insulation layer

196: Pad set

196a, 196b: pad

198: Spacer

200: sealant

D: thickness

H: height

T: Active component

Claims (7)

A manufacturing method of a backplane includes: A plurality of active device substrates are provided, wherein each of the active device substrates includes a base having a first surface and a second surface opposite to each other, an active device disposed on the first surface of the base, and an active device disposed on the active device. An insulating layer on the device, a pad group arranged on the insulating layer and electrically connected to the active device, and a spacer arranged on the insulating layer and located outside the pad group; A first active device substrate of the active device substrates and a second active device substrate of the active device substrates are connected by a sealant, wherein the first surface of the first active device substrate faces the second active device substrate The first surface of the first active device substrate, the spacer of the first active device substrate against the insulating layer of the second active device substrate, and the spacer of the second active device substrate against the insulation of the first active device substrate Layer, and the spacer of the first active device substrate is staggered from the spacer of the second active device substrate; Forming a first circuit structure on the second surface of the base of the first active device substrate when the sealant connects the first active device substrate and the second active device substrate; Forming a second circuit structure on the second surface of the base of the second active device substrate when the sealant connects the first active device substrate and the second active device substrate; and After forming the first circuit structure and the second circuit structure, remove the sealant to separate the first active device substrate from the second active device substrate, and form a first backplane and a second backplane Board, wherein the first backplane includes the first active device substrate and the first circuit structure disposed on the second surface of the first active device substrate, and the second backplane includes the second active device substrate And the second circuit structure disposed on the second surface of the second active device substrate. The manufacturing method of the backplane as described in claim 1, further including: After forming the first circuit structure and before forming the second circuit structure, a first protective layer is formed to cover the first circuit structure. The manufacturing method of the backplane as described in claim 2 further includes: After forming the second circuit structure and before separating the first active device substrate from the second active device substrate, a second protective layer is formed to cover the second circuit structure. The manufacturing method of the backplane as described in claim 3 further includes: After forming the second protective layer and before separating the first active device substrate from the second active device substrate, the first protective layer is removed. The manufacturing method of the backplane as described in claim 4 further includes: After removing the first protective layer and before separating the first active device substrate from the second active device substrate, a third protective layer is formed to cover the first circuit structure. The manufacturing method of the backplane according to claim 5, wherein the method of separating the first active device substrate from the second active device substrate includes: When the third protective layer and the second protective layer cover the first circuit structure and the second circuit structure, respectively, the part of the first active device substrate provided with the sealant and the second active device are cut away The substrate is provided with a part of the sealant. The manufacturing method of the backplane according to claim 1, wherein the height of the spacer of each active device substrate is greater than twice the thickness of a pad of the pad group of the active device substrate.

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