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TWI782411B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI782411B
TWI782411B TW110103939A TW110103939A TWI782411B TW I782411 B TWI782411 B TW I782411B TW 110103939 A TW110103939 A TW 110103939A TW 110103939 A TW110103939 A TW 110103939A TW I782411 B TWI782411 B TW I782411B
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Taiwan
Prior art keywords
insulating material
semiconductor
semiconductor device
opening
side portion
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TW110103939A
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English (en)
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TW202213704A (zh
Inventor
前田竹識
本間荘一
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日商鎧俠股份有限公司
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

提供一種即使將半導體晶片、控制器晶片及柱狀電極以樹脂密封仍能抑制基體的翹曲之半導體裝置及其製造方法。 半導體裝置，具備具有凹部之支撐部。複數個半導體晶片，被收容於支撐部的凹部內，而被層積於支撐部的底面上。複數個柱狀電極，從複數個半導體晶片向支撐部的開口側延伸。配線層，設於支撐部的開口側。絕緣材，被充填於支撐部的凹部內，被覆複數個半導體晶片及柱狀電極，介於複數個半導體晶片與配線層之間。

Description

半導體裝置及其製造方法
本實施形態有關半導體裝置及其製造方法。 關連申請案之引用 本申請案以依2020年6月19日申請之先行的日本國專利申請案第2020-106382號之優先權利益為基礎，且求取其利益，其內容全體藉由引用而被包含於此。
目前正在開發將複數個半導體晶片及控制器晶片構成為1個半導體封裝之MCP(Multi Chip Package；多晶片封裝)。
但，將半導體晶片及控制器晶片予以樹脂密封時，由於樹脂的熱收縮而有導致基體翹曲的問題。
提供一種即使將半導體晶片及控制器晶片以樹脂密封仍能抑制基體的翹曲之半導體裝置及其製造方法。
按照本實施形態之半導體裝置，具備具有凹部之支撐部。複數個半導體晶片，被收容於支撐部的凹部內，而被層積於支撐部的底面上。複數個柱狀電極，從複數個半導體晶片向支撐部的開口側延伸。配線層，設於支撐部的開口側。絕緣材，被充填於支撐部的凹部內，被覆複數個半導體晶片及柱狀電極，介於複數個半導體晶片與配線層之間。
按照上述構成，能夠提供一種即使將半導體晶片及控制器晶片以樹脂密封仍能抑制基體的翹曲之半導體裝置及其製造方法。
以下參照圖面說明本發明之實施形態。本實施形態並不限縮本發明。以下實施形態中，支撐部的上下方向，是示意當將搭載半導體晶片的面訂為上的情形之相對方向，可能和遵照重力加速度的上下方向相異。圖面為模型化或概念性質之物，各部分的比率等，未必限於和現實之物相同。說明書及圖面中，有關已揭露之圖面，對於和前述者相同的要素係標記同一符號並適當省略詳細說明。以下各實施形態中所謂的「硬」，亦可指布氏(Brinell)硬度、維氏(Vickers)硬度等的試驗中的硬。
(第1實施形態) 圖1為按照第1實施形態之半導體裝置1的構成的一例示意截面圖。半導體裝置1，具備支撐部10、複數個半導體晶片20、複數個接著層30、複數個柱狀電極40、再配線層(RDL(Redistribution Layer))50、電極墊60、金屬凸塊70、絕緣材80。半導體裝置1，例如亦可為NAND型快閃記憶體、LSI(Large Scale Integration；大型積體電路)等的半導體封裝。
支撐部10，具有凹部，被成形為框體狀。更詳細地說，支撐部10，具備搭載複數個半導體晶片20之底部10a、及設於底部的外緣之側部10b。本實施形態中，底部10a與側部10b係一體成形，由同一材料所構成。藉由底部10a及側部10b，支撐部10成為凹形狀，在其凹部內可收容半導體晶片20。
支撐部10，可為導電材料或絕緣材料的任一種，但由具有和絕緣材80相異硬度的材料所構成。在支撐部10，作為導電材料，例如亦可使用Cu、Ag、Au、Al、Mg、坡莫合金(permalloy)、Co等的金屬材料。在支撐部10，作為絕緣材料，例如亦可使用樹脂、塑膠、陶瓷、矽等的材料。
複數個半導體晶片20，被收容於支撐部10的凹部內，而被階梯狀地層積於支撐部10的底面F10上。複數個半導體晶片20，例如亦可為NAND型快閃記憶體的記憶體晶片或是搭載了任意的LSI的半導體晶片。複數個半導體晶片20，可為具有同一構成的半導體晶片，亦可為各自具有相異構成的半導體晶片。半導體晶片20，藉由接著層30而被接著於底面F10，或是相互接著。半導體晶片20中，表面F20為形成有半導體元件的元件形成面。作為元件形成面的表面F20，和再配線層50相向。反之，表面F20的相反側的背面係面向底面F10而被接著。
接著層30，為了將半導體晶片20接著於底面F10上而層積複數個半導體晶片20，係設於半導體晶片20與支撐部10的底面F10之間及半導體晶片20間。在接著層30，例如使用苯酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazoIe；聚苯並噁唑)系、矽氧系、苯並環丁烯系等的樹脂，或是由它們的混合材料、複合材料所成之DAF(Die Attach Film；晶粒黏結膜)或DAP(Die Attach Paste；晶粒黏結膠)。
柱狀電極40，從各半導體晶片20向支撐部10的開口OP10側延伸，將各半導體晶片20與再配線層50之間電性連接。柱狀電極40，從底面F10或半導體晶片20的表面(元件形成面)F20向略垂直方向延伸。柱狀電極40的一端連接至半導體晶片20的電極墊P20，其另一端連接至再配線層50的配線或電極墊P50。例如，半導體晶片20以階梯狀錯開層積，柱狀電極40從設於複數個半導體晶片20的端部的階差部分之電極墊P20的各者延伸。藉此，各半導體晶片20透過柱狀電極40直接連接至再配線層50，能夠透過再配線層50而與外部或內部的控制器等之間直接交換訊號。其結果，能夠使半導體晶片20間或半導體晶片20與控制器之間的通訊資料量或通訊速度增大。柱狀電極40例如亦可為用於打線之金屬線。在柱狀電極40，例如使用Au、Ag、Cu、CuPd等的低電阻金屬。
再配線層50，在支撐部10的開口OP10側，以堵塞開口OP10之方式設置。再配線層50，為將複數個層間絕緣膜51與複數個配線層52層積而成之多層配線構造。層間絕緣膜51，將設於配線層52間的配線層52間予以電性絕緣。在配線層52間的層間絕緣膜51，視必要設有通孔接點(via contact)53，將配線層52的配線間電性連接。在層間絕緣膜51，例如使用樹脂等的絕緣材料。在配線層52及通孔接點53，例如使用Cu、鎢等的低電阻金屬。
再配線層50，具有和複數個半導體晶片20及支撐部10的底面F10相向之背面F50a、與位於和背面F50a相反側之表面F50b。柱狀電極40，和位於背面F50a側的配線層52連接。另一方面，在位於表面F50b側的配線層52，可設置電極墊60，在電極墊60上設有金屬凸塊70。
電極墊60，設於再配線層50的配線層52的一部分之上，將金屬凸塊70電性連接至配線層52的一部分。在電極墊60，例如使用CU、鎢等的低電阻金屬。
金屬凸塊70，設於電極墊60上，係為了獲得與其他元件之電性連接而設置。在金屬凸塊70，例如使用焊料等的低電阻金屬。
絕緣材80，被充填於支撐部10的凹部內，被覆而保護半導體晶片20及柱狀電極40。半導體晶片20，未直接接著於再配線層50。是故，絕緣材80介於半導體晶片20的元件形成面F20與再配線層50之間，柱狀電極40將半導體晶片20與再配線層50之間電性連接。
也就是說，半導體晶片20並非層積於再配線層50上，而是層積於支撐部10的底面F10上。支撐部10的開口OP10的上端，比最上層的半導體晶片20的表面還高，絕緣材80充分埋入至最上層的半導體晶片20。藉此，絕緣材80介於半導體晶片20與再配線層50之間。絕緣材80，充填由支撐部10與再配線層50所圍繞的空間，而接觸再配線層50。
像以上這樣按照本實施形態之半導體裝置1，是在由底部10a與側部10b所成之支撐部10的凹部內收容了半導體晶片20及柱狀電極40之後，將半導體晶片20及柱狀電極40以絕緣材80密封。側部10b，抑制絕緣材80的流動的速度。故，當以絕緣材80將半導體晶片20及柱狀電極40密封時，側部10b在凹部內的半導體晶片20及柱狀電極40的鄰近或周圍能夠抑制絕緣材80(模塑樹脂)激烈流動。藉由抑制絕緣材80的流動，能夠抑制柱狀電極40的變形，使得從絕緣材80露出的先端部的位置穩定而不會不一致。
此外，支撐部10的材料，由具有和硬化的絕緣材80相異硬度的材料所構成。藉此，於硬化後當研磨絕緣材80時，支撐部10的側部10b的上端會作用成為研磨的止擋。支撐部10的材料，較佳是比硬化的絕緣材80還硬。藉此，支撐部10的側部10b能夠良好地作用成為絕緣材80的研磨的止擋，而能夠抑制削磨過度。另一方面，支撐部10的材料，亦可比硬化的絕緣材80還軟。在此情形下，支撐部10會變得比絕緣材80還易研磨，但因支撐部10與絕緣材80之研磨阻力相異，故研磨裝置能夠檢測支撐部10的側部10b的上端已經露出。是故，支撐部10的材料，只要是具有和硬化的絕緣材80相異硬度的材料即可，比絕緣材80還硬或還軟皆可。當側部10b的上端已露出時結束研磨，藉此抑制絕緣材80的殘留過度或削磨過度，能夠在半導體裝置1間使絕緣材80的厚度(樹脂的厚度)略均一化，而能夠抑制封裝的翹曲。
此外，將支撐部10的側部10b的上端作為止擋，藉此絕緣材80的厚度會自我對準(self-alignment)地和支撐部10的底面F10至側部10b的上端為止之高度相等。故，不需測定絕緣材80的厚度，產出量會加快。
此外，將支撐部10以比絕緣材80還硬的材料構成，藉此側部10b的上端會保護其周圍的絕緣材80，而抑制其過度研磨。藉此，會抑制絕緣材80的表面被大幅碟陷(dishing)(窪陷成碗型)，而能夠改善絕緣材80的平坦性。
此外，支撐部10的側部10b能夠補強半導體裝置1的封裝，而抑制其翹曲。
又，在支撐部10使用導電性材料，藉此支撐部10能夠具有對於電磁波噪訊或磁噪訊之屏蔽效果。例如，當支撐部10的材料為Cu、Ag、Au、Al、Mg等的情形下，支撐部10能夠具有作為電磁波屏蔽的機能。例如，當支撐部10的材料為坡莫合金、Co等的磁性體材料的情形下，支撐部10能夠具有作為磁屏蔽的機能，能夠截斷低頻噪訊。當將支撐部10用作為電磁屏蔽或磁屏蔽的情形下，支撐部10透過再配線層50而被接地。
接著，說明按照本實施形態之半導體裝置1的製造方法。
圖2A~圖6B為按照第1實施形態之半導體裝置1的製造方法的一例示意立體圖及截面圖。首先，如圖2A及圖2B所示，準備具有複數個凹部的支撐部10。支撐部10尚未被分片化(singulate)，構成作為支撐基板。支撐部10，具有底部10a與側部10b。側部10b，比底部10a還厚，其規定層積複數個半導體晶片20之凹部10c。本實施形態中，底部10a及側部10b係一體成形。是故，凹部10c例如可使用微影技術及蝕刻技術，藉由將平坦的支撐部10的表面削磨而形成。或是，凹部10c例如亦可使用雷射加工技術，藉由將平坦的支撐部10的表面削磨而形成。凹部10c為藉由底部10a及側部10b而被圍繞的空間，形成為比複數個半導體晶片20及複數個接著層30的全體的厚度還深。
例如，支撐部10的側部10b的厚度較佳為約200μm~約1000μm。支撐部10的底部10a的厚度較佳為約30μm~約200μm。當支撐部10的側部10b的厚度未滿約200μm的情形下，支撐部10的剛性太低，因此充填了絕緣材80之後，支撐部10會翹曲。若支撐部10的側部10b的厚度超過1000μm，則變得難以藉由絕緣材80(例如模塑樹脂)充填凹部10c。此外，當支撐部10的底部10a的厚度未滿30μm的情形下，會難以在底面F10上層積複數個半導體晶片20，以及保持該層積的半導體晶片20。若底部10a的厚度超過200μm，則充填了絕緣材80之後，支撐部10的翹曲雖會變小，但支撐部10的厚度會變厚，半導體裝置1的封裝的厚度會增大。是故，支撐部10的厚度較佳是以上述範圍形成。
側部10b的橫向寬幅(鄰接的凹部10c間的間隔)較佳為0.1mm以上。若未滿0.1mm，則側部10b的機械強度不足，形成了絕緣材80之後難以抑制支撐部10的翹曲。將側部10b的寬幅做成0.1mm以上，藉此會提高側部10b的機械強度，形成了絕緣材80之後能夠抑制支撐部10的翹曲。
接著，如圖2A及圖2B所示，在凹部10c的底面F10上層積複數個半導體晶片20。在各半導體晶片20的背面，事先貼附著接著層30。將半導體晶片20載置於底面F10上或其他的半導體晶片20上，藉此接著層30便會將半導體晶片20貼附於底面F10或其他的半導體晶片20上。此時，複數個半導體晶片20，以圖1的電極墊P20會露出之方式相互錯開配置而被層積成階梯狀。
接著，將柱狀電極40從半導體晶片20的電極墊P20朝向凹部10c的開口OP10側延伸形成。例如，柱狀電極40例如為金屬線，打線接合器藉由和打線接合近乎相同的方法將金屬線的一端連接至電極墊P20。另一方面，打線接合器將金屬線朝向相對於底面F10或半導體晶片20的表面而言略垂直方向拉出至比凹部10c的開口OP10(側部10b的上端)還上方，予以切斷。藉此，金屬線的另一端便被置放於比凹部10c的開口OP10還上方。亦即，柱狀電極40形成為從各半導體晶片20的電極墊P20朝向凹部10c的開口OP10略垂直地延伸，其上端位於比開口OP10還高的位置。柱狀電極40的金屬線，例如為具有約10μm~100μm的直徑之細金屬線。但，底面F10至開口OP10為止的高度(側部10b的厚度或凹部10c的深度)，例如為約30μm~1000μm這樣相對較低，故金屬線於凹部10c內能夠維持直立狀態。
接著，如圖3A及圖3B所示，在凹部10c內充填絕緣材80，將複數個半導體晶片20及複數個柱狀電極40以絕緣材80被覆。絕緣材80例如為樹脂，包覆模塑(overmolding)至比凹部10c的開口OP10(側部10b的上端)及柱狀電極40的上端還上方。藉此，半導體晶片20及柱狀電極40的全體被埋入絕緣材80內。
此時，半導體晶片20及柱狀電極40配置於凹部10c內，藉由側部10b而四方被圍繞。因此，以絕緣材80充填凹部10c內時，熔融的絕緣材80的流動會一定程度藉由側部10b而被遮擋。藉此，能夠抑制柱狀電極40倒塌。亦即，側部10b具有保護柱狀電極40及半導體晶片20免受熔融的絕緣材80的流動影響之機能。
絕緣材80的充填方法，可為模塑法，亦可為使用了片狀的膜之片狀模塑(sheet molding)。此外，絕緣材80的充填方法，亦可為塗布液狀樹脂之方法。絕緣材80充填後，使用紫外線等將其固化而使絕緣材80硬化。
接著，如圖4A及圖4B所示，研磨絕緣材直到支撐部10的側部10b的表面及柱狀電極40的上端露出。研磨，例如可使用CMP(Chemical Mechanical Polishing；化學機械研磨)法等來執行。如上述般，柱狀電極40的上端位於比側部10b的上端還高的位置。是故，若逐漸研磨絕緣材80，則首先柱狀電極40的上端會露出，其後支撐部10的側部10b的表面會露出。
另一方面，側部10b的上端位於比半導體晶片20的層積體還高的位置。是，當側部10b的表面露出時停止研磨，藉此在最上層的半導體晶片20上會殘留絕緣材80。故，柱狀電極40及側部10b雖會露出，但半導體晶片20會維持被絕緣材80被覆。
這裡，柱狀電極40是使用非常細的金屬線，故研磨工程中，研磨裝置難以檢測柱狀電極40露出。另一方面，支撐部10的側部10b，是在半導體裝置1的各封裝以外的區域跨比較廣的範圍而設置。是故，一旦側部10b露出則研磨阻力會變化，故研磨裝置藉由監控研磨阻力便能相對容易地檢測側部10b已經露出。當側部10b由比絕緣材80還硬的材料所構成的情形下，側部10b露出時研磨速度會降低，故會更有效地作用成為研磨止擋。是故，側部10b較佳是由比絕緣材80還硬的材料所構成。另一方面，當側部10b由比絕緣材80還軟的材料所構成的情形下，物理上無法使研磨速度降低。但，當側部10b露出時，研磨阻力會降低，故側部10b即使比絕緣材80還軟，仍能具有作為研磨止擋之機能。
接著，如圖5A及圖5B所示，在露出的柱狀電極40、側部10b及絕緣材80上形成再配線層50。再配線層50，是層積和柱狀電極40及側部10b電性連接的配線層52(參照圖1)、與將配線層52間絕緣的層間絕緣膜51而形成。配線層52的一部分，和柱狀電極40電性連接。此外，配線層52的其他一部分，和側部10b亦電性連接，以發揮支撐部10為導電性而支撐部10的電磁屏蔽效果或磁屏蔽效果。
接著，如圖5A及圖5B所示，在再配線層50上形成金屬凸塊(例如銲料球)70。金屬凸塊70，藉由熱處理而迴焊而連接至再配線層50的電極墊60(參照圖1)。
接著，如圖6A及圖6B所示，切斷支撐部10的側部10b，藉此將半導體裝置1分片化。側部10b，是使用切割刀或/及切割雷射而被切斷。藉由切斷側部10b的中心部，在被分片化的半導體裝置1的各封裝，會殘留底部10a及側部10b。是故，如圖1所示，支撐部10能夠在藉由底部10a及側部10b而形成的凹部內收容複數個半導體晶片20。依此方式，完成按照本實施形態之半導體裝置1的封裝。
按照本實施形態，當以絕緣材80將半導體晶片20及柱狀電極40密封時，支撐部10的側部10b會圍繞半導體晶片20及柱狀電極40的周圍。藉此，能夠抑制熔融的絕緣材80使柱狀電極40倒塌、屈曲。其結果，於絕緣材80的充填前後，從絕緣材80露出的柱狀電極40的先端部的位置不大變化而穩定。這會使得在再配線層50的形成中，配線層52與柱狀電極40之連接變得容易。
此外，支撐部10的材料，由具有和硬化的絕緣材80相異硬度的材料所構成。藉此，於絕緣材80的研磨工程中，支撐部10的側部10b的上端會作用成為研磨止擋。支撐部10的材料，只要會使絕緣材80的研磨阻力變化即可，比絕緣材80還硬或還軟皆可。藉此，會抑制絕緣材80的殘留過度或削磨過度，使絕緣材80的厚度(樹脂的厚度)略均一化，而能夠抑制封裝的翹曲。
此外，將支撐部10的側部10b的上端作為止擋，藉此絕緣材80的厚度會自我對準(self-alignment)地和支撐部10的底面F10至側部10b的上端為止之高度相等。故，不需測定絕緣材80的厚度，產出量會加快。
此外，將側部10b設置在半導體晶片20的周圍，且將側部10b由比絕緣材80還硬的材料構成，藉此會抑制絕緣材80的研磨面被碟陷(窪陷成碗型)，能夠改善絕緣材80的平坦性。藉此，會變得容易在絕緣材80上形成再配線層50。支撐部10的側部10b能夠補強半導體裝置1的封裝，也能抑制其翹曲。
又，在支撐部10使用導電性材料，藉此支撐部10能夠具有對於電磁波噪訊或磁噪訊之屏蔽效果。在此情形下，支撐部10透過再配線層50而被接地。
另，柱狀電極40是於半導體晶片20的層積後以打線接合法形成。但，柱狀電極40亦可藉由打線接合法或鍍覆法等而事先形成在各半導體晶片20，其後將半導體晶片20層積於支撐部10。
(變形例) 圖7為按照第1實施形態的變形例之半導體裝置1的構成例示意截面圖。第1實施形態中，半導體晶片20例如為具有同一構成之NAND記憶體晶片。但，半導體晶片20的一部分亦可具有相異的構成及尺寸。例如，圖7的半導體晶片21為控制NAND記憶體晶片(20)的控制器晶片。半導體晶片21，設於半導體晶片20的層積體之上，在支撐部10的凹部內成為最上層的半導體晶片。半導體晶片21亦同樣地透過柱狀電極40和再配線層50電性連接。像這樣，即使包含其他的半導體晶片21，仍不失本實施形態之效果。
(第2實施形態) 圖8為按照第2實施形態之支撐部10的構成例示意截面圖。按照第2實施形態之支撐部10，底部10a與側部10b構成為不同個體。底部10a及側部10b的材料，可和第1實施形態之支撐部10的材料相同。但，底部10a與側部10b可由同一材料亦可由相互相異的材料所構成。例如，亦可在底部10a使用樹脂材料，而在側部10b使用金屬材料。此外，反之亦可。於形成為不同個體時，例如亦可將底部10a與側部10b藉由接著層而貼合。或是，亦可藉由銲接、熔接、真空接合、常溫接合等而貼合。即使是金屬與樹脂材料這樣相異的材料亦可藉由一體成型而形成。此外亦能以各式各樣的方法將支撐部10以不同個體來形成。
側部10b，藉由未圖示之接著層等而被接著至底部10a。底部10a，搭載複數個半導體晶片20。複數個半導體晶片20，亦可在將側部10b接著至底部10a上之後，被層積於底面F10上。或是，複數個半導體晶片20，亦可在將側部10b接著至底部10a上之前，被層積於底面F10上。在此情形下，側部10b必需以不干涉半導體晶片20的層積體之方式接著。
底部10a與側部10b為不同個體，藉此底部10a及側部10b能夠個別地形成。在此情形下，底部10a可單純為平板狀的材料。側部10b，只要在平板狀的材料以衝壓加工等在規定的位置打穿即可。其後，在底部10a上將側部10b貼合。第2實施形態之支撐部10，不需使用微影技術、蝕刻技術或是雷射加工技術，故比較一體型的支撐部10其形成容易。
第2實施形態的其他構成，可和第1實施形態同樣。是故，第2實施形態能夠獲得和第1實施形態同樣的效果。
(第3實施形態) 圖9A~圖13B為按照第3實施形態之半導體裝置1的製造方法的一例示意立體圖或截面圖。第3實施形態中，柱狀電極40並非以打線接合法，而是使用鍍覆法等而於絕緣材80的形成後形成。
首先，如圖9A及圖9B所示，在凹部10c的底面F10上層積複數個半導體晶片20。半導體晶片20的層積方法，可和第1實施形態同樣。此時，尚未形成柱狀電極40。
接著，如圖10A及圖10B所示，在凹部10c內充填絕緣材80，將複數個半導體晶片20以絕緣材80被覆。絕緣材80的充填方法，可和第1實施形態同樣。
接著，如圖11A及圖11B所示，在絕緣材80藉由雷射等打穿孔H40。孔H40，形成於柱狀電極40的形成位置，以到達半導體晶片20的電極墊P20之方式形成。
接著，如圖12A及圖12B所示，將側部10b作為止擋而研磨絕緣材80。絕緣材80的研磨，可和第1實施形態同樣。藉此，側部10b的表面便露出。
接著，如圖13A及圖13B所示，在孔H40內埋入金屬材料，形成柱狀電極40。柱狀電極40，例如使用鍍覆法等而形成。藉此，柱狀電極40便從各半導體晶片20的電極墊P20至絕緣材80的表面為止。
其後，經由參照圖5A~圖6B而說明之工程，完成半導體裝置1的封裝。
如第3實施形態般，柱狀電極40亦可藉由鍍覆法來取代打線接合法而形成。第3實施形態中，柱狀電極40是將絕緣材80充填於凹部10c後才形成，故沒有因絕緣材80的流動而倒塌、屈曲之虞。是故，柱狀電極40的先端的位置，比第1實施形態更穩定。
(變形例) 圖14及圖15為按照第1實施形態的另一變形例之半導體裝置1的構成例示意截面圖。
圖14所示變形例中，當將支撐部10分片化成半導體裝置1時，會使用切割刀或/及切割雷射來切斷側部10b與絕緣材80之交界部或是比該交界部還靠絕緣材80側。藉此，在半導體裝置1的側面不會殘留側部10b，絕緣材80會露出。絕緣材80殘留於半導體晶片20的側面，而不會使半導體晶片20露出。像這樣，側部10b亦可於切割時被除去。藉此，能夠將半導體裝置1的封裝小型化。本變形例的其他的構成及製造方法，可和上述實施形態的任一構成及製造方法相同。
圖15所示變形例中，半導體裝置1的底部10a進一步被除去。在此情形下，是於切割支撐部10之前，將支撐部10的底部10a藉由CMP法等予以研磨、除去。半導體晶片20的底面係接觸支撐部10的底部10a，故藉由除去底部10a，在半導體裝置1不會殘留底部10a，半導體晶片20的背面會露出。其後，使用切割刀或/及切割雷射將支撐部10分片化成半導體裝置1。切割時，係切斷側部10b與絕緣材80之交界部或是比該交界部還靠絕緣材80側。藉此，在半導體裝置1的側面不會殘留側部10b，絕緣材80會露出。亦即，在完成後的半導體裝置1不會留下支撐部10。其結果，能夠將半導體裝置1的封裝進一步小型化。本變形例的其他的構成及製造方法，可和上述實施形態的任一構成及製造方法相同。
雖已說明了本發明的幾個實施形態，但該些實施形態僅是提出作為例子，並非意圖限定發明的範圍。該些實施形態，可以其他各種形態來實施，在不脫離發明要旨之範圍內，可進行種種省略、置換、變更。該些實施形態或其變形，均包含於發明之範圍或要旨中，同樣地包含於申請專利範圍所記載之發明及其均等範圍內。
1:半導體裝置 10:支撐部 10a:底部 10b:側部 10c:凹部 20:半導體晶片 30:接著層 40:柱狀電極 50:再配線層 51:層間絕緣膜 52:配線層 53:通孔接點 60:電極墊 70:金屬凸塊 80:絕緣材 F10:(支撐部10的)底面 F20:(半導體晶片20的)表面 F50a:(再配線層50的)背面 F50b:(再配線層50的)表面 OP10:(支撐部10的)開口 P20:(半導體晶片20的)電極墊 P50:(再配線層50的)電極墊
[圖1]為按照第1實施形態之半導體裝置的構成的一例示意截面圖。 [圖2A]為按照第1實施形態之半導體裝置的製造方法的一例示意立體圖。 [圖2B]為按照第1實施形態之半導體裝置的製造方法的一例示意截面圖。 [圖3A]為接續圖2A之半導體裝置的製造方法的一例示意立體圖。 [圖3B]為接續圖2B之半導體裝置的製造方法的一例示意截面圖。 [圖4A]為接續圖3A之半導體裝置的製造方法的一例示意立體圖。 [圖4B]為接續圖3B之半導體裝置的製造方法的一例示意截面圖。 [圖5A]為接續圖4A之半導體裝置的製造方法的一例示意立體圖。 [圖5B]為接續圖4B之半導體裝置的製造方法的一例示意截面圖。 [圖6A]為接續圖5A之半導體裝置的製造方法的一例示意立體圖。 [圖6B]為接續圖5B之半導體裝置的製造方法的一例示意截面圖。 [圖7]為按照第1實施形態的變形例之半導體裝置的構成例示意截面圖。 [圖8]為按照第2實施形態之支撐部的構成例示意截面圖。 [圖9A]為按照第3實施形態之半導體裝置的製造方法的一例示意立體圖。 [圖9B]為按照第3實施形態之半導體裝置的製造方法的一例示意截面圖。 [圖10A]為接續圖9A之半導體裝置的製造方法的一例示意立體圖。 [圖10B]為接續圖9B之半導體裝置的製造方法的一例示意截面圖。 [圖11A]為接續圖10A之半導體裝置的製造方法的一例示意立體圖。 [圖11B]為接續圖10B之半導體裝置的製造方法的一例示意截面圖。 [圖12A]為接續圖11A之半導體裝置的製造方法的一例示意立體圖。 [圖12B]為接續圖11B之半導體裝置的製造方法的一例示意截面圖。 [圖13A]為接續圖12A之半導體裝置的製造方法的一例示意立體圖。 [圖13B]為接續圖12B之半導體裝置的製造方法的一例示意截面圖。 [圖14]為按照第1實施形態的另一變形例之半導體裝置的構成例示意截面圖。 [圖15]為按照第1實施形態的另一變形例之半導體裝置的構成例示意截面圖。
1:半導體裝置
10:支撐部
10a:底部
10b:側部
20:半導體晶片
30:接著層
40:柱狀電極
50:再配線層
51:層間絕緣膜
52:配線層
53:通孔接點
60:電極墊
70:金屬凸塊
80:絕緣材
F10:(支撐部10的)底面
F20:(半導體晶片20的)表面
F50a:(再配線層50的)背面
F50b:(再配線層50的)表面
OP10:(支撐部10的)開口
P20:(半導體晶片20的)電極墊
P50:(再配線層50的)電極墊

Claims (10)

  1. 一種半導體裝置，具備：支撐體，具有底部與側部，在前述底部的相反側形成有開口部；複數個半導體晶片，被收容於前述支撐體；絕緣材，被充填於前述支撐體，而覆蓋前述複數個半導體晶片；複數個柱狀電極，從前述複數個半導體晶片向開口部側延伸，至少一部分被前述絕緣材覆蓋；及配線層，設於前述開口部側，一部分亦形成於前述側部之上，和前述複數個柱狀電極連接。
  2. 如請求項1記載之半導體裝置，其中，前述支撐體，由導電性材料、磁性體材料、樹脂或陶瓷所成。
  3. 如請求項1記載之半導體裝置，其中，前述柱狀電極，將形成於前述複數個半導體晶片的墊與前述配線層之間電性連接。
  4. 如請求項1記載之半導體裝置，其中，前述支撐體，硬度和前述絕緣材相異。
  5. 如請求項1記載之半導體裝置，其中，前述複數個半導體晶片，藉由接著層被接著於前述底部。
  6. 如請求項1記載之半導體裝置，其中，前述底部和前述側部為一體。
  7. 如請求項1記載之半導體裝置，其中，前 述底部和前述側部為不同個體。
  8. 如請求項1至請求項7的任一項記載之半導體裝置，其中，前述複數個半導體晶片，以階梯狀錯開而被層積，前述複數個柱狀電極，從前述複數個半導體晶片的端部的階差部分的各者延伸。
  9. 一種半導體裝置的製造方法，包含：在具有底部與側部而在前述底部的相反側形成有開口部之支撐體的內部，收容複數個半導體晶片，從前述複數個半導體晶片朝向凹部的前述開口部形成柱狀電極，在前述支撐體充填絕緣材，而將前述複數個半導體晶片及前述柱狀電極的至少一部分藉由前述絕緣材被覆，研磨前述絕緣材直到前述側部的前述開口部側的面及前述柱狀電極的至少一部分露出，在前述開口部側形成配線層而亦在前述側部之上形成一部分。
  10. 一種半導體裝置的製造方法，包含：在具有底部與側部而在前述底部的相反側形成有開口部之支撐體的內部，收容複數個半導體晶片，在前述支撐體充填絕緣材，而將前述複數個半導體晶片藉由前述絕緣材被覆，研磨前述絕緣材直到前述側部的前述開口部側的面露出， 在前述絕緣材形成到達前述複數個半導體晶片的孔，在前述孔形成金屬材料而形成柱狀電極，在前述開口部側形成配線層。
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