TWI628919B - Sar analog to digital converter - Google Patents

Abstract

A continuous progressive analog-to-digital converter includes a sample and hold circuit group, a capacitor array group, a plurality of dynamic comparators, and a SAR control circuit. The sample and hold circuit group is configured to sample a analog signal to generate a sample signal. The capacitor array group has a signal capacitor array and a reference capacitor array, wherein the signal capacitor array has a plurality of non-binary arrayed capacitor bits, and at least two capacitor bits are simultaneously switched in one cycle, at least one set of capacitor bits The signal capacitor array outputs a signal voltage, and the reference capacitor array outputs a reference voltage. The dynamic comparator compares the signal voltage and the potential of the reference voltage and outputs a comparison signal. The SAR control circuit controls switching of the capacitor array group according to the comparison signals of the dynamic comparators.

Description

Continuous progressive analog digital converter

This invention relates to an analog digital converter, and more particularly to a continuous progressive analog digital converter.

Please refer to FIG. 1 , which is a circuit diagram of a continuous progressive analog-to-digital converter including a sample and hold circuit, a comparator, a digital analog converter and a control logic circuit. Wherein, a type of analog signal V _{IN is} input to the sample and hold circuit for sampling and maintaining the sampled voltage, and the voltage held by the sample and hold circuit is input to the positive terminal of the comparator, and the control logic circuit causes the digital analog converter to output a reference. Voltage to the negative terminal of the comparator, the comparator compares the magnitude of the voltage and the reference voltage, and outputs 1 or 0 to the control logic circuit, the control logic circuit stores the comparison result of the comparator, and according to the comparison result Determining the magnitude of the reference voltage for the next cycle, the control logic circuit finally outputs the digital signals D ₀ , D ₁ ... D _N-2 and D _N-1 , so if it is an analog converter of N-bit resolution, then It takes N comparisons to complete the conversion of a piece of data.

The main object of the present invention is to provide an analog digital converter having a two-element switching capacitor bit in one cycle and a one-element switching capacitor bit in one cycle, which can improve the analog digital position while maintaining high resolution. The conversion speed of the converter. In addition, the analog-to-digital converter has a non-binary array of capacitors, which increases the range of fault tolerance during switching to improve the conversion speed of the analog-to-digital converter.

A continuous progressive analog-to-digital converter of the present invention includes a sample and hold circuit group, a capacitor array group, a plurality of dynamic comparators, and a SAR control circuit. The sample and hold circuit group receives an analog signal, and the sample and hold circuit group The analog array is configured to generate a sampling signal, and the capacitor array is electrically connected to the sampling and holding circuit to receive the sampling signal, the capacitor array group has a signal capacitor array and a reference capacitor array, wherein the capacitor array The signal capacitor array has a plurality of non-binary arrayed capacitor bits, and at least two capacitor bits are simultaneously switched in one cycle, at least one set of capacitor bits are individually switched in another cycle, and the signal capacitor array outputs a signal a voltage, the reference capacitor array outputs a reference voltage, the dynamic comparators are electrically connected to the capacitor array group to receive the signal voltage and the reference voltage, and the dynamic comparator is configured to compare the signal voltage and the potential of the reference voltage, and Each of the dynamic comparators outputs a comparison signal, and the SAR control circuit is electrically connected to the capacitor Column groups, and the plurality of dynamic comparator, the control circuit switches the capacitive SAR array group based on the comparison of the control signal of the plurality of dynamic comparator.

The continuous progressive analog-to-digital converter of the invention simultaneously maintains the fast conversion of two-bit switching and the high-precision conversion of one-bit switching, and can improve the conversion speed while maintaining high resolution, and can Suitable for applications such as wireless communication that require fast conversion.

Referring to FIG. 2, a block diagram of a continuous progressive analog-to-digital converter 100 includes a sample and hold circuit group 110, a capacitor array group 120, and an active progressive analog-to-digital converter 100, in accordance with an embodiment of the present invention. A plurality of dynamic comparators 130, a SAR control circuit 140, a register set 150, an error detection circuit 160, a non-binary code conversion circuit 170, a digital code replacement circuit 180, and a decoder 190.

Referring to FIG. 2, in the embodiment, the continuous progressive analog-to-digital converter 100 is a differential continuous progressive analog-to-digital converter. Therefore, the sample-and-hold circuit group 110 has a first sample-and-hold circuit 111. And a second sample-and-hold circuit 112, the first sample-and-hold circuit 111 receives an analog signal V _ip , and the second sample-and-hold circuit 112 receives an inverting analog signal V _in , the first sample-and-hold circuit 111 and the first The second sample and hold circuit 112 samples and holds the analog signal V _ip and the inverted analog signal V _in respectively. Referring to FIG. 3 , the circuit of the first sample and hold circuit 111 and the second sample and hold circuit 112 . a schematic view, which includes a switch and a charging capacitor, when the clock signal CLK turns on the switch of the sample and hold circuit is sampling phase, an input signal V _n to charge the charging capacitor, the potential of the charging capacitor rises to the input signal V _n the potential size of the sample and hold circuit when the clock signal CLK to switch off the hold phase, the output voltage V _out of the charging capacitor to the potential holding input The potential of the signal V _n .

Referring to FIG. 2, in the embodiment, the capacitor array group 120 includes a first capacitor array group 121 and a second capacitor array group 122. The first capacitor array group 121 has a signal capacitor array 121a and a reference. The second capacitor array 122 has a signal capacitor array 122a and a reference potential capacitor array 122b. The signal capacitor array 121a of the first capacitor array group 121 is electrically connected to the first sample and hold circuit. The signal capacitor array 122a of the second capacitor array group 122 is electrically connected to the second sample and hold circuit 112 to receive the second sample and hold circuit. The sample signal held by 112.

Referring to FIG. 4, a circuit diagram of the signal capacitor array 121a of the first capacitor array group 121 and the signal capacitor array 122a of the second capacitor array group 122, wherein the signal capacitor array of the first capacitor array group 121 The signal capacitor array 122a of the second capacitor array group 122 forms a differential pair, and the operation of the two capacitor arrays is reversed, wherein the voltage of one capacitor array rises and the voltage of the other capacitor array decreases. This approach keeps the common-mode voltage of the signal consistent. In addition, the capacitor capacitor array 121a of the first capacitor array group 121 and the capacitor capacitors of the signal capacitor array 122a of the second capacitor array group 122 are divided into upper and lower portions, which can reduce the complexity of the switch circuit. And reduce the load on the switching circuit.

In this embodiment, the signal capacitor array has 12 capacitor bits, and the 12 capacitor bits are arranged in sizes of 512, 256, 192, 96, 64, 32, 16, 8, 4, 4, 2, and 1. It can be seen that the capacitor bits of the present invention are not binary arrangements. The capacitance bit size 192 is 128 for the traditional binary plus 64 bits, and the size of the capacitor bit 96 is 64 for the conventional binary plus 32 bits, while the second capacitor with a capacitance of 4 is redundant. Redundancy capacitors, which increase the error-tolerant range of the signal capacitor array, thereby increasing the overall analog-to-digital conversion speed.

Preferably, the first 16 capacitive bits 512, 256, 192, 96, 64, 32, 16 and 8 of the signal capacitor array of the present invention are monotonically switched in a two-bit manner. That is, switching between two capacitor bits in one cycle to control the rise or fall of the voltage, and the last four capacitor bits 4, 4, 2, and 1 of the signal capacitor array are one bit at a time. The mode is switched, that is, a capacitor bit is switched in a cycle, so that the continuous progressive analog-to-digital converter 100 can simultaneously maintain a fast conversion of two-bit switching and a high-precision conversion of one-bit switching. efficacy.

Referring to FIG. 5, it is a circuit diagram of the reference potential capacitor array 121b of the first capacitor array group 121 and the reference potential capacitor array 122a of the second capacitor array group 122. Each of the reference potential capacitor arrays has six capacitor positions. The capacitance of 20C is used to compensate the error between the reference potential capacitor array and the redundant capacitor in the signal capacitor array, and the capacitors of 96C, 20C, 8C, 3C and 1C are used to generate the reference voltage V _refp , V _refn , and the reference voltages V _refp , V _{refn are} further used to generate reference potentials V _REF+ , V _REF− for comparison of four potentials of the first two capacitors of the first eight capacitor bits of the signal capacitor array, four The potentials are 1/2V _REF , 3/16V _REF , 1/16V _REF and 1/64V _REF , respectively, in this embodiment, V _REF+ =V _refp -V _refn , V _REF- =V _refp +V _refn , using a change in capacitance charge of the determined potential size, wherein the reference calculation equation potential capacitor arrays can be expressed as: V _REF + ((capacitance _{value) / 128) * V cm =} V refp and V _REF + ((capacitance value) / 128 *V _cm =V _refn , and the magnitude of the potential can be obtained by adjusting the switches.

Please refer to FIG. 2 again, the signal capacitor array 121a of the first capacitor array group 121 and the reference potential capacitor array 121b and the signal capacitor array 122a of the second capacitor array group 122 and the reference potential capacitor array 122b. The signal voltages and the reference voltages are sent to the dynamic comparators 130 for potential comparison. In this embodiment, there are a total of three dynamic comparators to compare the signals to the first capacitor array group 121. The signal voltages of the capacitor array 121a and the reference potential capacitor array 121b and the signal capacitor array 122a of the second capacitor array group 122 and the reference potential capacitor array 122b and the potential magnitudes of the reference voltages, and each of the dynamic comparisons One of the output signals of the device 130 is sent to the register group 150 for storage, and the comparison signal is sent to the SAR control circuit 140 for determination, so that the SAR control circuit 140 outputs control signals to the capacitor array group 120 and the respective The dynamic comparator 130 performs control.

Referring to FIG. 2, in the embodiment, the first 8 bits are switched by two cycles in one cycle, and three dynamic comparators are needed for comparison at the same time, and errors are more likely to occur, and one of the dynamic comparators is A comparison signal and an inverted signal of the comparison signal are outputted. Therefore, it is possible to detect whether the dynamic comparators have an error. If the comparison signal and its inverted signal are both low, it indicates that an error has occurred. Preferably, the error detection circuit 160 captures the comparison signal and the inverted comparison signal from the register group 150 for error detection, and transmits an error detection signal to the digital code. Replace the circuit 180.

Referring to FIG. 2, the non-binary code conversion circuit 170 receives the comparison signals from the register group 150. Since the signal capacitor array has a total of 12 capacitance bits, the non-binary code conversion circuit 170 outputs the comparison signals according to the comparison signals. A 12-bit non-binary digit signal, and the non-binary code conversion circuit 170 transmits the non-binary digit signal to the error code replacement circuit.

Referring to FIG. 2, the digital code replacement circuit 180 receives the error detection signal of the error detection circuit 160 and the non-binary digital signal of the non-binary code conversion circuit 170, and corrects the non-binary digital signal according to the error detection signal. If an error occurs in the display, for example, if the error detection signal indicates that the 8th bit has an error, the 7 bits representing the subsequent comparison are all errors, so the digital code replaces the circuit 180 directly with a prediction. The data replaces the 8 bits of the non-binary digital signal. This way, the continuous progressive analog digital converter 100 can be prevented from being stopped due to the error comparison, so as to greatly increase the conversion speed of the continuous progressive analog digital converter 100. .

Referring to FIG. 2, the decoder 190 receives the non-binary digit signal by the digit code replacement circuit 180. Since the non-binary digit signal further includes a redundant capacitor and an additional valid bit, the decoder 190 will The 12-bit non-binary digit signal is converted to a 10-bit binary digit signal Digital.

The continuous progressive analog-to-digital converter 100 of the present invention simultaneously maintains the fast conversion of two-bit switching and the high-precision conversion of one-bit switching, and can improve the conversion speed while maintaining high resolution. It can be applied to applications such as wireless communication that require fast conversion.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Continuous progressive analog digital converter

110‧‧‧Sampling and holding circuit group

111‧‧‧First sample hold circuit

112‧‧‧Second sample and hold circuit

120‧‧‧Capacitor array group

121‧‧‧First Capacitor Array Group

121a‧‧‧ Signal Capacitor Array

121b‧‧‧Reference potential capacitor array

122‧‧‧Second capacitor array

122a‧‧‧Signal Capacitor Array

122b‧‧‧Reference potential capacitor array

130‧‧‧Dynamic comparator

140‧‧‧SAR control circuit

150‧‧‧storage group

160‧‧‧Error detection circuit

170‧‧‧Non-binary code conversion circuit

180‧‧‧Digital code replacement circuit

190‧‧‧Decoder

V _ip ‧‧‧ analog signal

V _in ‧‧‧Inverse analog signal

V _n ‧‧‧ input signal

Common mode voltage V _cm ‧‧‧

Inpp‧‧‧ signal voltage

Innn‧‧‧Signal voltage

Digital‧‧‧ binary digit signal

V _IN ‧‧‧ analog signal

CLK‧‧‧ clock signal

V _out ‧‧‧output voltage

V _{refp ‧‧‧reference} voltage

V _{refn ‧‧‧reference} voltage

Figure 1: A functional block diagram of a continuous progressive analog digital converter. 2 is a functional block diagram of a continuous progressive analog digital converter in accordance with an embodiment of the present invention. Figure 3 is a circuit diagram of a sample and hold circuit in accordance with an embodiment of the present invention. Figure 4 is a circuit diagram of a signal capacitor array in accordance with an embodiment of the present invention. Figure 5 is a circuit diagram of a reference potential capacitor array in accordance with an embodiment of the present invention.

Claims (9)

A continuous progressive analog-to-digital converter includes: a sample-and-hold circuit group that receives an analog signal, and the sample-and-hold circuit group samples the analog signal to generate a sample signal; a capacitor array group, The sampling and holding circuit is configured to receive the sampling signal, the capacitor array group has a signal capacitor array and a reference capacitor array, wherein the signal capacitor array has a plurality of non-binary arrayed capacitor bits, and at least two capacitor bits Switching simultaneously in one cycle, at least one set of capacitor bits is individually switched in another cycle, the signal capacitor array outputs a signal voltage, the reference capacitor array outputs a reference voltage; a plurality of dynamic comparators, electrically connected The capacitor array is configured to receive the signal voltage and the reference voltage, the dynamic comparator is configured to compare the signal voltage and the potential of the reference voltage, and each of the dynamic comparators outputs a comparison signal; a SAR control circuit electrically connected to the a capacitor array group and the dynamic comparators, the SAR control circuit is based on the dynamic comparators The comparison signal controls switching of the capacitor array group; a register group electrically connected to the dynamic comparators to store the comparison signals; and an error detection circuit electrically connected to the register group for receiving The comparison signals are stored in the register group, and the error detection circuit is configured to detect whether the comparison signals have an error to output an error detection signal. The continuous progressive analog-to-digital converter of claim 1, wherein the sample-and-hold circuit group has a first sample-and-hold circuit and a second sample-and-hold circuit, and the first sample-and-hold circuit receives the analog signal. The second sample and hold circuit receives the analog signal of the inversion. A continuous progressive analog digital converter as described in claim 2, which comprises The first capacitor array is electrically connected to the first sample-and-hold circuit, and the signal capacitor array of the second capacitor array is electrically connected to the first capacitor array. A second sample hold circuit. The continuous progressive analog-to-digital converter according to claim 1, comprising a non-binary code conversion circuit electrically connected to the register group to convert the comparison signals into one Non-binary digit signal. The continuous progressive analog-to-digital converter according to claim 4, comprising a digital code replacement circuit electrically connected to the error detection circuit and the non-binary code conversion circuit to The detection signal corrects the non-binary digital signal. The continuous progressive analog-to-digital converter of claim 5, comprising a decoder electrically coupled to the digital code replacement circuit, the decoder for converting the non-binary digital signal into a binary digit Signal. The continuous progressive analog-to-digital converter of claim 1, wherein the signal capacitor array has 12 capacitor bits. The continuous progressive analog-to-digital converter according to claim 7, wherein the capacitor bits are arranged in sizes of 512, 256, 192, 96, 64, 32, 16, 8, 4, 4, 2, and 1. A continuous progressive analog-to-digital converter includes: a sample-and-hold circuit group that receives an analog signal, and the sample-and-hold circuit group samples the analog signal to generate a sample signal; a capacitor array group, The sampling and holding circuit is configured to receive the sampling signal, the capacitor array group has a signal capacitor array and a reference capacitor array, wherein the signal capacitor array has a plurality of non-binary arrayed capacitor bits, and at least two capacitor bits Switching simultaneously in one cycle, at least A set of capacitor bits are separately switched in another cycle, the signal capacitor array outputs a signal voltage, and the reference capacitor array outputs a reference voltage, wherein the signal capacitor array has 12 capacitor bits, and the capacitor bits The size is arranged to be 512, 256, 192, 96, 64, 32, 16, 8, 4, 4, 2, and 1; a plurality of dynamic comparators are electrically connected to the capacitor array group to receive the signal voltage and the reference voltage The dynamic comparator is configured to compare the signal voltage and the potential of the reference voltage, and each of the dynamic comparators outputs a comparison signal; and a SAR control circuit electrically connected to the capacitor array group and the dynamic comparators, the SAR The control circuit controls switching of the capacitor array group according to the comparison signals of the dynamic comparators.