CN107786206A - Pipeline SAR-ADC system - Google Patents
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- CN107786206A CN107786206A CN201711228776.9A CN201711228776A CN107786206A CN 107786206 A CN107786206 A CN 107786206A CN 201711228776 A CN201711228776 A CN 201711228776A CN 107786206 A CN107786206 A CN 107786206A
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- 239000003990 capacitor Substances 0.000 claims description 26
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- 238000010586 diagram Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- BWSIKGOGLDNQBZ-LURJTMIESA-N (2s)-2-(methoxymethyl)pyrrolidin-1-amine Chemical compound COC[C@@H]1CCCN1N BWSIKGOGLDNQBZ-LURJTMIESA-N 0.000 description 2
- UGAJKWZVPNVCIO-UHFFFAOYSA-N Terminalin Chemical compound O1C(=O)C(C2=3)=C(C4=C(O)C(O)=C(O)C=C4C(=O)O4)C4=C(O)C=3OC(=O)C3=C2C1=C(O)C(OC1=O)=C3C2=C1C=C(O)C(O)=C2O UGAJKWZVPNVCIO-UHFFFAOYSA-N 0.000 description 1
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- 238000005215 recombination Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention discloses a Pipeline SAR-ADC system, which comprises successive approximation type analog-to-digital conversion modules and a register, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register. The successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline type for output. The invention has the advantages of less used components, convenient realization, low cost and capability of improving the output rate and the resolution ratio during application.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a Pipeline SAR-ADC system.
Background
An analog-to-digital converter (ADC) is a key device for converting an analog signal into a digital signal, and plays a crucial role in the fields of aerospace and defense, automotive applications, software radio, consumer electronics, video monitoring and image acquisition, radar communication, and the like. With the continuous development of modern technology, the requirements of the fields on speed and resolution are continuously increased, and the requirements on the analog-digital converter are higher and higher.
The traditional analog-to-digital converter often adopts a Pipeline-ADC structure and an SAR-ADC structure, wherein the Pipeline-ADC structure has the following defects when being applied: first, the Pipeline-ADC is greatly affected by capacitance mismatch, which results in a great limitation on the Pipeline-ADC resolution; secondly, the Pipeline-ADC needs to be equipped with an error correction module, which increases the power consumption and area of the ADC, and limits its application in the fields of industrial control and the like. The SAR-ADC structure has the following disadvantages when applied: the SAR-ADC adopts a gradual approximation type voltage comparison method, so that the SAR-ADC cannot be applied to a high-speed environment, namely the sampling rate of the SAR-ADC is low.
Disclosure of Invention
The invention aims to solve the problems of low resolution and low sampling rate of the traditional analog-to-digital converter, and provides a Pipeline SAR-ADC system which has the advantage of structural combination of Pipeline and SAR-ADC and can improve the output rate and resolution.
The invention mainly solves the problems by the following technical scheme: a Pipeline SAR-ADC system comprises successive approximation type analog-to-digital conversion modules and a register, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register; wherein,
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register;
and the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form for output.
Furthermore, the successive approximation type analog-to-digital conversion module comprises two sampling switches, two capacitor arrays, two comparators, a logic control module and an output buffer module, wherein the two sampling switches are connected with the input ends of the two capacitor arrays in a one-to-one correspondence manner, and the output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
Furthermore, a signal amplifying circuit is arranged on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
In conclusion, the invention has the following beneficial effects: (1) the invention has simple integral structure, less used components, convenient realization and low cost, and can effectively improve the output rate of the ADC by combining the SAR-ADC circuit structure with the Pipeline operation mode.
(2) The invention adopts a fully differential structure, and can reduce the noise and the interference of capacitor mismatch.
(3) The invention can divide the full range from the maximum (first stage) to the minimum (N stages) by dividing the range step by step when being applied, each stage is converted by the SAR-ADC, and then the Pipeline type recombination output is formed, so that the resolution of the final output is greatly improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a block diagram of one embodiment of the present invention;
FIG. 2 is a block diagram of a successive approximation analog-to-digital conversion module according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating the overall voltage simulation results according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a simulation result of local voltages according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1:
as shown in fig. 1, a Pipeline SAR-ADC system includes successive approximation type analog-to-digital conversion modules and a register, where the number of successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, and the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N stages. In this embodiment, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input in all successive approximation type analog-to-digital conversion modules, and the order of signals input by the N-order successive approximation type analog-to-digital conversion module is as follows: a first order successive approximation type analog-to-digital conversion module, a second order successive approximation type analog-to-digital conversion module, … … and an Nth order successive approximation type analog-to-digital conversion module. In the specific setting of this embodiment, a signal amplifying circuit is disposed on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
The structure of fig. 1 shows that N successive approximation type digital-to-analog conversion modules are operated in a pipeline type manner, and compared with the conventional successive approximation type digital-to-analog converter, the system can remarkably improve the analog-to-digital conversion speed. Fig. 2 shows that the system is a differential structure, and compared with a traditional successive approximation type digital-to-analog converter, the differential input differential comparison structure can effectively inhibit the influence of input noise on an output result. In addition, the differential structure can effectively reduce the influence of signal common-mode errors on the output.
In this embodiment, the digital output end of each successive approximation type analog-to-digital conversion module is connected to the input end of the register, and the successive approximation type analog-to-digital conversion module is configured to convert an analog signal input thereto into a digital signal and send the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline type for output.
When the embodiment is applied, the analog input signal VinEntering a first-order successive approximation type analog-to-digital conversion module, and converting the analog signal into N through the first-order successive approximation type analog-to-digital conversion module1Bit digital signal D1Store to the register. The residual voltage V output by the first-order successive approximation type analog-to-digital conversion moduleo1Amplified into a voltage V by a signal amplifying circuiti2Voltage V ofi2Converting the analog signal into N by a second-order successive approximation type analog-to-digital conversion module2Bit digital signal D2The residual voltage V is stored in a register and output by a second-order successive approximation type analog-to-digital conversion moduleo2Amplified into a voltage V by a signal amplifying circuiti3. By analogy, the input signal V is input in the last orderiNAfter entering the Nth order successive approximation type analog-to-digital conversion module, the analog signal is converted into NnBit digital signal Dn. Finally D1，D2…DnIn Pipeline) Form combined output (N)1+N2+…+Nn) Bit digital signal Dout。
Example 2:
as shown in fig. 2, the present embodiment is further defined on the basis of embodiment 1 as follows: the successive approximation type analog-to-digital conversion module of the embodiment includes a sampling switch, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the capacitor array is provided with IN, OUT, G, H, L and C1-NThe pin and the logic control module are provided with IN, OUT, CLK and C1(1-N)And C2(1-N)And (7) a pin. In this embodiment, the number of the sampling switches and the number of the capacitor arrays are two, and the two sampling switches are sampling switches SAMP respectively1And a sampling switch SAMP2SAMP switch1And a sampling switch SAMP2Respectively connected with IN input ends of two capacitor arrays IN one-to-one correspondence, and input voltage Vip(t)By sampling switches SAMP1Input, input voltage Vin(t)By sampling switches SAMP2And (4) inputting. And OUT output ends of the two capacitor arrays are respectively connected with a non-inverting input end and an inverting input end of the comparator. The output end of the comparator is connected with the input end of the IN of the logic control module, and the C of the logic control module1(1-N)Digital control output and C of a capacitor array1-NC of digital bit control input end connection and logic control module2(1-N)C of digital control output end and another capacitor array1-NThe digital bit control input end is connected, and the OUT output end of the logic control module is connected with the input end of the output buffer module.
When the embodiment is applied, the reference high voltage V is input into the H ends of the two capacitor arraysrefHThe L ends of the two capacitor arrays are input with a reference low voltage VrefLThe G ends of the two capacitor arrays are input with a ground voltage GND, and the CLK Clock input end of the logic control module is input with a Clock signal. At the sampling phase, the sampling switch SAMP1SAMP (sampling switch)2Closed, differential positive input voltage Vip(t)By sampling switch SAMP1Form Vip(z)Entering a capacitor array, inputting a voltage V at the negative terminalin(t)By sampling switch SAMP2Form Vin(z)Into another capacitor array. Sampling switch SAMP during the comparison phase1SAMP (sampling switch)2Disconnecting, the comparator CMP compares the output voltages V of the two capacitor arrayspAnd VnThereby determining the output logic D of the comparator CMPcmpAnd inputting the data to a logic control module. The logic control module is input to the IN input end of the logic control module according to the output voltage value, and the logic control module is connected with the output end of the output voltage1(1-N)Outputting control signals of corresponding digital positions to a control port C of a capacitor array1-NAnd from C2(1-N)Outputting control signals of corresponding digital positions to a control port C of another capacitor array1-NAnd further eliminating charges stored in the two capacitor arrays corresponding to the digital position, and simultaneously recording corresponding digital data of the digital position. After one comparison procedure is completed, the logic control module eliminates the charges stored in the capacitor array in the same way in successive cycles to complete the output data of all digital positions, and finally outputs the final digital data D in a pipeline (pipeline) formout. The output buffer signal D of the output buffer module can be selectively added according to specific requirementsbout。
The embodiment applies and realizes a 16-bit Pipeline SAR-ADC system, the sampling rate of which is 33kHz, the reference voltage is 2.5V, and the input signal is changed from 0V to 2.5V. The output result is that the significant digit (ENOB) reaches 16 bits, the Integral Nonlinearity (INL) is less than 0.5LSB, and the Differential Nonlinearity (DNL) is less than 0.5 LSB. Fig. 3 and 4 are simulation diagrams of an example application of the circuit. The simulation method is that the output digital signal of the 16-bit Pipeline SAR-ADC system passes through an ideal DAC, and the analog signal output by the DAC is compared with the input analog signal. Wherein the upper line in the coordinate system shown in fig. 3 is the voltage input signal varying from 0V to 2.5V and the lower line is the analog signal into which the circuit converts the output digital signal. As can be seen from fig. 3, the voltage output signal of the circuit varies linearly and substantially corresponds to the voltage input signal. Fig. 4 is a graph of the results of local voltage simulation, where the flatter lines are the input analog signals and the more tortuous lines are the analog signals converted from the output digital signals. As can be seen from the figure, the analog signal converted from the output digital signal is substantially stepped, and is expected.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (3)
1. A Pipeline SAR-ADC system is characterized by comprising successive approximation type analog-to-digital conversion modules and a register, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register; wherein,
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register;
and the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form for output.
2. The Pipeline SAR-ADC system of claim 1, wherein the successive approximation type analog-to-digital conversion module comprises two sampling switches, two capacitor arrays, two comparators, a logic control module and an output buffer module, the two sampling switches are connected with the input ends of the two capacitor arrays in a one-to-one correspondence manner, and the output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
3. The Pipeline SAR-ADC system of claim 1 or 2, wherein a signal amplifying circuit is arranged on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
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Cited By (2)
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