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TWI624016B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI624016B
TWI624016B TW106127763A TW106127763A TWI624016B TW I624016 B TWI624016 B TW I624016B TW 106127763 A TW106127763 A TW 106127763A TW 106127763 A TW106127763 A TW 106127763A TW I624016 B TWI624016 B TW I624016B
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TW
Taiwan
Prior art keywords
packaging layer
electronic package
layer
interposer
item
Prior art date
Application number
TW106127763A
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English (en)
Other versions
TW201911500A (zh
Inventor
蔡文山
鄭子企
林長甫
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW106127763A priority Critical patent/TWI624016B/zh
Priority to CN201710784754.4A priority patent/CN109411418B/zh
Priority to US15/860,222 priority patent/US20190057917A1/en
Application granted granted Critical
Publication of TWI624016B publication Critical patent/TWI624016B/zh
Publication of TW201911500A publication Critical patent/TW201911500A/zh

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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Geometry (AREA)

Abstract

一種電子封裝件及其製法，係於中介板之上側設有電子元件及形成有包覆該電子元件之第一封裝層，且於該中介板之下側設有複數導電元件及包覆該些導電元件之第二封裝層，以於該電子封裝件進行熱循環時，該第一封裝層之收縮力與該第二封裝層之收縮力會相互抵銷，而減緩該中介板翹曲情況。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝結構，尤指一種能減緩結構翹曲之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。據此，目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等，藉以達到縮小晶片封裝面積及縮短訊號傳遞路徑之目的。
第1A至1B圖係為習知三維積體電路晶片堆疊之封裝結構1之製法之剖面示意圖。如第1A圖所示，提供一矽中介板(Through Silicon interposer，簡稱TSI)10，該矽中介板10具有相對之置晶側10a與轉接側10b、及連通該置晶側10a與轉接側10b之複數導電矽穿孔(Through-silicon via，簡稱TSV)100，且該轉接側10b上形成有一重佈線 路結構101，再將半導體晶片19之電極墊190藉由複數銲錫凸塊102電性結合至該置晶側10a上，並以底膠192包覆該些銲錫凸塊102，且形成封裝膠體18於該矽中介板10上，以包覆該半導體晶片19。接著，如第1B圖所示，於該重佈線路結構101上藉由複數如銲錫凸塊之導電元件103電性結合封裝基板17之銲墊170，並以另一底膠172包覆該些導電元件103。
惟，習知封裝結構1之製法中，於第1A圖之製程中，該矽中介板10之置晶側10a形成有封裝膠體18，而該轉接側10b上僅形成有導電元件103，導致該封裝膠體18於熱循環過程中會產生一收縮力，致使第1A圖所示之結構發生嚴重的翹曲，導致後續於第1B圖所示之製程中，該些導電元件103無法準確對位結合該封裝基板17之銲墊170，因而造成電性連接不良。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：中介板，係具有相對之第一側與第二側；電子元件，係設於該中介板之第一側上；第一封裝層，係形成於該中介板之第一側上以包覆該電子元件；複數導電元件，係設於該中介板之第二側上；以及第二封裝層，係形成於該中介板之第二側上以包覆該些導電元件，且令該些導電元件之部分表面外露出該第二封裝層。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一側與第二側的中介板，且於該中介板之第一側上設置電子元件；於該中介板之第一側上形成包覆該電子元件之第一封裝層；於該中介板之第二側上形成複數導電元件；以及於該中介板之第二側上形成包覆該些導電元件之第二封裝層，且令該些導電元件之部分表面外露出該第二封裝層。
前述之電子封裝件及其製法中，該第一封裝層與第二封裝層係為環氧樹酯所形成者，且該環氧樹酯包含有樹脂材及填充材，其中，該第一封裝層的樹酯材含量與該第二封裝層的樹酯材含量不同。例如，該第二封裝層的樹酯材含量大於第一封裝層之樹酯材含量。進一步地，該第一封裝層與該第二封裝層的填充材含量不相同，例如，該第一封裝層的填充材含量大於該第二封裝層的填充材含量。
前述之電子封裝件及其製法中，該第一封裝層之體積大於該第二封裝層之體積。例如，該第一封裝層的寬度等於該第二封裝層的寬度。或者，該第一封裝層之厚度大於該第二封裝層之厚度。亦或，該第一封裝層之厚度與該第二封裝層之厚度的比值係大於或等於1.3。
前述之電子封裝件及其製法中，該第一封裝層之寬度等於該中介板之寬度。
前述之電子封裝件及其製法中，該第二封裝層之寬度等於該中介板之寬度。
前述之電子封裝件及其製法中，該些導電元件係凸伸 出該第二封裝層。
前述之電子封裝件及其製法中，該第二封裝層之厚度係小於該導電元件之厚度的一半。
由上可知，本發明之電子封裝件及其製法，主要藉由在中介板之第一側與第二側上分別形成第一封裝層與第二封裝層，以於製程中進行熱循環時，該第一封裝層之收縮力與該第二封裝層之收縮力會相互抵銷，使該中介板之應力得以平衡，因而減緩該中介板翹曲情況，故相較於習知技術，本發明之電子封裝件於後續製程中，該些導電元件能準確對位結合該封裝基板之電性接點，避免電性連接不良之問題。
1,3‧‧‧封裝結構
10‧‧‧矽中介板
10a‧‧‧置晶側
10b‧‧‧轉接側
100‧‧‧導電矽穿孔
101‧‧‧重佈線路結構
102,240‧‧‧銲錫凸塊
103,20‧‧‧導電元件
17‧‧‧封裝基板
170‧‧‧銲墊
172,192,31‧‧‧底膠
18‧‧‧封裝膠體
19‧‧‧半導體晶片
190‧‧‧電極墊
2‧‧‧電子封裝件
200‧‧‧凸塊底下金屬層
21‧‧‧第一封裝層
22‧‧‧第二封裝層
23‧‧‧中介板
23a‧‧‧第一側
23b‧‧‧第二側
230‧‧‧導電穿孔
231‧‧‧重佈線路層
24‧‧‧電子元件
30‧‧‧電子裝置
300‧‧‧電性接點
S‧‧‧切割路徑
W‧‧‧寬度
T,H1,H2‧‧‧厚度
第1A至1B圖係為習知封裝結構之製法之剖面示意圖；第2A至2E圖係為本發明之電子封裝件之製法的剖面示意圖；以及第3圖係為第2E圖之後續製程的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定 條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一具有相對之第一側23a與第二側23b的中介板23，且該中介板23之第一側23a上設有複數電子元件24。
於本實施例中，該中介板23係為半導體板材，如矽基板、玻璃板或其它適當板材，其具有複數連通該第一側23a與第二側23b之導電穿孔230、及至少一設於該第一側23a上並電性連接該導電穿孔230之重佈線路層(redistribution layer，簡稱RDL)231。另外，該重佈線路層231亦可選擇設於該第二側23b上或同時佈設於該中介板23之第一側23a與第二側23b，並電性連接該導電穿孔230。
再者，該電子元件24係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件24係為半導體晶片，其藉由複數銲錫凸塊240以覆晶方式電性結合 該重佈線路層231；或者，該電子元件24可藉由複數銲線(圖略)以打線方式電性連接該重佈線路層231；亦或，該電子元件24可直接接觸該重佈線路層231。然而，有關該電子元件24電性連接該中介板23之方式不限於上述。
如第2B圖所示，形成第一封裝層21於該中介板23之第一側23a上以包覆該電子元件24。
於本實施例中，形成該第一封裝層21之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材。
如第2C圖所示，形成複數導電元件20於該中介板23之第二側23b上，使該些導電元件20電性連接該導電穿孔230。
於本實施例中，可依需求形成凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)200於該導電穿孔230與該導電元件20之間，即該些導電元件20對應設於各該導電穿孔230之端面上，且該導電元件20係如銲球或其它金屬塊體(如銅柱)，並無特別限制。
如第2D圖所示，形成第二封裝層22於該中介板23之第二側23b上以包覆該些導電元件20，且令該些導電元件20之部分表面外露於該第二封裝層22。
於本實施例中，形成該第二封裝層22之材質係為聚醯亞胺(PI)、乾膜、環氧樹脂或封裝材，其可相同或不相同於該第一封裝層21之材質。
再者，所述之第一及第二封裝層之構成係包含主要材 質與填充材(filler)，若上述第一及第二封裝層之主要材質為環氧樹脂，且包含有樹脂材及填充材，該第一封裝層21的樹酯材(epoxy resin)含量與該第二封裝層22的樹酯材含量不同，其中，該第二封裝層22的樹酯材含量大於第一封裝層21之樹酯材含量，使該第二封裝層22於樹酯材較多時收縮力較大，而可提供一大於該第一封裝層21之收縮力的反向收縮力，藉以降低翹曲的發生機率。具體地，該第一封裝層21的樹酯材含量少於20%重量百分比，且該第二封裝層22的樹酯材含量大於或等於20%重量百分比。換言之，該第一封裝層21與該第二封裝層22的填充材含量不相同，且該第一封裝層21的填充材含量大於該第二封裝層22的填充材含量。具體地，該第一封裝層21的填充材含量大於或等於80%重量百分比，且該第二封裝層22的填充材含量小於80%重量百分比。
又，該第一封裝層21之體積大於該第二封裝層22之體積。例如，當該第一封裝層21的寬度等於該第二封裝層22的寬度(或兩者均等於該中介板23之寬度)時，該第一封裝層21之厚度H1大於該第二封裝層22之厚度H2。較佳地，該第一封裝層21之厚度H1與該第二封裝層22之厚度H2的比值(H1/H2)係大於或等於1.3，以達成較佳的翹曲控制。
另外，該些導電元件20之部分表面(如端部)係凸伸出該第二封裝層22以外露於該第二封裝層22，例如，該第二封裝層22的厚度H2係小於該導電元件20相對該第二 側23b之厚度T的一半(即H2<T/2)。然而，於其它實施例中，亦可以其它方式外露於該第二封裝層22，例如，該些導電元件20之端面齊平該第二封裝層22之下表面、或該第二封裝層22形成複數外露該些導電元件20之開孔等，故有關該些導電元件20外露於該第二封裝層22之方式並無特別限制。
如第2E圖所示，沿如第2D圖所示之切割路徑S進行切單製程，以獲得複數電子封裝件2。
於本實施例中，於後續製程中，如第3圖所示，該電子封裝件2可藉由該些導電元件20結合至一如封裝基板之電子裝置30上，再以底膠31包覆該些導電元件20，以製成一封裝結構3，其中，該電子裝置30具有複數電性接點300以結合該些導電元件20。
本發明之製法，係於該中介板23之第一側23a與第二側23b上分別形成該第一封裝層21與第二封裝層22，以當該電子封裝件2進行熱循環時，該第一封裝層21之收縮力與該第二封裝層22之收縮力會相互抵銷，使該中介板23之相對兩側(第一側23a與第二側23b)之應力得以平衡，因而能減緩該中介板23翹曲狀況，故相較於習知技術，本發明之電子封裝件2於後續製程中，該些導電元件20能準確對位結合該封裝基板30之電性接點300，因而能避免電性連接不良之問題。
本發明提供一種電子封裝件2，係包括：一中介板23、一電子元件24、第一封裝層21、複數導電元件20以及第 二封裝層22。
所述之中介板23係具有相對之第一側23a與第二側23b。
所述之電子元件24係設於該中介板23之第一側23a上。
所述之第一封裝層21係形成於該中介板23之第一側23a上以包覆該電子元件24。
所述之導電元件20係設於該中介板23之第二側23b上。
所述之第二封裝層22係形成於該中介板23之第二側23b上以包覆該些導電元件20，且令該些導電元件20之部分表面外露出該第二封裝層22。
於一實施例中，該第一與第二封裝層21,22係為環氧樹酯，且該第一封裝層21的樹酯材含量與該第二封裝層22的樹酯材含量不同。例如，該第二封裝層22的樹酯材含量大於第一封裝層21之樹酯材含量。進一步，該第一封裝層21與該第二封裝層22的填充材含量不相同，例如，該第一封裝層21的填充材含量大於該第二封裝層22的填充材含量。
於一實施例中，該第一封裝層21之體積大於該第二封裝層22之體積。例如，該第一封裝層21的寬度W等於該第二封裝層22的寬度W，該第一封裝層21之厚度H1大於該第二封裝層22之厚度H2。再者，該第一封裝層21之厚度H1與該第二封裝層22之厚度H2的比值係大於或等 於1.3。
於一實施例中，該第一封裝層21之寬度W等於該中介板23之寬度W。
於一實施例中，該第二封裝層22之寬度W等於該中介板23之寬度W。
於一實施例中，該些導電元件20係凸伸出該第二封裝層22。
於一實施例中，該第二封裝層22的厚度H2係小於該導電元件20相對該第二側23b之厚度T的一半。
綜上所述，本發明之電子封裝件及其製法，係藉由該中介板之第一側與第二側上分別形成該第一與第二封裝層之設計，以於進行熱循環時，能減緩該中介板翹曲情況，故本發明之電子封裝件於後續製程中，該些導電元件能準確對位結合該封裝基板之電性接點，因而能避免電性連接不良之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (24)

  1. 一種電子封裝件，係包括：中介板，係具有相對之第一側與第二側；電子元件，係設於該中介板之第一側上；第一封裝層，係形成於該中介板之第一側上以包覆該電子元件；複數導電元件，係設於該中介板之第二側上；以及第二封裝層，係形成於該中介板之第二側上以包覆該些導電元件，且令該些導電元件之部分表面外露出該第二封裝層；其中，該第一封裝層與第二封裝層係為環氧樹酯所形成者，且該環氧樹酯包含有樹脂材及填充材，其中，該第一封裝層的樹酯材含量與該第二封裝層的樹酯材含量不同。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第二封裝層的樹酯材含量大於第一封裝層之樹酯材含量。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第一封裝層與該第二封裝層的填充材含量不相同。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該第一封裝層的填充材含量大於該第二封裝層的填充材含量。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該第一封裝層之體積大於該第二封裝層之體積。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該第一封裝層的寬度等於該第二封裝層的寬度。
  7. 如申請專利範圍第5項所述之電子封裝件，其中，該第一封裝層之厚度大於該第二封裝層之厚度。
  8. 如申請專利範圍第5項所述之電子封裝件，其中，該第一封裝層之厚度與該第二封裝層之厚度的比值係大於或等於1.3。
  9. 如申請專利範圍第1項所述之電子封裝件，其中，該第一封裝層之寬度等於該中介板之寬度。
  10. 如申請專利範圍第1項所述之電子封裝件，其中，該第二封裝層之寬度等於該中介板之寬度。
  11. 如申請專利範圍第1項所述之電子封裝件，其中，該些導電元件係凸伸出該第二封裝層。
  12. 如申請專利範圍第1項所述之電子封裝件，其中，該第二封裝層之厚度係小於該導電元件之厚度的一半。
  13. 一種電子封裝件之製法，係包括：提供一具有相對之第一側與第二側的中介板，且於該中介板之第一側上設置電子元件；於該中介板之第一側上形成包覆該電子元件之第一封裝層；於該中介板之第二側上設置複數導電元件；以及於該中介板之第二側上形成包覆該些導電元件之第二封裝層，且令該些導電元件之部分表面外露出該第二封裝層；其中，該第一封裝層與第二封裝層係為環氧樹酯所形成者，且該環氧樹酯包含有樹脂材及填充材，其中，該第一封裝層的樹酯材含量與該第二封裝層的樹酯材含量不同。
  14. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第二封裝層的樹酯材含量大於第一封裝層之樹酯材含量。
  15. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第一封裝層與該第二封裝層的填充材含量不相同。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一封裝層的填充材含量大於該第二封裝層的填充材含量。
  17. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第一封裝層之體積大於該第二封裝層之體積。
  18. 如申請專利範圍第17項所述之電子封裝件之製法，其中，該第一封裝層的寬度等於該第二封裝層的寬度。
  19. 如申請專利範圍第17項所述之電子封裝件之製法，其中，該第一封裝層之厚度大於該第二封裝層之厚度。
  20. 如申請專利範圍第17項所述之電子封裝件之製法，其中，該第一封裝層之厚度與該第二封裝層之厚度的比值係大於或等於1.3。
  21. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第一封裝層之寬度等於該中介板之寬度。
  22. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第二封裝層之寬度等於該中介板之寬度。
  23. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該些導電元件係凸伸出該第二封裝層。
  24. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第二封裝層之厚度係小於該導電元件之厚度的一半。
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