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TWI615970B - 半導體元件 - Google Patents

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TWI615970B
TWI615970B TW105143896A TW105143896A TWI615970B TW I615970 B TWI615970 B TW I615970B TW 105143896 A TW105143896 A TW 105143896A TW 105143896 A TW105143896 A TW 105143896A TW I615970 B TWI615970 B TW I615970B
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field effect
semiconductor device
conductivity type
substrate
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TW201824558A (zh
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溫文瑩
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新唐科技股份有限公司
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Priority to TW105143896A priority Critical patent/TWI615970B/zh
Priority to CN201710196968.XA priority patent/CN108257955B/zh
Priority to US15/856,066 priority patent/US10217814B2/en
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Abstract

一種半導體元件，包括基底、金氧半場效電晶體以及多個並聯的接面場效電晶體。金氧半場效電晶體配置於基底上。金氧半場效電晶體包括源極區、汲極區以及配置在源極區與汲極區之間的閘極結構。接面場效電晶體與金氧半場效電晶體串聯。各接面場效電晶體於源極區與汲極區之間橫向延伸。

Description

半導體元件
本發明是有關於一種積體電路，且特別是有關於一種半導體元件。
近年來，隨著環保意識抬頭，於是具有低功耗以及高效率能源轉換的高壓元件（high voltage device）愈來愈受到矚目。一般而言，高壓元件主要是應用在功率切換（power switch）元件，例如是開關式電源供應（switching mode power supply，SMPS）、照明、馬達控制或電漿顯示器驅動器等各種領域。
橫向擴散金氧半導體（laterally diffused metal oxide semiconductor，LDMOS）元件是一種典型的高壓元件，其可與互補式金氧半導體製程整合，藉此在單一晶片上製造具有控制、邏輯以及電源開關功能的元件。LDMOS元件在操作時必須具有高崩潰電壓（breakdown voltage）以及低的開啟狀態電阻（on-state resistance，Ron）。然而，設計者若要達成高崩潰電壓的規格要求，通常會犧牲開啟狀態電阻，反之亦然。因此，崩潰電壓與開啟狀態電阻處於一種權衡關係（trade-off）。
本發明提供一種半導體元件，其將多個並聯的接面場效電晶體與金氧半場效電晶體串聯，使得所述半導體元件具有高崩潰電壓，同時維持低的開啟狀態電阻。
本發明提供一種半導體元件，包括基底、金氧半場效電晶體以及多個並聯的接面場效電晶體。金氧半場效電晶體配置於基底上。金氧半場效電晶體包括源極區、汲極區以及配置在源極區與汲極區之間的閘極結構。接面場效電晶體與金氧半場效電晶體串聯。各接面場效電晶體於源極區與汲極區之間橫向延伸。
本發明提供一種半導體元件，包括具有第一導電型的基底、具有第二導電型的源極區與汲極區、閘極結構、具有第二導電型的第一漂移區、多個第一隔離結構以及具有第一導電型的多個第一摻雜區。源極區與汲極區分別配置在基底上。閘極結構配置於源極區與汲極區之間的基底上。第一漂移區配置於基底與閘極結構之間。第一隔離結構分別配置於第一漂移區中，使得第一漂移區分隔為多個第二漂移區。各第二漂移區自源極區延伸至汲極區。第一摻雜區分別配置於第一隔離結構與第二漂移區之間。
基於上述，本發明將多個並聯的接面場效電晶體與金氧半場效電晶體串聯。當汲極電壓低時，本發明之半導體元件的開啟狀態電阻即為接面場效電晶體的並聯電阻。當汲極電壓高時，由於接面場效電晶體的夾止（pinch off）作用，分擔了大部分的壓降，藉此提高了本發明之半導體元件的崩潰電壓。因此，本發明之半導體元件不僅具有高崩潰電壓，同時可維持低的開啟狀態電阻。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
在以下的實施例中，第一導電型與第二導電型不同。在一實施例中，第一導電型為N型，第二導電型為P型。在另一實施例中，第一導電型為P型，第二導電型為N型。P型摻雜例如是硼；N型摻雜例如是磷或是砷。在本實施例中，是以第一導電型為P型，第二導電型為N型為例來說明，但本發明並不以此為限。
圖1是依照本發明之一實施例的一種半導體元件的上視圖。為圖面清楚起見，在圖1中僅繪示出源極區、汲極區、閘極結構、井區、第一隔離結構以及接面場效電晶體。
請先參照圖1，半導體元件10包括具有第二導電型的源極區202、具有第二導電型的汲極區204、閘極結構208、第一隔離結構104以及多個並聯的接面場效電晶體106。
源極區202、汲極區204以及配置於源極區202與汲極區204之間的閘極結構208可構成一金氧半場效電晶體。所述金氧半場效電晶體與接面場效電晶體106串聯。如圖1所示，各接面場效電晶體106於源極區202（或閘極結構208）與汲極區204之間橫向延伸。換言之，各接面場效電晶體106自源極區202（或閘極結構208）朝向汲極區204的方向（即A-A’線方向）延伸。詳細地說，各接面場效電晶體106包括具有第一導電型的兩個第一摻雜區110a、110b以及具有第二導電型的漂移區108。在垂直於源極區202（或閘極結構208）朝向汲極區204的方向（即B-B’線方向）上，漂移區108位於兩個第一摻雜區110a、110b之間。第一隔離結構104分別配置於接面場效電晶體106之間。也就是說，各第一隔離結構104亦自源極區202（或閘極結構208）延伸至汲極區204，且第一隔離結構104與接面場效電晶體106沿著B-B’線方向交替排列。另外，雖然圖1中僅繪示兩個接面場效電晶體106，但本發明不以此為限。在其他實施例中，接面場效電晶體106的數量可依需求來調整。
在本實施例中，第一隔離結構104分隔彼此並聯的接面場效電晶體106，使得源極區202與汲極區204之間的通道變成了多通道（亦即多個漂移區108）。因此，當汲極電壓低時，本實施例之半導體元件10的開啟狀態電阻即為接面場效電晶體106的並聯電阻。而當汲極電壓高時，由於接面場效電晶體106的夾止作用，分擔了大部分的壓降，藉此提高了本實施例之半導體元件10的崩潰電壓。如此一來，本實施例之半導體元件10不僅具有高崩潰電壓，同時可維持低的開啟狀態電阻。
值得注意的是，在A-A’線方向上，本實施例之第一隔離結構104與閘極結構208相距一距離D。此距離D可使得閘極結構208中的閘介電層208a（如圖2所示）與第一隔離結構104不會重疊，藉此避免時依性介電崩潰（time-dependent dielectric breakdown，TDDB）效應，進而提升半導體元件10的可靠度。在一實施例中，距離D可例如是大於或等於0 µm 。但本發明不以此為限，在其他實施例中，第一隔離結構104與閘極結構208之間的距離可趨近於零，或是部分重疊。
此外，本實施例之半導體元件10更包括具有第一導電型的井區114。井區114位於閘極結構208遠離接面場效電晶體106的一側，使得源極區202位於井區114與閘極結構208之間。另一方面來看，井區114包圍源極區202，並與部分閘極結構208相連。
圖2是圖1之A-A’線的第一實施例的剖面示意圖。圖3A是圖1之B-B’線的第一實施例的剖面示意圖。
請同時參照圖1、圖2與圖3A，從剖面示意圖的角度來看，半導體元件10包括具有第一導電型的基底100、具有第二導電型的第三摻雜區102、具有第一導電型的井區114、具有第二導電型的源極區202、具有第二導電型的汲極區204、具有第一導電型的第四摻雜區206、閘極結構208、第一隔離結構104、第二隔離結構112以及多個並聯的接面場效電晶體106。
基底100可以是半導體基底、半導體化合物基底或是絕緣層上有半導體基底（Semiconductor Over Insulator，SOI）。半導體例如是IVA族的原子，例如矽或鍺。半導體化合物例如是IVA族的原子所形成之半導體化合物，例如是碳化矽或是矽化鍺，或是IIIA族原子與VA族原子所形成之半導體化合物，例如是砷化鎵。
第三摻雜區102位於基底100上。在一實施例中，第三摻雜區102可例如是N型磊晶層（N-epi）、N型深井區（deep N-well）或其組合。
井區114位於第三摻雜區102中。源極區202與第四摻雜區206分別位於井區114中。源極區202與第四摻雜區206之間更包括第三隔離結構210。第三隔離結構210例如是局部熱氧化隔離結構，其材質為絕緣材料，例如是氧化矽。
閘極結構208包括閘介電層208a與閘電極208b。閘介電層208a位於井區114（或第三摻雜區102）與閘電極208b之間。閘介電層208a可以是由單材料層所構成。單材料層例如是低介電常數材料或是高介電常數材料。低介電常數材料是指介電常數低於4的介電材料，例如是氧化矽或氮氧化矽。高介電常數材料是指介電常數高於4的介電材料，例如是HfAlO、HfO 2、Al 2O 3或Si 3N 4。閘介電層208a的厚度依不同介電材料的選擇而有所不同，舉例來說，若閘介電層208a為氧化矽的話，其厚度可為5 nm至100 nm。閘電極208b為導電材質，例如金屬、多晶矽、摻雜多晶矽、多晶矽化金屬或其組合而成之堆疊層。
接面場效電晶體106位於第三摻雜區102中。另一方面，如圖3A所示，第三摻雜區102位於接面場效電晶體106與基底100之間。各接面場效電晶體106包括具有第一導電型的兩個第一摻雜區110a、110b以及具有第二導電型的漂移區108。如圖3A所示，在B-B’線方向上，漂移區108位於兩個第一摻雜區110a、110b之間。
如圖3A所示，第一隔離結構104分別配置於接面場效電晶體106之間，以分隔接面場效電晶體106。在一實施例中，第一隔離結構104可例如是淺溝渠隔離（Shallow Trench Isolation，STI）結構。具體來說，第一隔離結構104的形成方法可例如是先在第三摻雜區102中形成多個開口（未繪示）。接著，對所述開口進行一傾斜角度的離子佈植製程。藉由調整所述傾斜角度，可於所述開口的兩側分別形成第一摻雜區110a、110b。在一實施例中，各第一摻雜區110a、110b的摻雜濃度為1´10 17/cm 3至1´10 19/cm 3。但本發明不以此為限，在其他實施例中，可隨著設計者的需求調整第一摻雜區110a、110b的摻雜濃度。之後，於所述開口中填入絕緣材料。所述絕緣材料可例如是氧化矽。在一實施例中，第一隔離結構104的底面與漂移區108的底面齊平。但本發明不限於此，在其他實施例中，第一隔離結構104的底面與漂移區108的底面亦可為不同平面。
另外，第二隔離結構112配置於第一隔離結構104與接面場效電晶體106上。如圖2所示，第二隔離結構112位於源極區202與汲極區204之間，且第二隔離結構112的一部分位於漂移區108中，第二隔離結構112的另一部分位於第三摻雜區102中。換言之，第二隔離結構112與接面場效電晶體106部分重疊。閘極結構208覆蓋第二隔離結構112的部分頂面。透過閘極結構208覆蓋部分第二隔離結構112的架構，可使源極區202與汲極區204之間所形成的電場中最大電場強度的位置往第二隔離結構112下方偏移，而非落在閘介電層208a下方，避免厚度較薄的閘介電層208a被過強的電場擊穿。在一實施例中，第二隔離結構112例如是局部熱氧化隔離結構，其材質為絕緣材料，例如是氧化矽。
在替代實施例中，如圖3A所示，第一隔離結構104與第二隔離結構112的組合可視為是一種指叉型結構。第一隔離結構104分別埋入第三摻雜區102中，使得第三摻雜區102分隔為多個漂移區108。在此實施例中，第三摻雜區102的摻雜濃度可實質上等於漂移區108的摻雜濃度。
雖然圖3A所繪示的第一隔離結構104與基底100之間具有第三摻雜區102，但本發明不以此為限。在其他實施例中，第一隔離結構104亦可與基底100相連或接觸。也就是說，第一隔離結構104與基底100之間可不具有第三摻雜區102。
請回頭參照圖2，汲極區204位於漂移區108中。在一實施例中，漂移區108的摻雜濃度可高於第三摻雜區102的摻雜濃度；而汲極區204的摻雜濃度可高於漂移區108的摻雜濃度。但本發明不以此為限，在其他實施例中，可隨著設計者的需求調整漂移區108的摻雜濃度，以降低本實施例之半導體元件10的開啟狀態電阻。
此外，半導體元件10更包括接觸窗212配置於源極區202上；接觸窗214配置於汲極區204上。接觸窗212與接觸窗214分別為導電材質，例如金屬、多晶矽、摻雜多晶矽、多晶矽化金屬或其組合。
圖3B是圖1之B-B’線的第二實施例的剖面示意圖。
請參照圖3B，本發明第二實施例之半導體元件20與第一實施例之半導體元件10相似，其不同之處在於：第二實施例之半導體元件20更包括具有第一導電型的多個第二摻雜區110c分別配置於第一隔離結構104的下方的第三摻雜區102中。詳細地說，第二摻雜區110c的形成方法可例如是先在第三摻雜區102中形成多個開口（未繪示）。接著，對所述開口進行一傾斜角度的離子佈植製程。藉由調整所述傾斜角度，可於所述開口的兩側分別形成第二摻雜區110a、110b，並同時在所述開口的底部形成第二摻雜區110c。在一實施例中，第一摻雜區110a、110b以及第二摻雜區110c的摻雜濃度可實質上相同。但本發明不以此為限，在其他實施例中，亦可分開形成第一摻雜區110a、110b以及第二摻雜區110c，使得第一摻雜區110a、110b以及第二摻雜區110c的摻雜濃度實質上不同。
值得注意的是，第二摻雜區110c、第三摻雜區102以及基底100可形成另一種接面場效電晶體。當汲極電壓高時，由於第二摻雜區110c、第三摻雜區102以及基底100所構成的接面場效電晶體亦具有夾止作用，其可更進一步地提高了本實施例之半導體元件20的崩潰電壓。
綜上所述，本發明將多個並聯的接面場效電晶體與金氧半場效電晶體串聯。當汲極電壓低時，本發明之半導體元件的開啟狀態電阻即為接面場效電晶體的並聯電阻。當汲極電壓高時，由於接面場效電晶體的夾止作用，分擔了大部分的壓降，藉此提高了本發明之半導體元件的崩潰電壓。因此，本發明之半導體元件不僅具有高崩潰電壓，同時可維持低的開啟狀態電阻。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20‧‧‧半導體元件
100‧‧‧基底
102‧‧‧第三摻雜區
104‧‧‧第一隔離結構
106‧‧‧接面場效電晶體
108‧‧‧漂移區
110a、110b‧‧‧第一摻雜區
110c‧‧‧第二摻雜區
112‧‧‧第二隔離結構
114‧‧‧井區
202‧‧‧源極區
204‧‧‧汲極區
206‧‧‧第四摻雜區
208‧‧‧閘極結構
208a‧‧‧閘介電層
208b‧‧‧閘電極
210‧‧‧第三隔離結構
212、214‧‧‧接觸窗
D‧‧‧距離
圖1是依照本發明之一實施例的一種半導體元件的上視圖。 圖2是圖1之A-A’線的第一實施例的剖面示意圖。 圖3A是圖1之B-B’線的第一實施例的剖面示意圖。 圖3B是圖1之B-B’線的第二實施例的剖面示意圖。
10‧‧‧半導體元件
104‧‧‧第一隔離結構
106‧‧‧接面場效電晶體
108‧‧‧漂移區
110a、110b‧‧‧第一摻雜區
114‧‧‧井區
202‧‧‧源極區
204‧‧‧汲極區
208‧‧‧閘極結構
D‧‧‧距離

Claims (10)

  1. 一種半導體元件，包括：一金氧半場效電晶體，配置於一基底上，其中該金氧半場效電晶體包括：一源極區、一汲極區以及配置在該源極區與該汲極區之間的一閘極結構；以及多個並聯的接面場效電晶體，與該金氧半場效電晶體串聯，其中各該些接面場效電晶體於該源極區與該汲極區之間橫向延伸。
  2. 如申請專利範圍第1項所述的半導體元件，更包括多個第一隔離結構，分別配置於該些接面場效電晶體之間，其中各該些第一隔離結構於該源極區與該汲極區之間橫向延伸。
  3. 如申請專利範圍第2項所述的半導體元件，其中各該些接面場效電晶體包括：具有一第一導電型的兩個第一摻雜區，位於該基底上；以及具有一第二導電型的一漂移區，配置在該些第一摻雜區之間。
  4. 如申請專利範圍第3項所述的半導體元件，更包括具有該第一導電型的多個第二摻雜區，分別配置在該些第一隔離結構的下方。
  5. 如申請專利範圍第2項所述的半導體元件，其中該些第一隔離結構與該閘極結構相距一距離。
  6. 如申請專利範圍第2項所述的半導體元件，更包括一第二隔離結構，配置於該些第一隔離結構與該些接面場效電晶體上，其中該閘極結構部分覆蓋該第二隔離結構的頂面。
  7. 如申請專利範圍第1項所述的半導體元件，更包括具有一第二導電型的一第三摻雜區，位於該基底與該些接面場效電晶體之間。
  8. 一種半導體元件，包括：具有一第一導電型的一基底；具有一第二導電型的一源極區與一汲極區，分別配置在該基底上；一閘極結構，配置於該源極區與該汲極區之間的該基底上；具有該第二導電型的一第一漂移區，配置於該基底與該閘極結構之間；多個第一隔離結構，分別配置於該第一漂移區中，使得該第一漂移區分隔為多個第二漂移區，其中各該些第二漂移區於該源極區與該汲極區之間橫向延伸；以及具有該第一導電型的多個第一摻雜區，分別配置於該些第一隔離結構與該些第二漂移區之間。
  9. 如申請專利範圍第8項所述的半導體元件，更包括具有該第二導電型的一第三摻雜區位於該基底與該些第一隔離結構之間。
  10. 如申請專利範圍第9項所述的半導體元件，更包括具有該第一導電型的多個第二摻雜區，分別配置於該些第一隔離結構的下方的該第三摻雜區中。
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