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TWI601254B - 晶圓級晶片尺寸封裝及其形成方法 - Google Patents

晶圓級晶片尺寸封裝及其形成方法 Download PDF

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Publication number
TWI601254B
TWI601254B TW105140372A TW105140372A TWI601254B TW I601254 B TWI601254 B TW I601254B TW 105140372 A TW105140372 A TW 105140372A TW 105140372 A TW105140372 A TW 105140372A TW I601254 B TWI601254 B TW I601254B
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Taiwan
Prior art keywords
conductive
layer
passivation layer
bonding pad
forming
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TW105140372A
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English (en)
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TW201733059A (zh
Inventor
季彥良
熊明仁
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聯發科技股份有限公司
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Publication of TW201733059A publication Critical patent/TW201733059A/zh
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Publication of TWI601254B publication Critical patent/TWI601254B/zh

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Description

晶圓級晶片尺寸封裝及其形成方法
本發明涉及積體電路(Integrated Circuit，IC)，特別係涉及一種具有RDL(Redistribution Layer，重分佈層)的WLCSP(Wafer-Level Chip-Size Package，晶圓級晶片尺寸封裝)及其形成方法。
使電子產品小、輕和高性能的願望已經發展為使電子部件小、輕和高性能的願望。此種願望已導致各種封裝技術連同與半導體設計與製造有關的技術的發展。典型的封裝技術例如包括：基於區域陣列及表面黏著(surface-mount)封裝的BGA(Ball Grid Array，球柵陣列)、覆晶以及CSP(Chip-Size Package，晶片尺寸封裝)。
於上述中，CSP係一種亟待開發的能夠使得小封裝與實際的晶片具有相同尺寸的封裝技術。特別地，在WLCSP中，以晶圓級製造封裝使得每晶片的封裝成本可以顯著地降低。一般地，WLCSP包括：RDL佈線(wiring trace)、用於形成凸塊的UBM(Under Bump Metallurgy，凸塊下金屬)層，以及保護電路的鈍化層。
因此，本發明之主要目的即在於提供一種晶圓級晶片尺寸封裝及其形成方法，可以縮小晶圓級晶片尺寸封裝的尺寸。
根據本發明至少一個實施例的一種晶圓級晶片尺寸封裝，包括：一半導體結構；一接合墊，形成於該半導體結構上，並且包括：複數個導電片段；一導電元件，形成於該半導體結構上，並且與該接合墊相鄰；一鈍化層，形成於該半導體結構、該接合墊及該導電元件上，其中該鈍化層露出該接合墊的導電片段的一部分；一導電的重分佈層，形成於該鈍化層和該接合墊的導電片段從該鈍化層露出的部分上；一平坦化層，形成於該鈍化層和該導電的重分佈層上，並且露出該導電的重分佈層的一部分；一凸塊下金屬層，形成於該平坦化層以及該導電的重分佈層從該平坦化層露出的部分上；以及一導電凸塊，形成於該凸塊下金屬層上。
根據本發明至少一個實施例一種形成晶圓級晶片尺寸封裝的方法，包括：提供一半導體結構，具有形成於其上的一接合墊和一導電元件，其中該接合墊包括：複數個導電片段，並且該導電元件相鄰該接合墊；於該半導體結構、該接合墊及該導電元件上形成一鈍化層，其中該鈍化層露出該接合墊的導電片段的複數部分；於該鈍化層和該接合墊的導電片段從該鈍化層露出的部分上形成一導電的重分佈層；於該鈍化層和該導電的重分佈層上形成一平坦化層，並且該平坦化層露出該導電的重分佈層的一部分；於該平坦化層以及該導電的重分佈層從該平坦化層露出的部分上形成一凸塊下金屬層；以及於該 凸塊下金屬層上形成一導電凸塊。
本發明實施例，由鈍化層來露出接合墊的導電片段的一部分，因此不需要接合墊具有大尺寸構造，從而能夠減少導電片段的尺寸以使得接合墊附近能夠有額外的空間來設置導電元件，從而增加了元件佈置密度，進而縮小晶圓級晶片尺寸封裝(如其中的積體電路)的尺寸。
100、200‧‧‧半導體結構
102、202‧‧‧接合墊
104、204‧‧‧鈍化層
106、210‧‧‧第一平坦化層
112、218‧‧‧第二平坦化層
110、216‧‧‧重分佈層
116、224‧‧‧UBM層
118、226‧‧‧導電凸塊
108、114、208、214、222‧‧‧開口
A‧‧‧梯狀部分
B‧‧‧平坦部分
203‧‧‧導電元件
202a‧‧‧導電片段
201‧‧‧溝道
C、T‧‧‧厚度
206、212、220‧‧‧圖案化製程
216a‧‧‧第一部分
216b‧‧‧第二部分
通過閱讀接下來的詳細描述以及參考所附的圖式所做的示例，可以更全面地理解本發明，其中： 第1圖為根據本發明實施例的WLCSP的橫截面示意圖；第2~8圖為橫截面示意圖，用於示意根據本發明實施例的形成WLCSP的方法；第9圖為第8圖中的WLCSP的區域的俯視圖；第10圖為根據本發明另一實施例的WLCSP的橫截面示意圖；第11圖為第10圖中的WLCSP的區域的俯視圖；第12圖為根據本發明另一實施例的WLCSP的橫截面示意圖；第13圖為第12圖中的WLCSP的區域的俯視圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。 本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
以下描述為實現本發明的較佳預期模式。該描述僅做為說明本發明的一般原理的目的，而不應被視為限制。本發明的範圍最好參考所附的申請專利範圍來確定。
第1圖是根據本發明實施例的WLCSP(晶圓級晶片尺寸封裝)的橫截面示意圖。
如第1圖所示，該WLCSP包括：一半導體結構100，一接合墊102，一鈍化層104，一第一平坦化(planarization)層106，一第二平坦化層112，一導電的重分佈層(conductive redistribution layer)110，一UBM(凸塊下金屬)層116和一導電凸塊118。
此中，出於簡化圖式的目的，將該半導體結構100示意為具有平坦的頂面。需要注意的是，該半導體結構100可以為一具有在其上形成的複數個半導體裝置及互連結構(均未示出)的晶圓級半導體基底。該等形成在該半導體基底100上的半導體裝置例如可以為諸如電晶體或者二極體等主動設備，及/或諸如電容、電阻和導體等被動設備。該半導體結構 100中的互連結構可以包括：由複數個層間介電層隔離與支撐的多層金屬化結構。在本實施例中，僅半導體結構100的一部分被示出在WLCSP中。
參考第1圖，接合墊102形成在半導體結構100的一部分上並且可以與形成在半導體結構100中的電路的互連結構(未示出)之一電性連接。鈍化層104和第一平坦化層106順序地形成在半導體結構100上，並且鈍化層104和第一平坦化層106分別部分地覆蓋接合墊102的一部分。在第一平坦化層106中形成開口108以露出接合墊102的一部分，並且導電的重分佈層110一致地(conformably)形成在第一平坦化層106的一部分上，並且一致地形成在開口108中以覆蓋接合墊102從開口108中露出的部分。第二平坦化層112形成在第一平坦化層106及導電的重分佈層110上，並且在第二平坦化層112中形成一開口114以露出導電的重分佈層110的一部分。UBM層116形成在第二平坦化層112的一部分及導電的重分佈層110從第二平坦化層112露出的部分上，並且導電凸塊118形成在UBM層116上。
在本實施例中，接合墊102可以包括：諸如鋁等導電材料，並且鈍化層104可以包括：諸如氧化矽、氮化矽或者他們的組合物等介電材料。第一平坦化層106和第二平坦化層112可以包括：諸如氮化矽、氧化矽或者聚合物等介電材料。在一個實施例中，適合於第一平坦化層106和第二平坦化層112的聚合物例如可以為聚酰亞胺，聚苯並惡唑，苯環丁烯。導電的重分佈層110可以包括：諸如銅、鎳或鋁等導電材料。 UBM層116可以包括：諸如金屬或金屬合金等導電材料，例如鎳、銀、鋁、銅或者他們的合金，或者摻有多晶矽、單晶矽或者導電玻璃的材料。另外，諸如鈦、鉬、鉻或者鈦鎢等耐火金屬材料可以用來獨立地形成UBM層116或者與其他金屬層組合。一般地，第一平坦化層106具有大約5μm~7.5μm的厚度C。並且接合墊102上的第一平坦化層106的階梯高度(step-height)太大，從而使得第一平坦化層106中形成的開口108小於鈍化層104中形成的開口，該鈍化層104中形成的開口具有3μm~300μm的尺寸。因此，導電的重分佈層110一致地形成在第一平坦化層106的一部分和接合墊102從開口露出的部分上，並且具有位於開口108附近的梯狀(step-like)構造的梯狀部分A，以及平坦構造的平坦部分B，其中平坦部分B從開口108延伸並且位於第一平坦化層106上。另外，第二平坦化層112中形成的開口114露出導電的重分佈層110的平坦部分B的一部分，使得UBM層114可以一致地設置在第二平坦化層112的一部分以及從開口114露出的導電的重分佈層110的平坦部分B上。
在第1圖所示的WLCSP中，由於提供了具有大約5μm~7.5μm厚度C的第一平坦化層106，因此開口108附近的第一平坦化層106的階梯高度太大以致於不能夠使得開口108太小。如此，導電的重分佈層110位於開口108附近的部分形成梯狀構造，並且UBM層116和形成在UBM層116上的導電凸塊(如焊錫凸塊)118僅形成在導電的重分佈層110的平坦部分B上，其中該平坦部分B沿開口108延伸並且位於第 一平坦化層106上。另外，由於鈍化層104中形成的開口需要形成的尺寸大於第一平坦化層106中形成的開口108的尺寸，因此鈍化層104中形成的開口所露出的接合墊102將具備在第1圖所示的WLCSP的操作期間僅具有單一電位的大型(large-sized)導電墊的構造。因此，第1圖所示的WLCSP的封裝(footprint)是相當大並且沒有機會在靠近接合墊102的位置形成另一導電元件，以在第1圖所示的WLCSP的操作期間提供另一電位。由於進一步降低WLCSP中的IC的尺寸的趨勢，因此第1圖所示的WLCSP是不受歡迎的。
因此，第2~8圖為根據本發明另一實施例的橫截面示意圖，用來示意形成WLCSP的方法，其中，該WLCSP具有靠近接合墊的額外的導電元件，以提供不同於接合墊的電位的另一電位。
參考第2圖，提供了一半導體結構200，具有形成在該半導體結構200的各部分上的一接合墊202及一導電元件203。接合墊202包括：複數個形成在半導體結構200上的分開的導電片段(conductive segments)，並且導電元件203靠近接合墊202。在一個實施例中，如第2圖所示，接合墊202包括：兩個導電片段202a，形成在半導體結構200的各部分上，並且導電元件203於導電墊202的導電片段202a之間的位置處形成於半導體結構200上。導電元件203通過溝道(trench)201與接合墊202的兩個導電片段202a隔開，其中該溝道201形成於導電元件203和接合墊202的一個導電片段202a之間。導電元件203及接合墊202的導電片段202a包括： 諸如Al(鋁)、Cu(銅)或者W(鎢)等相同的導電材料，並且可以同時形成。
仍然參考第2圖，接著例如通過CVD(Chemical Vapor Deposition，化學氣相沈積)製程(未示出)在半導體結構200、接合墊202及導電元件203上一致地形成一鈍化層204。該鈍化層204一致地形成在半導體結構200、接合墊202及導電元件203上，並且填充每個溝道201。如第2圖所示，鈍化層204在半導體結構200的上方具有非平坦的頂面。在一個實施例中，鈍化層204的一部分形成在半導體結構200上，並且具有大約0.8μm~4μm的厚度T。
在一個實施例中，半導體結構200相同於第1圖所示的半導體結構100，並且形成鈍化層204的材料類似於用於形成第1圖所示的鈍化層104的材料，以及形成接合墊202及導電元件203的材料類似於用於形成第1圖所示的接合墊102的材料。
參考第3圖所示，接著在第2圖所示的鈍化層204上執行圖案化製程206以僅在鈍化層204位於接合墊202的導電片段202a上的部分中形成複數個開口208。
如第3圖所示，開口208分別露出接合墊202的導電片段202a的一部分。但是，鈍化層204位於導電元件203上的部分中沒有形成開口208，從而使得鈍化層204仍然覆蓋導電元件203並且導電元件203不會從開口208露出。每個開口208具有大約2μm~90μm的尺寸W(例如寬度)，並且俯視時，開口208可以具有圓形、帶狀或者多邊形(未示出)。 在一個實施例中，圖案化製程206可以包括：微影(photolithography)和蝕刻(etching)步驟(未示出)，其使用合適的圖案化光罩(未示出)來作為蝕刻光罩(未示出)。
參考第4圖所示，第一平坦化層210形成在第3圖所示的結構的頂面上，並且接著在第一平坦化層210上執行圖案化製程212以在第一平坦化層210的一部分中形成開口214，從而露出鈍化層204的一部分，露出開口208以及導電墊202的導電片段202a從開口208露出的部分，其中鈍化層204露出的部分形成於導電元件203和接合墊202的導電片段202a上。例如可以通過CVD或旋轉塗覆來形成第一平坦化層210，並且可以通過圖案化製程212來圖案化第一平坦化層210，其中圖案化製程212包括：結合了合適的圖案化光罩(未示出)來作為蝕刻光罩(未示出)的微影和蝕刻步驟(未示出)。用來形成第一平坦化層210的材料可以相同於第1圖所示的第一平坦化層106的材料，第一平坦化層具有大約2μm~15μm的厚度。
參考第5圖，接著在鈍化層204從開口214露出的部分和第一平坦化層210的一部分上形成圖案化的導電的重分佈層216。參考第5圖所示，圖案化的導電的重分佈層216形成於開口214中的部分填充開口208並且覆蓋鈍化層204形成於導電元件203上的部分，其中開口208露出接合墊202的導電片段202a的一部分，其中圖案化的導電的重分佈層216形成於開口214中的部分包含：複數個第一部分216a，填充鈍化層204中形成的開口208，以及一第二部分216b，形成於鈍 化層204的平坦的頂面和開口208的上方。因此，圖案化的導電的重分佈層216也具有一致地頂面，如第5圖所示。通過首先在鈍化層204上及開口208中形成導電的重分佈層，接著通過圖案化製程(未示出)來圖案化該導電的重分佈層，從而形成圖案化的導電的重分佈層216，其中圖案化製程(未示出)包括：結合了合適的圖案化光罩(未示出)來作為蝕刻光罩的微影和蝕刻步驟(未示出)。形成圖案化的導電的重分佈層216的導電材料可以相同於第1圖所示的導電的重分佈層110的材料，並且鈍化層204上方的圖案化的導電的重分佈層216具有4μm~9μm的厚度。
參考第6圖，在第5圖所示的結構的頂面上形成第二平坦化層218，並且接著在第二平坦化層218上執行圖案化製程220，以在第二平坦化層218的一部分中形成開口222，從而露出圖案化的重分佈層216的一部分。例如可以通過CVD或者旋轉塗覆來形成第二平坦化層218，並且由圖案化製程220來圖案化第二平坦化層218，其中圖案化製程220包括：結合了合適的圖案化光罩(未示出)來作為蝕刻光罩的微影和蝕刻步驟(未示出)。形成第二平坦化層218的材料可以與第1圖所示的第一平坦化層112的材料相同，並且第二平坦化層218可以具有大約7.5μm~10μm的厚度，其中第二平坦化層218的厚度大於圖案化的導電的重分佈層216的厚度。
參考第7圖所示，接著在圖案化的導電的重分佈層216從開口222露出的部分上形成UBM層224。通過在第6圖所示的結構上形成導電材料層來形成UBM層224，其中例 如可以通過CVD或電鍍來在第6圖所示的結構上形成導電材料層，並且接著通過圖案化製程(未示出)來圖案化UBM層224，其中圖案化製程(未示出)包括：結合了合適的圖案化光罩(未示出)來作為蝕刻光罩的微影和蝕刻步驟(未示出)。形成UBM層224的材料可以相同於第1圖所示的UBM層116的材料。
參考第8圖，接著通過傳統的焊接凸塊形成製程在UBM層224上形成導電凸塊226。UBM層224和導電凸塊226可以順序地且堅固地形成在圖案化的導電的重分佈層216上。因此，具有額外的靠近接合墊的導電元件的WLCSP大致形成。
如第8圖所示，由於WLCSP具有額外的導電元件203，該導電元件203與接合墊202和圖案化的重分佈層216電性隔離，使得導電元件203可以被設計為用作訊號線、電源線或者接地線，其在第8圖所示的WLCSP的操作期間，操作在與接合墊202的電位不同的電位。另外，由於形成了導電元件203，因此可以將接合墊202的導電片段202a的尺寸縮小得比第1圖所示的傳統的接合墊102的尺寸更小。因此，第8圖所示的WLCSP允許在更緊湊的結構中進行多功能設計，由於趨勢繼續向著進一步降低WLCSP中的積體電路的尺寸，因此第8圖所示的WLCSP是受歡迎的。
第9圖為含有第8圖所示的接合墊202和導電元件203的區域的俯視圖。在第9圖中，僅示意了接合墊202和導電元件203而忽略其他元件，從而方便顯示接合墊202和導 電元件203的佈置。如第9圖所示，導電元件203設置在接合墊202的導電片段202a之間。導電元件203形成為向上和向下延伸的帶狀構造，並且接合墊202的導電片段202a形成為接合墊狀(pad-like)構造，並且該接合墊狀構造具有的最大尺寸(如長度)小於導電元件203的最大尺寸(如長度)。
除了第8圖所示的示範性實施例之外，第10圖為本發明的另一示範性的WLCSP的橫截面示意圖。此時，第10圖所示的WLCSP係修改自第8圖所示的WLCSP，並且第10圖中與第8圖中類似的元件使用相同的參考符號來表示，並且以下僅討論第8圖和第10圖中所示的WLCSP之間的不同。
參考第10圖，導電元件203的位置係與接合墊202中的一個導電片段202a調換，使得導電元件203形成在接合墊202中的導電片段202a的左側處。如第10圖所示，導電元件203僅靠近導電墊202中的一個導電片段202a。
第11圖為含有第10圖所示的WLCSP中的接合墊202和導電元件203的區域的俯視圖。類似地，在第11圖中，僅示意了接合墊202和導電元件203而省略了其他元件，從而方便顯示接合墊202和導電元件203的佈置。如第11圖所示，導電元件203設置在接合墊202的導電片段202a的左側處。導電元件203形成為向上和向下延伸的帶狀構造，並且接合墊202的導電片段202a形成為接合墊狀(pad-like)構造，並且該接合墊狀構造具有的最大尺寸(如長度)小於導電元件203的最大尺寸(如長度)。
另外，除了第8圖所示的示範性實施例之外，第 12圖為本發明的又另一示範性的WLCSP的橫截面示意圖。此時，第12圖所示的WLCSP係修改自第8圖所示的WLCSP，並且第12圖中與第8圖中類似的元件使用相同的參考符號來表示，並且以下僅討論第8圖和第12圖中所示的WLCSP之間的不同。
參考第12圖，導電元件203的位置係與接合墊202中的一個導電片段202a調換，使得導電元件203形成在接合墊202中的導電片段202a的右側處。如第12圖所示，導電元件203僅靠近接合墊202中的一個導電片段202a。
第13圖為含有第12圖所示的WLCSP中的接合墊202和導電元件203的區域的俯視圖。類似地，在第13圖中，僅示意了接合墊202和導電元件203而省略了其他元件，從而方便顯示接合墊202和導電元件203的佈置。如第13圖所示，導電元件203設置在接合墊202的導電片段202a右側處。導電元件203形成為向上和向下延伸的帶狀構造，並且接合墊202的導電片段202a形成為接合墊狀(pad-like)構造，並且該接合墊狀構造具有的最大尺寸(如長度)小於導電元件203的最大尺寸(如長度)。
類似於第8~9圖所示的實施例，由於第10~13圖所示的實施例中的WLCSP也具有與接合墊202和圖案化的重分佈層216電性隔離的額外的導電元件203，使得導電元件203可以設計為用作訊號線、電源線或接地線，其在第8圖所示的WLCSP的操作期間，操作在與接合墊202的電位不同的電位。另外，由於導電元件203的形成，因此可以將接合墊202的導 電片段202a的尺寸縮小至小於第1圖所示的傳統的接合墊102的尺寸。因此第10~13圖所示的WLCSP允許在更緊湊的結構中進行多功能設計，由於趨勢繼續向著進一步降低WLCSP中積體電路的尺寸，因此第10~13圖所示的WLCSP是受歡迎的。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
200‧‧‧半導體結構
202‧‧‧接合墊
204‧‧‧鈍化層
210‧‧‧第一平坦化層
216‧‧‧重分佈層
224‧‧‧UBM層
226‧‧‧導電凸塊
203‧‧‧導電元件
202a‧‧‧導電片段
216a‧‧‧第一部分
216b‧‧‧第二部分

Claims (12)

  1. 一種晶圓級晶片尺寸封裝，包括：一半導體結構；一接合墊，形成於該半導體結構上，並且包括：複數個導電片段；一導電元件，形成於該半導體結構上，並且與該接合墊相鄰；一鈍化層，形成於該半導體結構、該接合墊及該導電元件上，其中該鈍化層包括：複數個第一開口，分別露出該等導電片段的一部分；一導電的重分佈層，形成於該鈍化層和該接合墊的導電片段從該鈍化層露出的部分上；一平坦化層，形成於該鈍化層和該導電的重分佈層上，並且露出該導電的重分佈層的一部分；一凸塊下金屬層，形成於該平坦化層以及該導電的重分佈層從該平坦化層露出的部分上；以及一導電凸塊，形成於該凸塊下金屬層上；其中，該平坦化層包括：一第二開口，露出該鈍化層的該複數個第一開口；其中，該導電的重分佈層形成於該第二開口中並且填充該等第一開口。
  2. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝，其中，該導電元件設置在該接合墊的兩個導電片段之間、或者該導電元件設置在該接合墊的導電片段的左側處、或者該導 電元件設置在該接合墊的導電片段的右側處。
  3. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝，其中，該鈍化層包括：介電材料；及/或，該平坦化層包括：聚酰亞胺，聚苯並惡唑或者苯環丁烯。
  4. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝，其中，該凸塊下金屬層形成於該導電的重分佈層在特定位置處的部分上，其中該特定位置不位於該接合墊的導電片段從該鈍化層露出的部分的上方。
  5. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝，其中，該接合墊的導電片段從該鈍化層露出的部分具有2μm~90μm的尺寸；及/或，該接合墊的導電片段從該鈍化層露出的部分為圓形、帶狀或者多邊形。
  6. 如申請專利範圍第1項所述的晶圓級晶片尺寸封裝，其中，俯視時該導電元件具有帶狀構造。
  7. 一種形成晶圓級晶片尺寸封裝的方法，包括：提供一半導體結構，具有形成於其上的一接合墊和一導電元件，其中該接合墊包括：複數個導電片段，並且該導電元件相鄰該接合墊；於該半導體結構、該接合墊及該導電元件上形成一鈍化層，其中該鈍化層露出該接合墊的導電片段的複數個部分；於該鈍化層和該接合墊的導電片段從該鈍化層露出的部分上形成一導電的重分佈層；於該鈍化層和該導電的重分佈層上形成一平坦化層，並且 該平坦化層露出該導電的重分佈層的一部分；於該平坦化層以及該導電的重分佈層從該平坦化層露出的部分上形成一凸塊下金屬層；以及於該凸塊下金屬層上形成一導電凸塊。
  8. 如申請專利範圍第7項所述的方法，其中，該鈍化層的形成包括：於該半導體結構、該接合墊及該導電元件上形成該鈍化層；以及在該鈍化層中形成複數個開口並且該等開口露出該接合墊的導電片段的部分。
  9. 如申請專利範圍第7項所述的方法，其中，該平坦化層的形成包括：於該鈍化層和該導電的重分佈層上形成該平坦化層；以及在該平坦化層的一部分中形成開口並且該開口露出該導電的重分佈層的一部分。
  10. 如申請專利範圍第7項所述的方法，其中，該接合墊的導電片段從該鈍化層露出的部分具有圓形、帶狀或多邊形；及/或，該接合墊的導電片段從該鈍化層露出的部分具有2μm~90μm的尺寸；及/或，俯視時該導電元件具有帶狀構造。
  11. 一種晶圓級晶片尺寸封裝，包括：一半導體結構；一接合墊，形成於該半導體結構上，並且包括：複數個導電片段； 一導電元件，形成於該半導體結構上，並且與該接合墊相鄰；一鈍化層，形成於該半導體結構、該接合墊及該導電元件上，並且包括：複數個第一開口，分別露出該等導電片段的一部分；一第一平坦化層，形成於該鈍化層上，並且包括：一第二開口，露出該鈍化層的一部分、該等第一開口以及該等導電片段從該等第一開口露出的部分；一導電的重分佈層，形成於該第一開口以及第二開口中，以及形成於該第一平坦化層上，並且該導電的重分佈層覆蓋該鈍化層從該第二開口露出的部分以及覆蓋該等導電片段從該等第一開口露出的部分；一第二平坦化層，形成於該第一平坦化層和該導電的重分佈層上，並且露出該導電的重分佈層的一部分；一凸塊下金屬層，形成於該第二平坦化層以及該導電的重分佈層從該第二平坦化層露出的部分上；以及一導電凸塊，形成於該凸塊下金屬層上。
  12. 如申請專利範圍第11項所述的晶圓級晶片尺寸封裝，其中，該導電元件設置在該等導電片段之間、或者該等導電片段的左側處、或者該等導電片段的右側處。
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