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CN105047643A - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN105047643A
CN105047643A CN201510204708.3A CN201510204708A CN105047643A CN 105047643 A CN105047643 A CN 105047643A CN 201510204708 A CN201510204708 A CN 201510204708A CN 105047643 A CN105047643 A CN 105047643A
Authority
CN
China
Prior art keywords
metal
protective layer
perforate
integrated circuit
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510204708.3A
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English (en)
Inventor
吕国源
周文彬
陈永胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novatek Microelectronics Corp
Original Assignee
Novatek Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW104110499A external-priority patent/TW201541590A/zh
Application filed by Novatek Microelectronics Corp filed Critical Novatek Microelectronics Corp
Publication of CN105047643A publication Critical patent/CN105047643A/zh
Pending legal-status Critical Current

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Abstract

本发明提供一种集成电路，该集成电路包括芯片(chip)、保护层(passivation？layer)、第一金属内连线、路由线(routing？wire)以及压合区。保护层配置于芯片上，其中该保护层具有第一开孔。第一金属内连线配置于保护层下以及配置于该芯片中。路由线配置于保护层上，其中该路由线的第一端通过保护层的第一开孔电性连接第一金属内连线的第一端。压合区配置于保护层上，其中该压合区电性连接路由线的第二端。本发明提供的集成电路可以降低电性路径的内部阻抗。

Description

集成电路
技术领域
本发明是有关于一种集成电路。
背景技术
芯片(chip)的宽度(或长度)越长，其金属内连线(metalline)越长。举例来说，液晶显示面板的高解析度电源驱动芯片因为其狭长型的布局而使其金属内连线的长度过长，进而常遭遇其芯片内部的压降问题(voltagedropissue)。芯片内的金属内连线长度越长，其电阻值越大，导致压降问题越明显。压降问题将导致操作速度下降。传统解决方式通常是在芯片的制造程序中多加了介层窗插塞(Via)及金属层(Metallayer)至芯片内，以降低电性路径(例如系统电压VDD或接地电压VSS)的内部阻抗。然而，更改芯片的内部电路布局意味着要修改多个芯片处理掩模，也就是要花费昂贵的成本。
发明内容
本发明提供一种集成电路，其在保护层(passivationlayer)上增加了路由线(routingwire)，以降低电性路径的内部阻抗。
本发明实施例所述集成电路包括芯片(chip)、保护层(passivationlayer)、第一金属内连线、路由线(routingwire)以及压合区。保护层配置于芯片上，其中该保护层具有第一开孔。第一金属内连线配置于保护层下以及配置该芯片中。路由线配置于保护层上，其中该路由线的第一端通过保护层的第一开孔电性连接第一金属内连线的第一端。压合区配置于保护层上，其中该压合区电性连接路由线的第二端。
在本发明的一实施例中，上述的路由线与压合区配置于保护层之上。
在本发明的一实施例中，上述的第一金属内连线属于该芯片的最上层金属层(topmetallayer)。
在本发明的一实施例中，上述的路由线的材质包括金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物或钯的合金。
在本发明的一实施例中，上述的保护层还具有第二开孔，而该集成电路还包括第一金属垫。第一金属垫配置于保护层下且至少一部分位于该第二开孔下。其中，该压合区通过保护层的该第二开孔电性连接该第一金属垫。
在本发明的一实施例中，上述的第一金属垫的材质包括铝、铝化合物、铝的合金、铜、铜化合物或铜的合金。
在本发明的一实施例中，上述的第二开孔的短边长度为4μm～80μm。在本发明的另一实施例中，上述的第二开孔的短边长度为2μm～70μm。
在本发明的一实施例中，上述的压合区包括黏合层(adhesivelayer)以及路由层(routinglayer)。黏合层具有至少一部分配置于保护层的该第二开孔中。路由层配置于保护层上，并且该路由层电性连接该路由线。该路由层具有至少一部分或全部配置于该黏合层上，并且该路由层通过保护层的该第二开孔通过该黏合层电性连接该第一金属垫。
在本发明的一实施例中，上述的黏合层的材质包括钛、钛化合物或钛钨合金，而该路由层的材质包括金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物或钯的合金。
在本发明的一实施例中，上述的压合区还包括金属凸块。金属凸块配置于保护层上，以及配置于路由层上。金属凸块通过保护层的该第二开孔通过该路由层与该黏合层电性连接至该第一金属垫。
在本发明的一实施例中，上述的金属凸块的高度为3μm～18μm。在本发明的另一实施例中，上述的金属凸块的高度为5μm～15μm。
在本发明的一实施例中，上述的金属凸块与路由层的高度差大于5μm。
在本发明的一实施例中，上述的金属凸块的表面粗糙度为0.05μm～2μm。在本发明的另一实施例中，上述的金属凸块的表面粗糙度为0.8μm～1.7μm。
在本发明的一实施例中，上述的金属凸块的硬度为25～120Hv。在本发明的另一实施例中，上述的金属凸块的硬度为50～110Hv。
在本发明的一实施例中，上述的金属凸块的材质包括金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物或钯的合金。
在本发明的一实施例中，在该芯片的垂直方向，上述的第二开孔与金属凸块的面积比为0％～90％。在本发明的另一实施例中，上述的第二开孔与金属凸块的面积比为5％～33％。
在本发明的一实施例中，上述的集成电路还包括第二金属内连线。第二金属内连线配置于保护层下以及配置于芯片中，其中该第二金属内连线位于该第一金属垫的第一侧且不接触该第一金属垫。金属凸块在芯片的垂直方向至少部分重叠于第一金属垫以及至少部分重叠于第二金属内连线。
在本发明的一实施例中，上述的集成电路还包括第二金属垫。第二金属垫配置于保护层下且在第一金属垫的第一侧。第二金属内连线配置于第一金属垫与第二金属垫之间。金属凸块沿芯片的垂直方向至少部分重叠于该第二金属垫。
在本发明的一实施例中，上述的保护层还具有第三开孔。第二金属垫至少一部分位于该第三开孔下。金属凸块通过保护层的该第三开孔电性连接该第二金属垫。
在本发明的一实施例中，上述的路由线的高度为0.1μm～9μm。在本发明的另一实施例中，上述的路由线的高度为2μm～5μm。
在本发明的一实施例中，上述的集成电路还包括第一金属垫。第一金属垫配置于保护层下。在芯片的垂直方向，压合区位于该第一金属垫上方。
在本发明的一实施例中，上述的压合区包括路由层。路由层配置于保护层上，并且电性连接该路由线。
在本发明的一实施例中，上述的压合区包括金属凸块。金属凸块配置于保护层上，并且配置于该路由层上。
基于上述，本发明实施例所述集成电路在芯片处理结束后的封装处理中增加了路由线在保护层(passivationlayer)上，以降低电性路径的内部阻抗。再者，相较于在芯片处理中更动金属内连线的路由(routing)布局而言，在封装处理中增加路由线可有较大的设计弹性且缩短处理所需全部时间。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是本发明实施例说明一种集成电路100布局结构的俯视示意图；
图2是本发明实施例说明沿图1所示剖面线A-B绘制集成电路100的剖面示意图；
图3A至图3C是本发明实施例说明在制造过程的不同步骤中图1所示集成电路100的俯视示意图；
图4A至图4C是依照图3A至图3C所示剖面线A-B绘制的集成电路100的剖面示意图；
图5是本发明另一实施例说明一种集成电路500布局结构的俯视示意图；
图6是本发明实施例说明沿图5所示剖面线C-D绘制集成电路500的剖面示意图；
图7是本发明又一实施例说明一种集成电路700布局结构的俯视示意图；
图8是本发明实施例说明沿图7所示剖面线E-F绘制集成电路700的剖面示意图；
图9是本发明又一实施例说明一种集成电路900布局结构的俯视示意图；
图10是本发明实施例说明沿图9所示剖面线G-H绘制集成电路900的剖面示意图；
图11是本发明再一实施例说明一种集成电路1100布局结构的俯视示意图；
图12是本发明另一实施例说明一种集成电路1200布局结构的俯视示意图；
图13是本发明实施例说明沿图12所示剖面线I-J绘制集成电路1200的剖面示意图；
图14是本发明又一实施例说明一种集成电路1400布局结构的俯视示意图；
图15是本发明实施例说明沿图14所示剖面线K-L绘制集成电路1400的剖面示意图。
附图标记说明：
100：集成电路；
210：芯片；
220：保护层；
221：第一开孔；
222：第二开孔；
230：第一金属内连线；
231：金属内连线；
240：路由线；
241：黏合层；
250：压合区；
251：金属凸块；
252：路由层；
253：黏合层；
260：第一金属垫；
500：集成电路；
510：芯片；
520：保护层；
521：第一开孔；
522：第二开孔；
530：第一金属内连线；
540：路由线；
541：黏合层；
550：压合区；
551：金属凸块；
552：路由层；
553：黏合层；
560：第一金属垫；
571、572：第二金属内连线；
700：集成电路；
710：芯片；
720：保护层；
721：第一开孔；
722：第二开孔；
723：第三开孔；
730：第一金属内连线；
740：路由线；
741：黏合层；
750：压合区；
751：金属凸块；
752：路由层；
753、754：黏合层；
760：第一金属垫；
771、772：第二金属内连线；
780：第二金属垫；
900：集成电路；
910：芯片；
920：保护层；
921：第一开孔；
922：第二开孔；
923：第三开孔；
930：第一金属内连线；
940：路由线；
941：黏合层；
950：压合区；
951：金属凸块；
952：路由层；
953、954：黏合层；
960：第一金属垫；
971、972：第二金属内连线；
980：第二金属垫；
1100：集成电路；
1121：第一开孔；
1122：第二开孔；
1123：第三开孔；
1130：第一金属内连线；
1140：路由线；
1151：金属凸块；
1152：路由层；
1160：第一金属垫；
1171、1172：第二金属内连线；
1180：第二金属垫；
1200：集成电路；
1210：芯片；
1220：保护层；
1221：第一开孔；
1230：第一金属内连线；
1240：路由线；
1241：黏合层；
1250：压合区；
1251：金属凸块；
1252：路由层；
1260：第一金属垫；
1400：集成电路；
1410：芯片；
1420：保护层；
1421：第一开孔；
1430：第一金属内连线；
1440：路由线；
1441：黏合层；
1450：压合区；
1451：金属凸块；
1452：路由层；
1460：第一金属垫；
1471、1472：第二金属内连线；
1480：第二金属垫；
A-B：剖面线；
C-D：剖面线；
E-F：剖面线；
G-H：剖面线；
I-J：剖面线；
K-L：剖面线。
具体实施方式
在本案说明书全文(包括申请专利范围)中所使用的“耦接”一词可指任何直接或间接的连接手段。举例而言，若文中描述第一装置耦接于第二装置，则应该被解释成该第一装置可以直接连接于该第二装置，或者该第一装置可以通过其他装置或某种连接手段而间接地连接至该第二装置。另外，凡可能之处，在图式及实施方式中使用相同标号的元件、构件、步骤代表相同或类似部分。不同实施例中使用相同标号或使用相同用语的元件、构件、步骤可以相互参照相关说明。
图1是本发明实施例说明一种集成电路100布局结构的俯视示意图。图2是本发明实施例说明沿图1所示剖面线A-B绘制集成电路100的剖面示意图。请参照图1与图2，集成电路100包括芯片210、保护层(passivationlayer)220、第一金属内连线230、路由线(routingwire)240以及压合区250。图2所示芯片210仅为示意图，实际上芯片210的内部、上方和/或下方可能具有各种电性元件、掺杂区、金属层、绝缘层、多晶硅层、接触窗插塞、介层窗插塞和/或其他集成电路构件。在芯片处理结束后，保护层220被配置/覆盖于芯片210的最上层金属层(topmetallayer)上方，以保护芯片210。第一金属内连线230配置于保护层220下以及配置于芯片210中。第一金属内连线230可以表示芯片210中的任何一层金属层/导电层。举例来说，第一金属内连线230可以属于芯片210中的最上层金属层。
在保护层220被配置/覆盖于芯片210上之后，芯片210可以被运送至封装厂以进行后段处理(即封装处理)。集成电路100的封装处理可以用任何方式(例如电镀或其它方式)将路由线240与压合区250配置于芯片210的保护层220上。路由线240的高度可以被设定在0.1μm～9μm的范围内。在另一些实施例中，路由线240的高度可以被设定在2μm～5μm的范围内。路由线240的材质可以是金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物、钯的合金或是其他低阻抗导电物质。
在本实施例中(但不限于此)，保护层220具有第一开孔221与第二开孔222。路由线240配置于保护层220上，其中路由线240的第一端通过保护层220的第一开孔221电性连接第一金属内连线230的第一端。第一金属垫(pad)260配置于保护层220下，且第一金属垫260的至少一部分位于第二开孔222下。第二开孔222的短边长度可以被设定为4μm～80μm的范围内。在另一些实施例中，第二开孔222的短边长度可以被设定为为2μm～70μm的范围内。第一金属垫260可以是铝垫、金垫或其他导电材质。举例来说，第一金属垫260的材质可以是铝、铝化合物、铝的合金、铜、铜化合物、铜的合金或是其他导电物质。
压合区250配置于保护层220上，其中压合区250可以通过保护层220的第二开孔222电性连接第一金属垫260。压合区250电性连接路由线240的第二端。压合区250可以用任何方式(例如打线、导电凸块或其它方式)电性连接集成电路100的封装接脚(未示出)，以便将第一金属垫260和/或路由线240电性连接至集成电路100的外部。在另一些实施例中，路由线240可以用覆晶封装(flipchippackage)方式通过压合区250电性连接至集成电路100外部的电路板。
压合区250可以用任何方式实现。举例来说，图2所示出的压合区250包括金属凸块(bμmp)251、路由层(routinglayer)252以及黏合层(adhesivelayer)253。黏合层253具有至少一部分配置于第二开孔222中。路由层252配置于保护层220上。路由层252配置于黏合层253上，并且路由层252通过第二开孔222通过黏合层253电性连接第一金属垫260。路由层252的高度可以被设定在0.1μm～9μm的范围内。在一些实施例中，路由层252的高度可以被设定在2μm～5μm的范围内。路由层252的材质可以是金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物、钯的合金或其他导电物质。
黏合层253可以是钛钨层(即由钛层与钨层叠合成为黏合层253)，或由钛钨合金实现黏合层253。在其他实施例中，黏合层253的材质可以是其他导电材质(例如钛、钛化合物或其他导电物质)，用以作为路由层252与第一金属垫260之间的连接介质。黏合层253可以使第一金属垫260与路由层252之间有较好的接着力，以便抵抗金属凸块251在生产或压合过程经历的外力撞击而造成可能的变形。在另一些实施例中，基于路由层252与第一金属垫260的材质搭配，使得路由层252与第一金属垫260二者具有良好的黏合性，因此可以省略黏合层253而让路由层252与第一金属垫260直接黏合。
路由层252电性连接路由线240。在本实施例中，路由层252与路由线240可以在集成电路100的封装处理的同一个步骤(例如电镀或其它处理步骤)被配置于芯片210的保护层220上。在将路由层252与路由线240配置于芯片210的保护层220上之后，可以利用平坦化(Planarization)处理，例如化学机械研磨(ChemicalMechanicalPolishing，简称：CMP)等处理，将路由层252与路由线240平坦化。
在将路由层252与路由线240平坦化后，金属凸块251可以被配置于保护层220与路由层252上。金属凸块251通过第二开孔222通过路由层252与黏合层253电性连接至第一金属垫260。金属凸块251的材质可以是金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物、钯的合金或其他导电物质。或者，在其他实施例中，金属凸块251可以是从上述材质中选择部分而组成多层结构金属凸块。
金属凸块251的高度可以被设定在3μm～18μm的范围内。在另一些实施例中，金属凸块251的高度可以被设定在5μm～15μm的范围内。金属凸块251与路由层252的高度差(或金属凸块251与路由线240的高度差)可以视设计需求或处理需求来决定。举例来说，在一些实施例中，路由层252(或路由线240)与金属凸块251的高度差可以大于5μm。
金属凸块251的表面粗糙度可以被设定在0.05μm～2μm的范围内。在另一些实施例中，金属凸块251的表面粗糙度可以被设定在0.8μm～1.7μm的范围内。金属凸块251的硬度可以被设定在25～120Hv的范围内。在另一些实施例中，金属凸块251的硬度可以被设定在50～110Hv的范围内。
在芯片210的垂直方向，第二开孔222与金属凸块251的面积比可以被设定在0％～90％的范围内。在另一些实施例中，第二开孔222与金属凸块251的面积比可以被设定在5％～33％的范围内。
以下将说明集成电路100的制造方法。图3A至图3C是本发明实施例说明在制造过程的不同步骤中图1所示集成电路100的俯视示意图。图4A至图4C是依照图3A至图3C所示剖面线A-B绘制的集成电路100的剖面示意图。
图3A与图4A所示芯片210仅为示意图，实际上芯片210的内部、上方和/或下方可能具有各种电性元件、掺杂区、金属层、绝缘层、多晶硅层、接触窗插塞、介层窗插塞和/或其他集成电路构件。例如，芯片210中的最上层金属层具有第一金属内连线230、金属内连线231以及第一金属垫260。
请参照图3B与图4B，在芯片处理结束时，保护层220被配置/覆盖于芯片210的最上层金属层(第一金属内连线230与第一金属垫260)上，以保护芯片210。保护层220至少具有第一开孔221与第二开孔222。第一开孔221可以暴露部分第一金属内连线230。第二开孔222可以暴露部分第一金属垫260。在将保护层220配置于芯片210上之后，可以利用平坦化处理(例如化学机械研磨等处理)，以提高保护层220的平整度。
请参照图3C与图4C，在保护层220被配置/覆盖于芯片210上之后，芯片210可以在封装厂进行后段处理(即封装处理)。集成电路100的封装处理可以用任何方式(例如电镀或其它方式)将路由线240、黏合层241、黏合层253与路由层252配置于芯片210的保护层220上。黏合层241具有至少一部分配置于第一开孔221中。路由线240配置于黏合层241上，并且路由线240通过第一开孔221通过黏合层241电性连接第一金属内连线230。黏合层253具有至少一部分配置于第二开孔222中。路由层252配置于黏合层253上，并且路由层252通过第二开孔222通过黏合层253电性连接第一金属垫260。路由层252与路由线240可以在集成电路100的封装处理的同一个步骤(例如电镀或其它处理步骤)同时被配置于芯片210的保护层220上。在将路由层252与路由线240配置于芯片210的保护层220上之后，可以利用平坦化处理(例如化学机械研磨等处理)，将路由层252与路由线240平坦化。
在路由层252与路由线240平坦化后，接着将金属凸块251被配置于保护层220与路由层252上，如图1与图2所示。金属凸块251可以通过第二开孔222通过路由层252与黏合层253电性连接至第一金属垫260。金属凸块251还可以通过第一开孔221通过路由层252、路由线240与黏合层241电性连接第一金属内连线230。
金属凸块251表面粗糙度可通过配置金属凸块的处理得到控制。金属凸块251表面粗糙度为0.05～2μm，较佳的实施例为0.8～1.7μm。当表面粗糙度过大(例如≧2μm)会使在压合时金属凸块251接触不良。当表面粗糙度过小(例如≦0.05μm)可能影响金属凸块251捕捉导电粒子能力。
金属凸块251所适用硬度范围为25～120Hv，较佳的实施例为50～110Hv。在将集成电路100压合至电路版(例如COG面板)时，若金属凸块251硬度过高(例如>110Hv)，可能导致金属凸块251边缘的保护层220发生龟裂，而影响可靠度。若金属凸块251硬度过低(例如<50Hv)，在将集成电路100压合至电路版(例如COG面板)时，可能导致金属凸块251不易压破导电粒子而使导电情况不佳。
综上所述，本实施例所述集成电路100在芯片处理结束后的封装处理中增加了路由线240在保护层220上。路由线240具有低电阻值，故可以降低电性路径中的电能(例如数据信号、控制信号、系统电压VDD或接地电压VSS)损耗，避免因为压降问题(voltagedropissue)导致操作速度下降。再者，相较于在芯片处理中更动金属内连线的路由(routing)布局而言，在封装处理中增加路由线可有较大的设计弹性且缩短处理所需全部时间。本实施例所述集成电路100可以被应用于晶粒-玻璃接合处理(ChipOnGlass，简称：COG)产品、晶粒-软片接合处理(ChipOnFilm，简称：COF)产品、晶粒-电路板接合处理(ChiopOnBoard，简称：COB)产品或是其他类型集成电路产品。
图5是本发明另一实施例说明一种集成电路500布局结构的俯视示意图。图6是本发明实施例说明沿图5所示剖面线C-D绘制集成电路500的剖面示意图。请参照图5与图6，集成电路500包括芯片510、保护层520、第一金属内连线530、路由线540、黏合层541、压合区550以及第一金属垫560。压合区550包括金属凸块551、路由层552以及黏合层553。图5与图6所示芯片510、保护层520、第一金属内连线530、路由线540、黏合层541、压合区550、金属凸块551、路由层552、黏合层553以及第一金属垫560可以参照图1、图2、图3A～3C与图4A～4C所示芯片210、保护层220、第一金属内连线230、路由线240、黏合层241、压合区250、金属凸块251、路由层252、黏合层253以及第一金属垫260的相关说明，故不再赘述。
在本实施例中(但不限于此)，保护层520具有第一开孔521与第二开孔522。图5与图6所示第一开孔521与第二开孔522可以参照图1、图2、图3A～3C与图4A～4C所示第一开孔221与第二开孔222的相关说明。路由线540的第一端通过保护层520的第一开孔521通过黏合层541电性连接第一金属内连线530的第一端。路由层552通过保护层520的第二开孔522通过黏合层553电性连接第一金属垫560。
在图5与图6所示实施例中，集成电路500还包括第二金属内连线571与572。第二金属内连线571与572可以是芯片510的电源线、接地线、数据线、控制线、浮接(floating)金属或其他导线。第二金属内连线571与572配置于保护层520下以及配置于芯片510中。第二金属内连线571与572位于第一金属垫560的第一侧且不接触第一金属垫560。金属凸块551在芯片510的垂直方向(例如图6所示垂直方向Z)至少部分重叠于第一金属垫560以及至少部分重叠于第二金属内连线571与572。此可为凸块在主动区上(BumpOnActive,简称：BOA)设计。保护层520配置于金属凸块551与第二金属内连线571与572之间。举例而言(但不以此为限)，第二金属内连线571与572的宽度各自可为0.1μm～40μm。第二金属内连线571的边缘至第一金属垫560的边缘的距离可大于0.1μm。
综上所述，本实施例所述集成电路500通过缩小第二开孔522，也即有效减少第一金属垫560面积，使得金属凸块551下方可摆放第二金属内连线571与572，提高最上层金属层(topmetallayer)绕线面积，以利金属内连线的绕线设计。
图7是本发明又一实施例说明一种集成电路700布局结构的俯视示意图。图8是本发明实施例说明沿图7所示剖面线E-F绘制集成电路700的剖面示意图。请参照图7与图8，集成电路700包括芯片710、保护层720、第一金属内连线730、路由线740、黏合层741、压合区750以及第一金属垫760。压合区750包括金属凸块751、路由层752以及黏合层753。图7与图8所示芯片710、保护层720、第一金属内连线730、路由线740、黏合层741、压合区750、金属凸块751、路由层752、黏合层753以及第一金属垫760可以参照图1、图2、图3A～3C与图4A～4C所示芯片210、保护层220、第一金属内连线230、路由线240、黏合层241、压合区250、金属凸块251、路由层252、黏合层253以及第一金属垫260的相关说明，故不再赘述。
在本实施例中(但不限于此)，保护层720具有第一开孔721与第二开孔722。图7与图8所示第一开孔721与第二开孔722可以参照图1、图2、图3A～3C与图4A～4C所示第一开孔221与第二开孔222的相关说明。路由线740的第一端通过保护层720的第一开孔721通过黏合层741电性连接第一金属内连线730的第一端。路由层752通过保护层720的第二开孔722通过黏合层753电性连接第一金属垫760。
在图7与图8所示实施例中，集成电路700还包括第二金属内连线771、第二金属内连线772与第二金属垫780，而压合区750还包括黏合层754。图7与图8所示第二金属内连线771与772可以参照图5与图6所示第二金属内连线571与572的相关说明。第二金属垫780可以参照图1、图2、图3A～3C与图4A～4C所示第一金属垫260的相关说明。第二金属垫780配置于保护层720下且在第一金属垫760的第一侧。第二金属内连线771与772配置于第一金属垫760与第二金属垫780之间。金属凸块751沿芯片710的垂直方向(例如图8所示垂直方向Z)至少部分重叠于第二金属垫780。保护层720还具有第三开孔723。第二金属垫780至少一部分位于第三开孔723下，以及金属凸块751通过保护层720的第三开孔723通过黏合层754电性连接第二金属垫780。
图9是本发明又一实施例说明一种集成电路900布局结构的俯视示意图。图10是本发明实施例说明沿图9所示剖面线G-H绘制集成电路900的剖面示意图。请参照图9与图10，集成电路900包括芯片910、保护层920、第一金属内连线930、路由线940、黏合层941、压合区950、第二金属内连线971、第二金属内连线972、第一金属垫960以及第二金属垫980。压合区950包括金属凸块951、路由层952、黏合层953以及黏合层954。图9与图10所示芯片910、保护层920、第一金属内连线930、路由线940、黏合层941、压合区950、金属凸块951、路由层952、黏合层953、黏合层954以及第一金属垫960可以参照图1、图2、图3A～3C与图4A～4C所示芯片210、保护层220、第一金属内连线230、路由线240、黏合层241、压合区250、金属凸块251、路由层252、黏合层253以及第一金属垫260的相关说明，故不再赘述。图9与图10所示第二金属内连线971、第二金属内连线972、第一金属垫960、第二金属垫980、金属凸块951以及路由层952可以参照图7与图8所示第二金属内连线771、第二金属内连线772、第一金属垫760、第二金属垫780、金属凸块751以及路由层752的相关说明。
在图9与图10所示实施例中(但不限于此)，保护层920具有第一开孔921、第二开孔922与第三开孔923。图9与图10所示第一开孔921、第二开孔922与第三开孔923可以参照图1、图2、图3A～3C与图4A～4C所示第一开孔221与第二开孔222的相关说明。路由线940的第一端通过保护层920的第一开孔921通过黏合层941电性连接第一金属内连线930的第一端。路由层952通过保护层920的第二开孔922通过黏合层953电性连接第一金属垫960。路由层952也通过保护层920的第三开孔923通过黏合层954电性连接第一金属垫960。路由层952与第二金属垫980之间的保护层920不具有开孔。
图11是本发明再一实施例说明一种集成电路1100布局结构的俯视示意图。集成电路1100包括第一金属内连线1130、路由线1140、金属凸块1151、路由层1152、第一金属垫1160、第二金属内连线1171、第二金属内连线1172以及第二金属垫1180。图11所示集成电路1100可以参照图9与图10所示集成电路900的相关说明而类推之，故不再赘述。
在图11所示实施例中(但不限于此)，保护层具有第一开孔1121、第二开孔1122与第三开孔1123。图11所示第一开孔1121、第二开孔1122与第三开孔1123可以参照图1、图2、图3A～3C与图4A～4C所示第一开孔221与第二开孔222的相关说明。路由线1140的第一端通过保护层的第一开孔1121电性连接第一金属内连线1130的第一端。路由层1152通过保护层的第二开孔1122与第三开孔1123电性连接第一金属垫1160。路由层1152与第二金属垫1180之间的保护层不具有开孔。
图12是本发明另一实施例说明一种集成电路1200布局结构的俯视示意图。图13是本发明实施例说明沿图12所示剖面线I-J绘制集成电路1200的剖面示意图。请参照图12与图13，集成电路1200包括芯片1210、保护层1220、第一金属内连线1230、路由线1240、黏合层1241、压合区1250以及第一金属垫1260。压合区1250包括金属凸块1251以及路由层1252。图12与图13所示芯片1210、保护层1220、第一金属内连线1230、路由线1240、黏合层1241、压合区1250、金属凸块1251、路由层1252以及第一金属垫1260可以参照图1、图2、图3A～3C与图4A～4C所示芯片210、保护层220、第一金属内连线230、路由线240、黏合层241、压合区250、金属凸块251、路由层252以及第一金属垫260的相关说明，故不再赘述。
在图12与图13所示实施例中(但不限于此)，保护层具有第一开孔1221。图12所示第一开孔1221可以参照图1、图2、图3A～3C与图4A～4C所示第一开孔221的相关说明。路由线1240的第一端通过保护层1220的第一开孔1221通过黏合层1241电性连接第一金属内连线1230的第一端。
路由层1252与第一金属垫1260之间的保护层1220不具有开孔。第一金属垫1260配置于保护层1220下。在芯片1210的垂直方向，压合区1250在第一金属垫1260上方。压合区1250的路由层1252配置于保护层1220上，并且路由层1252电性连接路由线1240。金属凸块1251配置于保护层1220上，并且配置于路由层1252上。金属凸块1251可做为假凸块(dummybump)，以平衡压合力矩比，以及改善压合时集成电路翘曲(ICWarpage)现象。集成电路翘曲现象在薄化集成电路(例如集成电路厚度≦200μm)更易显现。
图14是本发明又一实施例说明一种集成电路1400布局结构的俯视示意图。图15是本发明实施例说明沿图14所示剖面线K-L绘制集成电路1400的剖面示意图。请参照图14与图15，集成电路1400包括芯片1410、保护层1420、第一金属内连线1430、路由线1440、黏合层1441、压合区1450、第一金属垫1460、第二金属垫1480、第二金属内连线1471以及第二金属内连线1472。压合区1450包括金属凸块1451以及路由层1452。图14与图15所示芯片1410、保护层1420、第一金属内连线1430、路由线1440、黏合层1441、压合区1450、金属凸块1451、路由层1452以及第一金属垫1460可以参照图12与图13所示芯片1210、保护层1220、第一金属内连线1230、路由线1240、黏合层1241、压合区1250、金属凸块1251、路由层1252以及第一金属垫1260的相关说明，故不再赘述。
在图14与图15所示实施例中(但不限于此)，保护层具有第一开孔1421。图14所示第一开孔1421可以参照图1、图2、图3A～3C与图4A～4C所示第一开孔221的相关说明。路由线1440的第一端通过保护层1420的第一开孔1421通过黏合层1441电性连接第一金属内连线1430的第一端。
在图14与图15所示实施例中，集成电路1400还包括第二金属垫1480、第二金属内连线1471与第二金属内连线1472。第二金属内连线1471与1472可以是芯片1410的电源线、接地线、数据线、控制线、浮接(floating)金属或其他导线。第二金属内连线1471与1472配置于保护层1420下以及配置于芯片1410中。图14所示第二金属内连线1471与1472可以参照图5与图6所示第二金属内连线571与572的相关说明。
第一金属垫1460与第二金属垫1480配置于保护层1420下。路由层1452与第一金属垫1460之间的保护层1420不具有开孔。路由层1452与第二金属垫1480之间的保护层1420也不具有开孔。压合区1450的路由层1452配置于保护层1420上，并且路由层1452电性连接路由线1440。在芯片1410的垂直方向，路由层1452在第一金属垫1460与第二金属垫1480上方。压合区1450的金属凸块1451配置于路由层1452上。由于金属凸块1451下方的保护层1420不具有开孔，使得金属凸块1451下方可摆放第二金属内连线1471与1472，提高芯片1410的最上层金属层绕线面积，以利金属内连线的绕线设计。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (31)

1.一种集成电路，其特征在于，所述集成电路包括：
芯片；
保护层，配置于所述芯片上，其中所述保护层具有第一开孔；
第一金属内连线，配置于所述保护层下以及配置于所述芯片中；
路由线，配置于所述保护层上，其中所述路由线的第一端通过所述保护层的所述第一开孔电性连接所述第一金属内连线的第一端；以及
压合区，配置于所述保护层上，其中所述压合区电性连接所述路由线的第二端。
2.根据权利要求1所述的集成电路，其特征在于，所述路由线与所述压合区配置于所述保护层之上。
3.根据权利要求1所述的集成电路，其特征在于，所述第一金属内连线属于所述芯片的最上层金属层。
4.根据权利要求1所述的集成电路，其特征在于，所述路由线的材质包括金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物或钯的合金。
5.根据权利要求1所述的集成电路，其特征在于，所述保护层还具有第二开孔，而所述集成电路还包括：
第一金属垫，配置于所述保护层下且至少一部分位于所述第二开孔下；
其中所述压合区通过所述保护层的所述第二开孔电性连接所述第一金属垫。
6.根据权利要求5所述的集成电路，其特征在于，所述第一金属垫的材质包括铝、铝化合物、铝的合金、铜、铜化合物或铜的合金。
7.根据权利要求5所述的集成电路，其特征在于，所述第二开孔的短边长度为4μm～80μm。
8.根据权利要求7所述的集成电路，其特征在于，所述第二开孔的短边长度为2μm～70μm。
9.根据权利要求5所述的集成电路，其特征在于，所述压合区包括：
黏合层，具有至少一部分配置于所述第二开孔中；以及
路由层，配置于所述保护层上，并且电性连接所述路由线，其中所述路由层配置于所述黏合层上，并且所述路由层通过所述第二开孔通过所述黏合层电性连接所述第一金属垫。
10.根据权利要求9所述的集成电路，其特征在于，所述黏合层的材质包括钛、钛化合物或钛钨合金，而所述路由层的材质包括金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物或钯的合金。
11.根据权利要求9所述的集成电路，其特征在于，所述路由层的高度为0.1μm～9μm。
12.根据权利要求11所述的集成电路，其特征在于，所述路由层的高度为2μm～5μm。
13.根据权利要求9所述的集成电路，其特征在于，所述压合区还包括：
金属凸块，配置于所述保护层上，以及配置于所述路由层上，其中所述金属凸块通过所述第二开孔通过所述路由层与所述黏合层电性连接至所述第一金属垫。
14.根据权利要求13所述的集成电路，其特征在于，所述金属凸块的高度为3μm～18μm。
15.根据权利要求14所述的集成电路，其特征在于，所述金属凸块的高度为5μm～15μm。
16.根据权利要求13所述的集成电路，其特征在于，所述金属凸块与所述路由层的高度差大于5μm。
17.根据权利要求13所述的集成电路，其特征在于，所述金属凸块的表面粗糙度为0.05μm～2μm。
18.根据权利要求17所述的集成电路，其特征在于，所述金属凸块的表面粗糙度为0.8μm～1.7μm。
19.根据权利要求13所述的集成电路，其特征在于，所述金属凸块的硬度为25～120Hv。
20.根据权利要求19所述的集成电路，其特征在于，所述金属凸块的硬度为50～110Hv。
21.根据权利要求13所述的集成电路，其特征在于，所述金属凸块的材质包括金、金化合物、金的合金、铜、铜化合物、铜的合金、镍、镍化合物、镍的合金、钯、钯化合物或钯的合金。
22.根据权利要求13所述的集成电路，其特征在于，在所述芯片的垂直方向，所述第二开孔与所述金属凸块的面积比为0％～90％。
23.根据权利要求22所述的集成电路，其特征在于，所述第二开孔与所述金属凸块的所述面积比为5％～33％。
24.根据权利要求13所述的集成电路，其特征在于，所述集成电路还包括：
第二金属内连线，配置于所述保护层下以及配置于所述芯片中，其中所述第二金属内连线位于所述第一金属垫的第一侧且不接触所述第一金属垫；
其中所述金属凸块于所述芯片的垂直方向至少部分重叠于所述第一金属垫以及至少部分重叠于所述第二金属内连线。
25.根据权利要求24所述的集成电路，其特征在于，所述集成电路还包括：
第二金属垫，配置于所述保护层下且于所述第一金属垫的所述第一侧；
其中所述第二金属内连线配置于所述第一金属垫与所述第二金属垫之间；以及所述金属凸块沿所述芯片的所述垂直方向至少部分重叠于所述第二金属垫。
26.根据权利要求25所述的集成电路，其特征在于，所述保护层还具有第三开孔，所述第二金属垫至少一部分位于所述第三开孔下，以及所述金属凸块通过所述保护层的所述第三开孔电性连接所述第二金属垫。
27.根据权利要求1所述的集成电路，其特征在于，所述路由线的高度为0.1μm～9μm。
28.根据权利要求27所述的集成电路，其特征在于，所述路由线的高度为2μm～5μm。
29.根据权利要求1所述的集成电路，其特征在于，所述集成电路还包括：
第一金属垫，配置于所述保护层下；
其中在所述芯片的垂直方向，所述压合区位于所述第一金属垫上方。
30.根据权利要求29所述的集成电路，其特征在于，所述压合区包括：
路由层，配置于所述保护层上，并且电性连接所述路由线。
31.根据权利要求30所述的集成电路，其特征在于，所述压合区包括：
金属凸块，配置于所述保护层上，并且配置于所述路由层上。
CN201510204708.3A 2014-04-28 2015-04-27 集成电路 Pending CN105047643A (zh)

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