TWI503941B - Chip package substrate and method for manufacturing same - Google Patents

Description

Chip package substrate and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing, and in particular, to a chip package substrate and a method of fabricating the same.

The chip package substrate can provide electrical connection, protection, support, heat dissipation, assembly and the like for the wafer to achieve multi-pin, reduce package volume, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization. .

A conventional chip package substrate includes one or more insulating substrates and a conductive wiring layer formed on one side or opposite sides of the insulating substrate. With the development of wafer technology, the pitch of the lines in the wafer is becoming finer and finer, so that the spacing of the conductive lines in the chip package substrate carrying the wafer is also required to be finer and finer, which makes the manufacturing of the chip package substrate more and more difficult. Manufacturing costs increase. Under the high-density packaging requirements of wafers, the industry also uses glass materials as the insulating substrate. The use of glass materials as the insulating substrate can achieve ultra-fine wiring requirements for conductive circuit layers. However, the insulating substrate of the chip package substrate is generally very thin. When the glass material is made into a very thin insulating substrate, the glass material is extremely fragile, resulting in difficulty in fabricating the chip package substrate and low production yield.

Therefore, it is necessary to provide a chip package substrate which is easy to manufacture and has a high yield and a method of manufacturing the same.

A method for fabricating a chip package substrate, comprising the steps of: providing a circuit board core board, comprising: an insulation substrate; and forming a first conductive circuit layer and a second conductive circuit layer on opposite sides of the insulation substrate, the first conductive circuit layer comprising a plurality of a first electrical connection pad, the second conductive circuit layer includes a plurality of second electrical connection pads; a first adhesive layer is disposed on the surface of the first conductive circuit layer and the insulating substrate exposed on the first conductive circuit layer, And bonding the first glass substrate to the first adhesive layer; forming a third conductive circuit layer on the surface of the first glass substrate, and forming a plurality of first through the first glass substrate and the first adhesive layer The guiding hole is electrically connected to the third conductive circuit layer at one end of the plurality of first guiding holes, and the opposite ends are electrically connected to the plurality of first electrical connecting pads respectively to form a chip package substrate.

A chip package substrate includes a circuit board core board, a first adhesive layer, a first glass substrate, and a third conductive circuit layer. The circuit board core board includes an insulating substrate and a first conductive circuit layer and a second conductive circuit layer forming opposite sides of the insulating substrate, the first conductive circuit layer includes a plurality of first electrical connection pads, and the second conductive circuit The layer includes a plurality of second electrical connection pads. The first adhesive layer is formed on the surface of the first conductive circuit layer and the insulating substrate is exposed on the surface of the first conductive circuit layer, and the first glass substrate is adhered to the first adhesive layer, the third conductive line The layer is formed on the surface of the first glass substrate, and is electrically connected to the plurality of first electrical connection pads respectively through a plurality of first guiding blind holes formed in the first glass substrate and the first adhesive layer.

In this embodiment, when the first blind via is formed on the first glass substrate, the first glass substrate is supported by the circuit board core board, thereby preventing the first glass substrate from being chipped during processing, and the wafer package substrate is fabricated. It becomes easy and improves the fabrication yield of the chip package substrate. In addition, ultra-fine lines can be fabricated on the glass substrate and the line pitch can be made fine, so that the layer of the conductive wiring layer of the entire chip package substrate can be reduced. The number is reduced to reduce the thickness of the chip package substrate, and the first glass substrate can be electrically connected to the semiconductor package having high-density solder joints, thereby making the chip package substrate more applicable.

10‧‧‧Circuit board

101‧‧‧Insulation base

20‧‧‧First glass substrate

22‧‧‧Second glass substrate

102‧‧‧First conductive circuit layer

103‧‧‧Second conductive circuit layer

104‧‧‧ first surface

105‧‧‧ second surface

106‧‧‧ core unit

107‧‧‧First electrical connection pad

108‧‧‧Second electrical connection pad

30‧‧‧First layer

32‧‧‧Second layer

24‧‧‧First blind hole

26‧‧‧Second blind hole

44‧‧‧ Third conductive circuit layer

46‧‧‧fourth conductive layer

242‧‧‧First blind hole

262‧‧‧Second blind hole

442‧‧‧ Third electrical connection pad

462‧‧‧4th electrical connection pad

50‧‧‧First dielectric layer

52‧‧‧ Fifth conductive circuit layer

60‧‧‧Second dielectric layer

62‧‧‧ sixth conductive circuit layer

522‧‧‧ Third blind hole

622‧‧‧4th blind hole

524‧‧‧The fifth electrical connection pad

624‧‧‧6th electrical connection pad

70‧‧‧First solder mask

72‧‧‧Second solder mask

74‧‧‧Surface treatment layer

100‧‧‧ chip package substrate

80‧‧‧ wafer

200‧‧‧ Chip package structure

82‧‧‧chip body

84‧‧‧ solder bumps

526,528‧‧‧ solder balls

530‧‧‧Bottom filler

1 is a top plan view of a circuit board core board and a glass substrate according to an embodiment of the present invention.

Figure 2 is an enlarged view of a portion II of the circuit board core and glass substrate shown in Figure 1.

3 is a cross-sectional view of the circuit board core board and the glass substrate of FIG. 2.

4 is a cross-sectional view showing a blind hole formed on the glass substrate of FIG. 3.

Figure 5 is a cross-sectional view showing the formation of a conductive wiring layer on the glass substrate of Figure 4 and the formation of via holes in the blind vias.

Figure 6 is a cross-sectional view of the circuit board of Figure 5 after layering.

7 is a cross-sectional view of a wafer package substrate formed after forming a solder resist layer on both sides of the circuit board of FIG. 6.

FIG. 8 is a cross-sectional view showing the wafer after the wafer is mounted on the chip package substrate of FIG. 7. FIG.

9 is a cross-sectional view showing a wafer package structure formed by packaging the wafer of FIG. 8.

Figure 10 is another embodiment of the connection relationship between the circuit board core board and the glass substrate of Figure 3.

Referring to FIG. 1 to FIG. 9 , an embodiment of the present invention provides a method for fabricating a chip package structure, including the following steps:

In the first step, referring to FIG. 1 to FIG. 3, a circuit board core board 10 is provided on the board core board. The first adhesive layer 30 and the second adhesive layer 32 are respectively disposed on opposite sides of the 10, and the plurality of first glass substrates 20 are adhered to the first adhesive layer 30, and the plurality of second glass substrates 22 are bonded. On the second adhesive layer 32.

The circuit board core board 10 includes an insulating substrate 101 and a first conductive wiring layer 102 and a second conductive wiring layer 103 disposed on opposite sides of the insulating substrate 101, the insulating substrate 101 including opposing first surface 104 and second surface 105. The first conductive circuit layer 102 and the second conductive circuit layer 103 are respectively formed on the first surface 104 and the second surface 105. The first conductive circuit layer 102 and the second conductive circuit layer 103 pass through the first conductive layer. The via holes (not shown) of the wiring layer 102, the insulating substrate 101, and the second conductive wiring layer 103 are electrically connected. In this embodiment, the circuit board core board 10 includes a plurality of core board units 106 arranged in an array for forming a plurality of chip package substrates of the same structure, and FIG. 1 and FIG. 2 are separated by a broken line, and the core is actually produced. The number of board units 106 is not limited thereto. The conductive lines of the first conductive wiring layer 102 in the plurality of core unit 106 have the same structure, and the second conductive wiring layers 103 in the plurality of core units 106 are the same. The first conductive circuit layer 102 in each core unit 106 includes a plurality of first electrical connection pads 107, and each of the second conductive circuit layers 103 in each core unit 106 includes a plurality of second electrical connection pads. 108.

The first adhesive layer 30 covers the first conductive circuit layer 102 and the first surface 104 exposed on the first conductive circuit layer 102. The second adhesive layer 32 covers the second conductive circuit layer 103 and is exposed to the second surface. The second surface 105 of the conductive circuit layer 103, the plurality of first glass substrates 20 and the plurality of second glass substrates 22 are respectively adhered to the first adhesive layer 30 and the second adhesive layer 32, that is, each core unit The first glass substrate 20 and the second glass substrate 22 are respectively disposed on opposite sides of the 106. The first adhesive layer 30 and the second adhesive layer 32 may be pure glue. In this embodiment, the plurality of first glass substrates 20 are respectively adhered and protruded to the first On the surface of the adhesive layer 30, the plurality of second glass substrates 22 are respectively adhered and protruded from the surface of the second adhesive layer 32. It can be understood that, as shown in FIG. 10, the plurality of first glass substrates 20 may also be respectively embedded in the first adhesive layer 30, and the plurality of second glass substrates 22 may also be embedded in the second adhesive layer 32, respectively. This embodiment is limited.

For convenience of explanation, the present embodiment starts from the first step to a plurality of steps of forming a plurality of separate chip package substrate units for the plurality of core unit 106 and the corresponding plurality of first glass substrates 20 and second glass. The processes of the substrate 22 are all performed simultaneously. In the present embodiment, for the convenience of description, the steps of forming the separated plurality of chip package substrate units from the second step to cutting are performed for one of the core unit 106 and its corresponding first glass substrate 20 and second glass substrate 22. The process is described as an example.

In the second step, referring to FIG. 4, a plurality of first blinds penetrating the first glass substrate 20 and the first adhesive layer 30 and exposing the plurality of first electrical connection pads 107 respectively are formed from the first glass substrate 20 side. The hole 24 defines a plurality of second blind holes 26 penetrating the second glass substrate 22 and the second adhesive layer 32 and exposing the plurality of second electrical connection pads 108 on the second glass substrate 22 side. The first blind hole 24 and the second blind hole 26 can be formed by a method of through-hole laser etching.

In the third step, referring to FIG. 5, a third conductive circuit layer 44 and a fourth conductive circuit layer 46 are formed on the surfaces of the first glass substrate 20 and the second glass substrate 22, respectively, and the first blind vias 24 and A first via hole 242 electrically connecting the first conductive circuit layer 102 and the third conductive circuit layer 44 and a second portion electrically connecting the second conductive circuit layer 103 and the fourth conductive circuit layer 46 are formed in the two blind vias 26 Two guiding blind holes 262. The third conductive circuit layer 44 includes a plurality of third electrical connection pads 442 , and the fourth conductive circuit layer 46 includes a plurality of fourth electrical connection pads 462 .

The third conductive circuit layer 44 and the first guiding hole 242 can be formed by the following method. Forming a continuous seed layer on the inner wall of the plurality of first blind holes 24, the surface of the plurality of first electrical connection pads 107, and the surface of the first glass substrate 20; forming a surface of the first glass substrate 20 a patterned photoresist layer exposing the plurality of first blind vias 24; forming a plated copper layer on a surface of the seed layer exposed to the photoresist layer by electroplating And removing the photoresist layer and removing a portion of the seed layer covered by the photoresist layer, and a seed layer and a copper plating layer remaining on the surface of the first glass substrate 20 constitute the third The conductive circuit layer 44, the seed layer and the electroplated copper layer in the plurality of first blind vias 24 constitute the plurality of first via holes 242. The seed layer is a thin copper layer formed by electroless copper plating or copper sputtering.

Of course, the third conductive circuit layer 44 and the first via hole 242 can also be formed by filling the plurality of first blind vias 24 with a conductive paste; forming a continuous seed on the surface of the first glass substrate 20. Forming a patterned photoresist layer on the surface of the first glass substrate 20, and a seed layer opposite to the plurality of first blind vias 24 is exposed to the photoresist layer; Forming an electroplated copper layer on a surface of the seed layer of the photoresist layer; and removing the photoresist layer and removing a portion of the seed layer covered by the photoresist layer, remaining in the The seed layer and the electroplated copper layer on the surface of the first glass substrate 20 constitute the third conductive circuit layer 44. The conductive paste in the plurality of first blind holes 24 constitutes the plurality of first guiding holes 242. The seed layer is a thin copper layer formed by electroless copper plating or copper sputtering.

The fourth conductive circuit layer 46 and the second via hole 262 are fabricated in the same manner as the third conductive circuit layer 44 and the first via hole 242.

In the fourth step, referring to FIG. 6, a first dielectric layer 50 and a fifth conductive wiring layer 52 are sequentially formed on the third conductive wiring layer 44 side, and a second dielectric layer is sequentially formed on the fourth conductive wiring layer 46 side. 60 and a sixth conductive circuit layer 62, and electrically connected to the third conductive line The road layer 44 and the plurality of third guiding holes 522 of the fifth conductive circuit layer 52 and the plurality of fourth guiding holes 622 electrically connecting the fourth conductive circuit layer 46 and the sixth conductive circuit layer 62. The fifth conductive circuit layer 52 includes a plurality of fifth electrical connection pads 524, and the sixth conductive circuit layer 62 includes a plurality of sixth electrical connection pads 624.

The first dielectric layer 50 and the second dielectric layer 60 may be formed by press curing of a prepreg film, which may be an epoxy resin. The fifth conductive circuit layer 52 and the third conductive via 522 and the sixth conductive circuit layer 62 and the fourth conductive via 622 are fabricated in a similar manner to the third conductive circuit layer 44 and the first via hole 242. One end of the plurality of third guiding holes 522 is electrically connected to the fifth conductive circuit layer 52, and the other end is electrically connected to the plurality of third electrical connecting pads 442, one end of the plurality of fourth guiding holes 622 The sixth conductive circuit layer 62 is electrically connected, and the opposite ends are electrically connected to the plurality of fourth electrical connection pads 462, respectively.

In the fifth step, referring to FIG. 7, a first solder resist layer 70 is formed on the fifth conductive circuit layer 52 side, a second solder resist layer 72 is formed on the sixth conductive trace layer 62 side, and the fifth electrical layer is formed. The surface of the connection pad 524 and the sixth electrical connection pad 624 form a surface treatment layer 74 to form a chip package substrate strip (not labeled).

The first solder resist layer 70 covers the surface of the first dielectric layer 50 exposed on the fifth conductive circuit layer 52 and a portion of the fifth conductive circuit layer 52. The plurality of fifth electrical connection pads 524 are exposed to the first The solder resist layer 70 covers the surface of the second dielectric layer 60 exposed on the sixth conductive circuit layer 62 and a portion of the sixth conductive circuit layer 62. The plurality of sixth electrical connection pads 624 Exposed to the second solder mask layer 72. The plurality of fifth electrical connection pads 524 are for electrically connecting to a wafer to be packaged, and the plurality of sixth electrical connection pads 624 are for electrically connecting with other electronic devices such as a package substrate or a circuit board.

In this embodiment, the surface treatment layer 74 is formed by electroplating gold. Understandably, The method of forming the surface treatment layer 74 may be replaced by nickel plating gold, nickel immersion gold plating, nickel plating palladium gold plating, tin plating, or the like, and is not limited to the embodiment. Of course, the surface treatment layer 74 may be omitted.

In the first step to the fifth step of the embodiment, the plurality of core unit 106 are connected together for processing. Therefore, the chip package substrate strip formed after the fifth step includes a plurality of array type chip package substrate units.

In the sixth step, a plurality of chip package substrate strips connected together are cut to form a plurality of wafer package substrates 100 having the same structure. The cutting method can be laser cutting, mechanical cutting or punching.

Referring to FIG. 7, the chip package substrate 100 of the present embodiment includes a circuit board core board 10, and a first glue layer 30, a first glass substrate 20, and a third conductive line are sequentially stacked along one side of the circuit board core board 10. The layer 44, the first dielectric layer 50, the fifth conductive circuit layer 52 and the first solder resist layer 70, and the second adhesive layer 32 and the second glass which are sequentially stacked along the opposite side of the circuit board core board 10 The substrate 22, the fourth conductive wiring layer 46, the second dielectric layer 60, the sixth conductive wiring layer 62, and the second solder resist layer 72. The circuit board core board 10 includes an insulating substrate 101 and a first conductive circuit layer 102 and a second conductive circuit layer 103 disposed on opposite sides of the insulating substrate 101. The first conductive circuit layer 102 and the second conductive circuit layer 103 pass through The via holes penetrating the first conductive wiring layer 102, the insulating substrate 101, and the second conductive wiring layer 103 are electrically connected. The first adhesive layer 30 covers the first conductive circuit layer 102 and the first surface 104 exposed on the first conductive circuit layer 102. The second adhesive layer 32 covers the second conductive circuit layer 103 and is exposed to the second surface. a second surface 105 of the conductive circuit layer 103, the first glass substrate 20 and the second glass substrate 22 are adhered to the first adhesive layer 30 and the second adhesive layer 32, respectively, the third conductive circuit layer 44 and the fourth Conductive wiring layers 46 are formed on the first glass substrate 20 and the second glass substrate, respectively 22 away from the surface of the circuit board core board 10, the third conductive circuit layer 44 is electrically connected to the first conductive circuit layer 102 through a first guiding hole 242 formed in the first glass substrate 20, the fourth conductive line The layer 46 is electrically connected to the second conductive wiring layer 103 through a second via hole 262 formed in the second glass substrate 22. The fifth conductive circuit layer 52 is electrically connected to the third conductive circuit layer 44 through the third via hole 522, and the sixth conductive circuit layer 62 is electrically connected to the fourth conductive circuit layer 46 through the fourth via hole 622. The first solder resist layer 70 covers the surface of the first dielectric layer 50 exposed on the fifth conductive circuit layer 52 and a portion of the fifth conductive circuit layer 52. The plurality of fifth electrical connection pads 524 are exposed to the first The solder resist layer 70; the second solder resist layer 72 covers the surface of the second dielectric layer 60 exposed on the sixth conductive circuit layer 62 and a portion of the sixth conductive trace layer 62. The plurality of sixth electrical connection pads 624 Exposed to the second solder mask layer 72.

In a seventh step, referring to FIG. 8 and FIG. 9, a wafer 80 is provided, and the wafer 80 is packaged on the chip package substrate 100 to form a chip package structure 200.

In this embodiment, the flip-chip package is taken as an example. The wafer 80 includes a wafer body 82 and a plurality of solder bumps 84 corresponding to the fifth electrical connection pads 524 . The solder bumps 84 and the wafer body 82 . The internal circuit is electrically connected. The step of packaging the wafer 80 on the chip package substrate 100 is as follows. First, solder balls 526 are formed on the surface of the surface treatment layer 74 corresponding to the plurality of fifth electrical connection pads 524. The material of the ball 526 generally consists primarily of tin.

Next, the wafer 80 is placed on the chip package substrate 100, and the plurality of solder bumps 84 are respectively brought into contact with the corresponding solder balls 526.

Further, the wafer 80 and the chip package substrate 100 are passed through a reflow furnace, and the solder bumps 84 and the solder balls 526 are melted and combined to be cooled and solidified, thereby causing a plurality of solder bumps. Blocks 84 are interconnected and electrically connected to corresponding solder balls 526, respectively. As shown in FIG. 9, the solder bumps 84 and the solder balls 526 are fused together to form a larger solder ball 528.

Finally, the underfill 530 is filled in the gap between the wafer 80 and the chip package substrate 100 to package and fix the wafer 80 and the chip package substrate 100. The underfill 530 adheres to the surface of the crystal piece 80 and the surface of the first solder resist 70, and surrounds the solder balls 528 formed by fusion bonding of the solder bumps 84 and the solder balls 526, thereby forming the chip package structure 200. The underfill 530 is typically an epoxy such as the underfill material Loctite 3536.

In this embodiment, each of the chip package substrates 100 is used to package one package wafer 80, thereby forming a plurality of wafer package structures 200. It can be understood that the step of packaging the wafer 80 on the chip package substrate 100 may also be performed after the fifth step and the sixth step, after the plurality of wafers 80 are packaged on the plurality of wafer package substrates 100, and then the cutting step of the sixth step is performed. A plurality of wafer package structures 200 are obtained.

It can be understood that the first dielectric layer 50 and the fifth conductive circuit layer 52 may also be omitted, and the first solder resist layer 70 is formed on the surface of the first glass substrate 20 and a portion of the surface of the third conductive circuit layer 44. The wafer 80 is directly electrically connected to the third conductive wiring layer 44; of course, the second dielectric layer 60 and the sixth conductive wiring layer 62 may be omitted, and the second solder resist layer 72 is formed on the second glass substrate. 22 surface and a portion of the surface of the fourth conductive wiring layer 46. It can also be understood that the layer can be further formed between the fifth conductive circuit layer 52 and the first solder resist layer 70 and between the sixth conductive circuit layer 62 and the second solder resist layer 72 to form more conductive lines. A layer of wafer package substrate.

Compared with the prior art, in the embodiment, when the first blind hole 24 is formed on the first glass substrate 20 and the second blind hole 26 is formed on the second glass substrate 22, the first glass substrate 20 and the second glass are formed. The substrate 22 is supported by the circuit board core board 10, thereby preventing the first glass The chipping of the glass substrate 20 and the second glass substrate 22 during processing facilitates the fabrication of the chip package substrate 100 and improves the fabrication yield of the chip package substrate 100. In addition, an ultrafine line can be formed on the glass substrate and the line pitch can be made fine, so that the number of layers of the conductive wiring layer of the entire chip package substrate 100 can be reduced to reduce the thickness of the wafer package substrate 100, and the first A glass substrate 20 and a second glass substrate 22 can electrically connect semiconductor packages having high-density solder joints, thereby making the wafer package substrate 100 more versatile.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application in this case. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

200‧‧‧ Chip package structure

74‧‧‧Surface treatment layer

80‧‧‧ wafer

524‧‧‧The fifth electrical connection pad

528‧‧‧ solder balls

530‧‧‧Bottom filler

Claims (10)

A method for fabricating a chip package substrate, comprising the steps of: providing a circuit board core board, comprising: an insulation substrate; and forming a first conductive circuit layer and a second conductive circuit layer on opposite sides of the insulation substrate, the first conductive circuit layer comprising a plurality of a first electrical connection pad, the second conductive circuit layer includes a plurality of second electrical connection pads; a first adhesive layer is disposed on the surface of the first conductive circuit layer and the insulating substrate exposed on the first conductive circuit layer, And bonding the first glass substrate to the first adhesive layer; forming a third conductive circuit layer on the surface of the first glass substrate, and forming a plurality of first through the first glass substrate and the first adhesive layer The guiding hole is electrically connected to the third conductive circuit layer at one end of the plurality of first guiding holes, and the opposite ends are electrically connected to the plurality of first electrical connecting pads respectively to form a chip package substrate. The method for fabricating a chip package substrate according to claim 1, wherein the method for fabricating the third conductive circuit layer and the first via hole comprises the steps of: forming a plurality of holes on the first glass substrate by a laser etching process a plurality of first blind holes respectively exposing the plurality of first electrical connection pads through the first blind holes of the first glass substrate and the first adhesive layer; and an inner wall of the plurality of first blind holes a surface of the first electrical connection pad and the surface of the first glass substrate form a continuous seed layer; forming a patterned photoresist layer on the surface of the first glass substrate, the photoresist layer exposing the plurality of layers a first blind via; forming a plated copper layer on the surface of the seed layer exposed to the photoresist layer by electroplating; and removing the photoresist layer and removing the seed layer by the photo-induced Part covered by the resist layer The seed layer and the electroplated copper layer remaining on the surface of the first glass substrate constitute the third conductive circuit layer, and the seed layer and the electroplated copper layer in the plurality of first blind holes constitute the plurality of first guiding holes. The method for fabricating a chip package substrate according to claim 1, wherein the method for fabricating the third conductive circuit layer and the first via hole comprises the steps of: forming a plurality of holes on the first glass substrate by a laser etching process a first blind via extending through the first glass substrate and the first adhesive layer, the plurality of first blind vias respectively exposing the plurality of first electrical connection pads; filling the plurality of first blind vias with a conductive paste; Forming a continuous seed layer on the surface of the first glass substrate; forming a patterned photoresist layer on the surface of the first glass substrate, and the seed layer opposite to the plurality of first blind holes is exposed to the photoresist a layer; forming a plated copper layer on a surface of the seed layer exposed to the photoresist layer by electroplating; and removing the photoresist layer and removing the seed layer by the photoresist layer The covered portion and the seed layer and the electroplated copper layer remaining on the surface of the first glass substrate constitute the third conductive circuit layer, and the plurality of first blind via conductive pastes constitute the plurality of first via holes. The method of fabricating a chip package substrate according to claim 1, wherein after forming the third conductive circuit layer and the first via hole, the method further comprises the steps of: sequentially forming a first dielectric layer on the third conductive circuit layer side An electric layer and a fifth conductive circuit layer; and a first solder resist layer formed on the fifth conductive circuit layer side, the first solder resist layer covering a portion of the fifth conductive circuit layer, exposed to the first solder resist layer The fifth conductive circuit layer constitutes a fifth electrical connection pad for electrically connecting to the wafer to be packaged. The method of fabricating a chip package substrate according to claim 1, wherein the first glass substrate protrudes from a surface of the first adhesive layer or is embedded in the first adhesive layer. The method of fabricating a chip package substrate according to claim 1, wherein the method of fabricating the chip package substrate further comprises the steps of: disposing a surface of the second conductive circuit layer and the insulating substrate on a surface of the second conductive circuit layer; a second adhesive layer, and bonding the second glass substrate to the second adhesive layer; and forming a fourth conductive circuit layer on the surface of the second glass substrate, and forming a plurality of through the second glass substrate and the second adhesive a second guiding blind hole of the layer, one end of the plurality of second guiding blind holes is electrically connected to the fourth conductive circuit layer, and the opposite other ends are electrically connected to the plurality of second electrical connecting pads respectively. The method of fabricating a chip package substrate according to claim 6, wherein the method for fabricating the chip package substrate further comprises the step of sequentially forming a second dielectric layer and a sixth conductive layer on the fourth conductive circuit layer side. And forming a second solder resist layer on the sixth conductive circuit layer side, the second solder resist layer covering a portion of the sixth conductive circuit layer, and the sixth conductive circuit layer exposed on the second solder resist layer constitutes a sixth electric The connection pad is electrically connected to other package substrates or circuit boards. A chip package substrate comprising: a circuit board core board comprising: an insulating substrate; and a first conductive circuit layer and a second conductive circuit layer forming opposite sides of the insulating substrate, the first conductive circuit layer and the second conductive circuit layer Electrically connecting, the first conductive circuit layer includes a plurality of first electrical connection pads, the second conductive circuit layer includes a plurality of second electrical connection pads; and a first adhesive layer, a first glass substrate, and a third conductive line a layer, the first adhesive layer is formed on the surface of the first conductive circuit layer, and the insulating substrate is exposed on the surface of the first conductive circuit layer, the first glass substrate is adhered to the first adhesive layer, and the third The conductive circuit layer is formed on the surface of the first glass substrate, and is electrically connected to the plurality of first electrical connection pads respectively through a plurality of first guiding holes formed on the first glass substrate and the first adhesive layer. The chip package substrate of claim 8, wherein the chip package substrate further comprises a second a film, a second glass substrate and a fourth conductive circuit layer, the second adhesive layer is formed on the surface of the second conductive circuit layer and the insulating substrate is exposed on the surface of the second conductive circuit layer, and the second glass substrate is bonded On the second adhesive layer, the fourth conductive circuit layer is formed on the surface of the second glass substrate, and through the plurality of second guide holes formed on the second glass substrate and the second adhesive layer, the plurality of The two electrical connection pads are electrically connected respectively. The chip package substrate according to claim 8, wherein the chip package substrate further comprises a first dielectric layer, a fifth conductive circuit layer and a first solder resist layer which are sequentially stacked on one side of the third conductive circuit layer, and Forming a second dielectric layer, a sixth conductive circuit layer and a second solder resist layer disposed on one side of the fourth conductive circuit layer, the fifth conductive circuit layer being formed on the first dielectric layer, the first protection The fifth conductive layer is formed on the fifth conductive layer, and the fifth conductive layer is exposed on the first solder resist layer. The sixth conductive layer is formed on the second dielectric layer. The second solder resist layer covers a portion of the sixth conductive circuit layer, and the sixth conductive circuit layer exposed to the second solder resist layer constitutes a sixth electrical connection pad.