CN104112673B - Chip package base plate and preparation method thereof - Google Patents
Chip package base plate and preparation method thereof Download PDFInfo
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- CN104112673B CN104112673B CN201310137349.5A CN201310137349A CN104112673B CN 104112673 B CN104112673 B CN 104112673B CN 201310137349 A CN201310137349 A CN 201310137349A CN 104112673 B CN104112673 B CN 104112673B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
A kind of chip package base plate, including circuit board core plate, the first glue-line, the first substrate of glass and the 3rd conductive circuit layer.The circuit board core plate includes dielectric base and forms first conductive circuit layer and the second conductive circuit layer of the dielectric base opposite sides, and first conductive circuit layer includes multiple first electric connection pads, and second conductive circuit layer includes multiple second electric connection pads.First glue-line is formed at the first conducting wire layer surface and the dielectric base is exposed on the surface of first conductive circuit layer, first substrate of glass is adhered on first glue-line, 3rd conductive circuit layer is formed at first glass basic surface, and is electrically connected with the plurality of first electric connection pad by being formed at multiple first guide holes of first substrate of glass and the first glue-line.The invention further relates to a kind of preparation method of said chip package substrate.
Description
Technical field
The present invention relates to circuit board making field, more particularly to a kind of chip package base plate and preparation method thereof.
Background technology
Chip package base plate can provide the effects such as electrical connection, protection, support, radiating, assembling for chip, to realize many pins
Change, reduce encapsulating products volume, improve the purpose of electrical property and thermal diffusivity, VHD or multi-chip module.
Existing chip package base plate includes one or more layers dielectric base and is formed at the dielectric base side or relative
The conductive circuit layer of both sides.Growing with chip technology, the circuit spacing in chip is more and more thinner so that carry chip
Chip package base plate in the spacing of conducting wire also require that increasingly thinner, cause the manufacture difficulty of chip package base plate more next
Bigger, manufacturing cost increases.Under the high-density packages demand of chip, industry also has using glass material as dielectric base,
Making dielectric base using glass material can accomplish the ultra fine-line requirement of conductive circuit layer.However, chip package base plate is exhausted
Edge substrate is general all very thin, and when glass material is made into very thin dielectric base, glass material easily fragmentation causes chip to seal
The manufacture difficulty for filling substrate is big, makes yield low.
The content of the invention
Therefore, it is necessary to provide a kind of making easily and yield chip package base plate high and preparation method thereof.
A kind of preparation method of chip package base plate, including step：Circuit board core plate, including dielectric base and formation are provided
First conductive circuit layer and the second conductive circuit layer of the dielectric base opposite sides, first conductive circuit layer include multiple the
One electric connection pad, second conductive circuit layer includes multiple second electric connection pads；In first conductive circuit layer and this is exhausted
Edge substrate be exposed to first conductive circuit layer surface set the first glue-line, and just the first substrate of glass be adhered to this first
On glue-line；And the 3rd conductive circuit layer is formed in first glass basic surface, and form multiple through first substrate of glass
With the first guide hole of the first glue-line, the one end in the plurality of first guide hole is electrically connected to the 3rd conductive circuit layer, relative
The other end is electrically connected in the plurality of first electric connection pad, so as to form chip package base plate.
A kind of chip package base plate, including circuit board core plate, the first glue-line, the first substrate of glass and the 3rd conducting wire
Layer.The circuit board core plate includes dielectric base and forms first conductive circuit layer and the second conduction of the dielectric base opposite sides
Line layer, first conductive circuit layer includes multiple first electric connection pads, and second conductive circuit layer includes multiple second electricity
Property connection gasket.First glue-line is formed at the first conducting wire layer surface and the dielectric base is exposed to first conducting wire
On the surface of layer, first substrate of glass is adhered on first glue-line, and the 3rd conductive circuit layer is formed at first glass
Substrate surface, and it is electrical with the plurality of first by being formed at multiple first guide holes of first substrate of glass and the first glue-line
Connection gasket is electrically connected.
In the present embodiment, when forming the first blind hole in the first substrate of glass, first substrate of glass is by circuit board core plate
Supported, so as to prevent fragmentation of first substrate of glass in processing, making the making of chip package base plate becomes easy, and improves
The making yield of chip package base plate.In addition, ultra fine-line and circuit spacing can be made in substrate of glass can also do
It is very thin, therefore can reduce whole chip package base plate conductive circuit layer the number of plies to reduce the thickness of chip package base plate
Degree, and cause that first substrate of glass can electrically connect the semiconductor package part with high-density spot, so that chip package base
The applicability of plate is wider.
Brief description of the drawings
Fig. 1 is the top view of circuit board core plate provided in an embodiment of the present invention and substrate of glass.
Fig. 2 is the enlarged drawing of the II parts of circuit board core plate shown in Fig. 1 and substrate of glass.
Fig. 3 is the circuit board core plate of Fig. 2 and the sectional view of substrate of glass.
Fig. 4 is that the sectional view after blind hole is formed in the substrate of glass of Fig. 3.
Fig. 5 is the sectional view after conductive circuit layer is formed in the substrate of glass of Fig. 4 and guide hole is formed in blind hole.
Fig. 6 is that the sectional view after increasing layer is carried out on the circuit board of Fig. 5.
Fig. 7 is the sectional view of the chip package base plate formed after the circuit board both sides of Fig. 6 form welding resisting layer.
Fig. 8 is that the sectional view after chip is set on the chip package base plate of Fig. 7.
Fig. 9 is the sectional view of the chip-packaging structure formed after the chip of Fig. 8 is packaged.
Figure 10 is another implementation method of the annexation of circuit board core plate in Fig. 3 and substrate of glass.
Main element symbol description
| Circuit board core plate | 10 |
| Dielectric base | 101 |
| First substrate of glass | 20 |
| Second substrate of glass | 22 |
| First conductive circuit layer | 102 |
| Second conductive circuit layer | 103 |
| First surface | 104 |
| Second surface | 105 |
| Core plate unit | 106 |
| First electric connection pad | 107 |
| Second electric connection pad | 108 |
| First glue-line | 30 |
| Second glue-line | 32 |
| First blind hole | 24 |
| Second blind hole | 26 |
| 3rd conductive circuit layer | 44 |
| 4th conductive circuit layer | 46 |
| First guide hole | 242 |
| Second guide hole | 262 |
| 3rd electric connection pad | 442 |
| 4th electric connection pad | 462 |
| First dielectric layer | 50 |
| 5th conductive circuit layer | 52 |
| Second dielectric layer | 60 |
| 6th conductive circuit layer | 62 |
| 3rd guide hole | 522 |
| 4th guide hole | 622 |
| 5th electric connection pad | 524 |
| 6th electric connection pad | 624 |
| First welding resisting layer | 70 |
| Second welding resisting layer | 72 |
| Surface-treated layer | 74 |
| Chip package base plate | 100 |
| Chip | 80 |
| Chip-packaging structure | 200 |
| Chip body | 82 |
| Solder projection | 84 |
| Soldered ball | 526,528 |
| Underfill | 530 |
Following specific embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.
Specific embodiment
Fig. 1 to 9 is referred to, the embodiment of the present invention provides a kind of preparation method of chip-packaging structure, comprises the following steps：
The first step, refers to Fig. 1 to Fig. 3, there is provided circuit board core plate 10, distinguishes in the opposite sides of the circuit board core plate 10
First glue-line 30 and the second glue-line 32 are set, and just multiple first substrate of glass 20 are adhered on first glue-line 30, will be many
Individual second substrate of glass 22 is adhered on second glue-line 32.
The circuit board core plate 10 includes dielectric base 101 and is arranged at the first conduction of the opposite sides of dielectric base 101
The conductive circuit layer 103 of line layer 102 and second, the dielectric base 101 includes relative first surface 104 and second surface 105,
The conductive circuit layer 103 of first conductive circuit layer 102 and second is respectively formed in the first surface 104 and second surface 105, should
First conductive circuit layer 102 and the second conductive circuit layer 103 by insertion first conductive circuit layer 102, dielectric base 101 and
The via (not shown) of the second conductive circuit layer 103 realizes electrical connection.In the present embodiment, the circuit board core plate 10 includes array
Multiple core plate units 106 of formula arrangement, for forming multiple mutually isostructural chip package base plates, Fig. 1 and Fig. 2 are separated by with dotted line
Open, the quantity of the core plate unit 106 in actual production is not limited thereto.The first conductor wire in the plurality of core plate unit 106
The structure of the conducting wire of road floor 102 is identical, and the second conductive circuit layer 103 in the plurality of core plate unit 106 is identical.Each core
The first conductive circuit layer 102 in Slab element 106 includes multiple first electric connection pads 107, in each core plate unit 106
Second conductive circuit layer 103 includes multiple second electric connection pads 108.
First glue-line 30 covers first conductive circuit layer 102 and is exposed to the first of first conductive circuit layer 102
Surface 104, second glue-line 32 covers second conductive circuit layer 103 and is exposed to the second of second conductive circuit layer 103
Surface 105, the plurality of first substrate of glass 20 is adhered to first glue-line 30 and second respectively with multiple second substrate of glass 22
On glue-line 32, i.e., the opposite sides of each core plate unit 106 is respectively arranged with the first substrate of glass 20 and the second substrate of glass 22.
The glue-line 32 of first glue-line 30 and second can be pure glue.In the present embodiment, the plurality of first substrate of glass 20 is bonded simultaneously respectively
The convex surface in the first glue-line 30, the plurality of second substrate of glass 22 is bonded and the convex surface in the second glue-line 32 respectively.Can be with
Understand, as shown in Figure 10, the plurality of first substrate of glass 20 can also be respectively embedded into the first glue-line 30, the plurality of second glass
Substrate 22 can also be respectively embedded into the second glue-line 32, be not limited with the present embodiment.
For purposes of illustration only, the present embodiment forms multiple chip package base plate units of separation since the first step to cutting
Multiple steps, for the plurality of core plate unit 106 and the system of the corresponding substrate of glass 22 of multiple first substrate of glass 20 and second
Cheng Junwei is carried out simultaneously.The present embodiment is for purposes of illustration only, form separate multiple chip package base plate lists from second step to cutting
The step of unit, with for one of core plate unit 106 and its substrate of glass 22 of corresponding first substrate of glass 20 and second
Processing procedure as a example by illustrate.
Second step, refers to Fig. 4, is formed from the side of the first substrate of glass 20 and runs through the glue of the first substrate of glass 20 and first
Layer 30 and multiple first blind holes 24 of the plurality of first electric connection pad 107 are exposed respectively, in the side shape of the second substrate of glass 22
Into exposing through the glue-line 32 of the second substrate of glass 22 and second and respectively multiple the second of the plurality of second electric connection pad 108
Blind hole 26.The blind hole 26 of first blind hole 24 and second can the method for through hole laser pit make to be formed.
3rd step, refers to Fig. 5, and formation is made respectively on the surface of 20 and second substrate of glass of the first substrate of glass 22
Three conductive circuit layers 44 and the 4th conductive circuit layer 46, and formed in the blind hole 26 of first blind hole 24 and second electrical connection this
First guide hole 242 of one conductive circuit layer 102 and the 3rd conductive circuit layer 44 and electrically connect second conductive circuit layer 103
With the second guide hole 262 of the 4th conductive circuit layer 46.3rd conductive circuit layer 44 includes multiple 3rd electric connection pads
442, the 4th conductive circuit layer 46 includes multiple 4th electric connection pads 462.
3rd conductive circuit layer 44 and the first guide hole 242 can adopt to make with the following method and be formed：The plurality of
The inwall of one blind hole 24, the surface of the plurality of first electric connection pad 107 and the surface of the first substrate of glass 20 are formed continuously
Seed Layer；The photoresist layer of patterning is formed on the surface of the first substrate of glass 20, it is many that the photoresist layer exposes this
Individual first blind hole 24；Copper electroplating layer is formed on the surface for being exposed to the Seed Layer of the photoresist layer by electric plating method；
And remove the photoresist layer, and remove the part that the Seed Layer is covered by the photoresist layer, remain in this first
The Seed Layer and copper electroplating layer on the surface of substrate of glass 20 constitute the 3rd conductive circuit layer 44, the kind in the plurality of first blind hole 24
Sublayer and copper electroplating layer constitute the plurality of first guide hole 242.The Seed Layer is by electroless copper or splashes copper coating shape
Into thin copper layer.
Certainly, the 3rd conductive circuit layer 44 and the first guide hole 242 can also adopt to make with the following method and be formed：At this
Filling conductive paste in multiple first blind holes 24；Continuous Seed Layer is formed on the surface of the first substrate of glass 20；In first glass
The surface of glass substrate 20 forms the photoresist layer of patterning, and the Seed Layer relative with the plurality of first blind hole 24 is exposed to the light
Cause resist layer；Copper electroplating layer is formed on the surface for being exposed to the Seed Layer of the photoresist layer by electric plating method；And
The photoresist layer is removed, and removes the part that the Seed Layer is covered by the photoresist layer, remain in first glass
The Seed Layer and copper electroplating layer on the surface of glass substrate 20 constitute the 3rd conductive circuit layer 44, conductive paste in the plurality of first blind hole 24
Constitute the plurality of first guide hole 242.The Seed Layer is by electroless copper or splashes the thin copper layer that copper coating is formed.
The preparation method in the 4th conductive circuit layer 46 and the second guide hole 262 and the 3rd conductive circuit layer 44 and first
The preparation method in guide hole 242 is identical.
4th step, refers to Fig. 6, and it is conductive to sequentially form the first dielectric layer 50 and the 5th in the side of the 3rd conductive circuit layer 44
Line layer 52, sequentially forms the second dielectric layer 60 and the 6th conductive circuit layer 62, and formed in the side of the 4th conductive circuit layer 46
Electrically connect the 3rd conductive circuit layer 44 and the 5th conductive circuit layer 52 multiple 3rd guide holes 522 and electrically connect this
Multiple 4th guide holes 622 of four conductive circuit layers 46 and the 6th conductive circuit layer 62.5th conductive circuit layer 52 includes
Multiple 5th electric connection pads 524, the 6th conductive circuit layer 62 includes multiple 6th electric connection pads 624.
The dielectric layer 60 of first dielectric layer 50 and second can be solidify to form by the pressing of semi-solid preparation film, and the semi-solid preparation film can
Think epoxy resin.5th conductive circuit layer 52 and the 3rd guide hole 522 and the 6th conductive circuit layer 62 and the 4th guide
The preparation method in hole 622 is similar with the preparation method of the 3rd conductive circuit layer 44 and the first guide hole 242.The plurality of 3rd guide
The one end in hole 522 electrically connects the 5th conductive circuit layer 52, and the relative other end is electrically connected the plurality of 3rd electric connection
Pad 442, the one end in the plurality of 4th guide hole 622 electrically connects the 6th conductive circuit layer 62, and the relative other end is electrically connected respectively
Connect the plurality of 4th electric connection pad 462.
5th step, refers to Fig. 7, and the first welding resisting layer 70 is formed in the side of the 5th conductive circuit layer 52, conductive the 6th
The side of line layer 62 forms the second welding resisting layer 72, and is formed in the 5th electric connection pad 524 and the surface of the 6th electric connection pad 624
Surface-treated layer 74, forms chip package base plate bar (sign).
The surface of the first dielectric layer 50 and part that first welding resisting layer 70 covering is exposed to the 5th conductive circuit layer 52 should
5th conductive circuit layer 52, the plurality of 5th electric connection pad 524 is exposed to first welding resisting layer 70, and second welding resisting layer 72 covers
Lid is exposed to the 6th conductive circuit layer 62 of the surface of the second dielectric layer 60 and part of the 6th conductive circuit layer 62, the plurality of the
Six electric connection pads 624 are exposed to second welding resisting layer 72.The plurality of 5th electric connection pad 524 is used for and chip to be packaged
Electrical connection, the plurality of 6th electric connection pad 624 is used to be electrically connected with other electronic devices such as package substrate or circuit board.
In the present embodiment, it is plating gold to form the mode of the surface-treated layer 74.It is appreciated that forming the surface-treated layer
74 method can also be substituted by plating nickel gold, change nickel leaching gold, plating NiPdAu, tin plating etc., be not limited with the present embodiment, certainly,
The surface-treated layer 74 can also be omitted.
In the first step of the present embodiment to the 5th step, multiple core plate units 106 link together and are processed, therefore, the
The chip package base plate bar formed after five steps includes multiple array chip package substrate units.
6th step, the chip package base plate bar that multiple is linked together is cut, and forms multiple structure identical cores
Piece package substrate 100.Cutting method can be using methods such as laser cutting, machine cuts or punchings.
Fig. 7 is referred to, the chip package base plate 100 of the present embodiment includes circuit board core plate 10, along the circuit board core plate 10
The first glue-line 30, the first substrate of glass 20, the 3rd conductive circuit layer 44, the first dielectric layer that wherein side is cascading
50th, the 5th conductive circuit layer 52 and the first welding resisting layer 70, and be cascading along the relative opposite side of the circuit board core plate 10
The second glue-line 32, the second substrate of glass 22, the 4th conductive circuit layer 46, the second dielectric layer 60, the 6th conductive circuit layer 62 and
Second welding resisting layer 72.The circuit board core plate 10 includes dielectric base 101 and is arranged at the first of the opposite sides of dielectric base 101
The conductive circuit layer 103 of conductive circuit layer 102 and second, first conductive circuit layer 102 is with the second conductive circuit layer 103 by passing through
Lead to first conductive circuit layer 102, the via of the conductive circuit layer 103 of dielectric base 101 and second realizes electrical connection.This first
Glue-line 30 covers first conductive circuit layer 102 and is exposed to the first surface 104 of first conductive circuit layer 102, and this second
Glue-line 32 covers second conductive circuit layer 103 and is exposed to the second surface 105 of second conductive circuit layer 103, and this first
The substrate of glass 22 of substrate of glass 20 and second is adhered on the glue-line 32 of the first glue-line 30 and second respectively, the 3rd conducting wire
The conductive circuit layer 46 of layer 44 and the 4th is respectively formed in the substrate of glass 22 of the first substrate of glass 20 and second away from the circuit board
The surface of core plate 10, the 3rd conductive circuit layer 44 is electrically connected by being formed at the first guide hole 242 of first substrate of glass 20
First conductive circuit layer 102 is connected to, the 4th conductive circuit layer 46 is led by being formed at the second of second substrate of glass 22
Blind hole 262 is electrically connected to second conductive circuit layer 103.5th conductive circuit layer 52 is electrically connected by the 3rd guide hole 522
In the 3rd conductive circuit layer 44, the 6th conductive circuit layer 62 is electrically connected to the 4th conductor wire by the 4th guide hole 622
Road floor 46.First welding resisting layer 70 covering be exposed to the 5th conductive circuit layer 52 the surface of the first dielectric layer 50 and part this
Five conductive circuit layers 52, the plurality of 5th electric connection pad 524 is exposed to first welding resisting layer 70；Second welding resisting layer 72 is covered
It is exposed to the 6th conductive circuit layer 62 of the surface of the second dielectric layer 60 and part of the 6th conductive circuit layer 62, the plurality of 6th
Electric connection pad 624 is exposed to second welding resisting layer 72.
7th step, refers to Fig. 8 and Fig. 9, there is provided chip 80, and by chip package in the chip package base plate 100, is formed
Chip-packaging structure 200.
The present embodiment illustrates that the chip 80 includes that chip body 82 and multiple are electrical with the 5th by taking chip package as an example
The one-to-one solder projection 84 of connection gasket 524, the solder projection 84 is electrically connected with the internal wiring of the chip body 82, the core
The step of piece 80 is packaged in chip package base plate 100 is as follows：
First, soldered ball 526 is formed respectively on the surface of 524 corresponding surface-treated layer of the plurality of 5th electric connection pad 74,
The material of the plurality of soldered ball 526 typically mainly includes tin.
Secondly, chip 80 is arranged on chip package base plate 100, and make the plurality of solder projection 84 respectively with it is corresponding
Soldered ball 526 is in contact.
Further, the chip 80 and chip package base plate 100 are made into solder projection 84 and soldered ball together through Overwelding and rewelding furnace
Cooled and solidified after 526 melt bindings, so that multiple solder projections 84 are connected with each other and conductance with corresponding soldered ball 526 respectively
It is logical.As shown in figure 9, forming bigger soldered ball 528 after the solder projection 84 and the melt binding of soldered ball 526.
Finally, underfill 530 is filled in the gap between the chip 80 and chip package base plate 100, so that
The chip 80 and chip package base plate 100 are encapsulated into fixation.Underfill 530 bonds the surface of chip 80 and first anti-welding
The surface of layer 70, and the soldered ball 528 by being formed after solder projection 84 and the melt binding of soldered ball 526 is surrounded, so as to form chip envelope
Assembling structure 200.The underfill 530 typically uses epoxy resin, such as underfill agent material Loctite 3536.
The present embodiment, each chip package base plate 100 is respectively used to one encapsulation chip 80 of encapsulation, so as to form multiple cores
Chip package 200.It is appreciated that chip 80 can also be after the 5th step, the step of being packaged in chip package base plate 100
Before six steps, after multiple chips 80 are packaged in into multiple chip package base plates 100, then the cutting step of the 6th step is carried out, obtained
Multiple chip-packaging structures 200.
It is understood that the conductive circuit layer 52 of the first dielectric layer 50 and the 5th can also be omitted, and it is anti-welding by first
Layer 70 is formed at the surface of the first substrate of glass 20 and the surface of the 3rd conductive circuit layer of part 44, and chip 80 is directly electrically connected to
3rd conductive circuit layer 44；Certainly, the conductive circuit layer 62 of the second dielectric layer 60 and the 6th can also be omitted, and second is prevented
Layer 72 is formed at the surface of the second substrate of glass 22 and the surface of the 4th conductive circuit layer of part 46.It is also understood that
Can be after and the 6th conductive circuit layer 62 and the second welding resisting layer 72 between five conductive circuit layers 52 and the first welding resisting layer 70
Continuous increasing layer, to form the chip package base plate with more layers conductive circuit layer.
Relative to prior art, in the present embodiment, the first blind hole 24 is formed in the first substrate of glass 20 and in the second glass
When forming the second blind hole 26 in glass substrate 22, the substrate of glass 22 of the first substrate of glass 20 and second is by the institute of circuit board core plate 10
Support, so as to prevent the fragmentation of the first substrate of glass 20 and the second substrate of glass 22 in processing, makes chip package base plate 100
Making becomes easy, and improves the making yield of chip package base plate 100.In addition, superfine wire can be made in substrate of glass
Road and circuit spacing can also be made very thin, therefore can reduce the layer of the conductive circuit layer of whole chip package base plate 100
Number causes that the substrate of glass 22 of the first substrate of glass 20 and second can be electrically connected to reduce the thickness of chip package base plate 100
Semiconductor package part with high-density spot, so that the applicability of chip package base plate 100 is wider.
It is understood that for the person of ordinary skill of the art, can be done with technology according to the present invention design
Go out other various corresponding changes and deformation, and all these changes and deformation should all belong to the protection model of the claims in the present invention
Enclose.
Claims (10)
1. a kind of preparation method of chip package base plate, including step：
Circuit board core plate is provided, the circuit board core plate includes multiple core plate units of array arrangement, it is multiple identical for being formed
The chip package base plate of structure, the core plate unit includes dielectric base and forms the first conductor wire of the dielectric base opposite sides
Road floor and the second conductive circuit layer, first conductive circuit layer include multiple first electric connection pads, second conductive circuit layer
Including multiple second electric connection pads；
The surface for being exposed to first conductive circuit layer in first conductive circuit layer and the dielectric base sets the first glue-line, and
First substrate of glass is embedded in first glue-line makes the surface of first substrate of glass with first glue-line away from the insulation
The surface flush of substrate；And
The 3rd conductive circuit layer is formed in first glass basic surface, and forms multiple through first substrate of glass and first
First guide hole of glue-line, the one end in the plurality of first guide hole is electrically connected to the 3rd conductive circuit layer, the relative other end
It is electrically connected in the plurality of first electric connection pad, so as to form chip package base plate.
2. the preparation method of chip package base plate as claimed in claim 1, it is characterised in that the 3rd conductive circuit layer and
The preparation method in one guide hole includes step：
Form in first substrate of glass multiple through first substrate of glass and the first glue-line by laser pit technique
First blind hole, the plurality of first blind hole exposes the plurality of first electric connection pad respectively；
Inwall, the surface of the plurality of first electric connection pad and first glass basic surface in the plurality of first blind hole are formed
Continuous Seed Layer；
The photoresist layer of patterning, photoresist layer exposure the plurality of first are formed in first glass basic surface
Blind hole；
Copper electroplating layer is formed on the surface for being exposed to the Seed Layer of the photoresist layer by electric plating method；And
Remove the photoresist layer, and remove the part that the Seed Layer is covered by the photoresist layer, remain in this
The Seed Layer and copper electroplating layer of one glass basic surface constitute the 3rd conductive circuit layer, the Seed Layer in the plurality of first blind hole
The plurality of first guide hole is constituted with copper electroplating layer.
3. the preparation method of chip package base plate as claimed in claim 1, it is characterised in that the 3rd conductive circuit layer and
The preparation method in one guide hole includes step：
Form in first substrate of glass multiple through first substrate of glass and the first glue-line by laser pit technique
First blind hole, the plurality of first blind hole exposes the plurality of first electric connection pad respectively；
Conductive paste is filled in the plurality of first blind hole；
Continuous Seed Layer is formed in first glass basic surface；
The photoresist layer of patterning, the Seed Layer relative with the plurality of first blind hole are formed in first glass basic surface
Exposed to the photoresist layer；
Copper electroplating layer is formed on the surface for being exposed to the Seed Layer of the photoresist layer by electric plating method；And
Remove the photoresist layer, and remove the part that the Seed Layer is covered by the photoresist layer, remain in this
The Seed Layer and copper electroplating layer of one glass basic surface constitute the 3rd conductive circuit layer, conductive paste structure in the plurality of first blind hole
Into the plurality of first guide hole.
4. the preparation method of chip package base plate as claimed in claim 1, it is characterised in that forming the 3rd conductive circuit layer
Behind the first guide hole, step is further included：
Stack gradually to form the first dielectric layer and the 5th conductive circuit layer in the 3rd conductive circuit layer side；And
The 5th conductive circuit layer side formed the first welding resisting layer, the conductive circuit layer of the first welding resisting layer covering part the 5th,
The 5th conductive circuit layer for being exposed to first welding resisting layer constitutes the 5th electric connection pad, and the 5th electric connection pad is used for and treats
Encapsulation chip electrical connection.
5. the preparation method of chip package base plate as claimed in claim 1, it is characterised in that first substrate of glass is protruded from
In the surface of first glue-line or embedded first glue-line.
6. the preparation method of chip package base plate as claimed in claim 1, it is characterised in that the making of the chip package base plate
Method further includes step：
On the surface that the second conducting wire layer surface and the dielectric base are exposed to second conductive circuit layer, the second glue is set
Layer, and the second substrate of glass is adhered on second glue-line；And
The 4th conductive circuit layer is formed in second glass basic surface, and forms multiple through second substrate of glass and second
Second guide hole of glue-line, the one end in the plurality of second guide hole is electrically connected to the 4th conductive circuit layer, the relative other end
It is electrically connected in the plurality of second electric connection pad.
7. the preparation method of chip package base plate as claimed in claim 6, it is characterised in that the making of the chip package base plate
Method further includes step：
Stack gradually to form the second dielectric layer and the 6th conductive circuit layer in the 4th conductive circuit layer side；And
The 6th conductive circuit layer side formed the second welding resisting layer, the conductive circuit layer of the second welding resisting layer covering part the 6th,
The 6th conductive circuit layer for being exposed to second welding resisting layer constitutes the 6th electric connection pad, and the 6th electric connection pad is used for and it
Its package substrate or circuit board are electrically connected.
8. a kind of chip package base plate, including：
Circuit board core plate, the circuit board core plate includes multiple core plate units of array arrangement, for forming multiple identical structures
Chip package base plate, the core plate unit includes dielectric base and forms the first conductive circuit layer of the dielectric base opposite sides
With the second conductive circuit layer, first conductive circuit layer includes multiple first electric connection pads, and second conductive circuit layer includes
Multiple second electric connection pads；
First glue-line, the first substrate of glass and the 3rd conductive circuit layer, first glue-line are formed at the first conductive circuit layer table
Face and the dielectric base are exposed on the surface of first conductive circuit layer, and first substrate of glass is embedded in first glue-line
And the surface of first substrate of glass deviates from the surface flush of the dielectric base, the 3rd conductive circuit layer with first glue-line
It is formed at first glass basic surface；And through first substrate of glass and multiple first guide holes of first glue-line,
3rd conductive circuit layer is electrically connected by multiple first guide holes with the plurality of first electric connection pad.
9. chip package base plate as claimed in claim 8, it is characterised in that the chip package base plate further includes the second glue
Piece, the second substrate of glass and the 4th conductive circuit layer, second glue-line are formed at the second conducting wire layer surface and the insulation
Substrate is exposed on the surface of second conductive circuit layer, and second substrate of glass is adhered on second glue-line, and the 4th leads
Electric line layer is formed at second glass basic surface, and by being formed at multiple the of second substrate of glass and the second glue-line
Two guide holes are electrically connected with the plurality of second electric connection pad.
10. chip package base plate as claimed in claim 8, it is characterised in that the chip package base plate is further included successively
The first dielectric layer in the 3rd conductive circuit layer side, the 5th conductive circuit layer and the first welding resisting layer are stacked, and successively
The second dielectric layer in the 4th conductive circuit layer side, the 6th conductive circuit layer and the second welding resisting layer are stacked, the 5th leads
Electric line layer is formed on first dielectric layer, the conductive circuit layer of the first welding resisting layer covering part the 5th, be exposed to this
5th conductive circuit layer of one welding resisting layer constitutes the 5th electric connection pad, and the 6th conductive circuit layer is formed at second dielectric layer
On, the conductive circuit layer of the second welding resisting layer covering part the 6th is exposed to the 6th conductive circuit layer structure of second welding resisting layer
Into the 6th electric connection pad.
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| CN201310137349.5A CN104112673B (en) | 2013-04-19 | 2013-04-19 | Chip package base plate and preparation method thereof |
| TW102114782A TWI503941B (en) | 2013-04-19 | 2013-04-25 | Chip package substrate and method for manufacturing same |
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| CN107305849B (en) * | 2016-04-22 | 2020-05-19 | 碁鼎科技秦皇岛有限公司 | Packaging structure and manufacturing method thereof |
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| CN101542719A (en) * | 2007-03-30 | 2009-09-23 | 住友电木株式会社 | Connection structure for flip-chip semiconductor package, buildup layer material, sealing resin composition and circuit board |
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| JP2002176258A (en) * | 2000-12-08 | 2002-06-21 | Toshiba Chem Corp | Method of manufacturing printed wiring board |
| TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
| JP4342174B2 (en) * | 2002-12-27 | 2009-10-14 | 新光電気工業株式会社 | Electronic device and manufacturing method thereof |
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| JP5095113B2 (en) * | 2005-03-25 | 2012-12-12 | 富士フイルム株式会社 | Solid-state imaging device manufacturing method and solid-state imaging device |
| CN100555619C (en) * | 2007-04-11 | 2009-10-28 | 全懋精密科技股份有限公司 | Substrate surface processing structure and preparation method thereof |
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| TW201442181A (en) | 2014-11-01 |
| CN104112673A (en) | 2014-10-22 |
| TWI503941B (en) | 2015-10-11 |
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