TWI581325B - 晶片封裝體及其製造方法 - Google Patents
晶片封裝體及其製造方法 Download PDFInfo
- Publication number
- TWI581325B TWI581325B TW104123721A TW104123721A TWI581325B TW I581325 B TWI581325 B TW I581325B TW 104123721 A TW104123721 A TW 104123721A TW 104123721 A TW104123721 A TW 104123721A TW I581325 B TWI581325 B TW I581325B
- Authority
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- Taiwan
- Prior art keywords
- chip package
- pad
- wafer
- blocking member
- insulating layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 230000000903 blocking effect Effects 0.000 claims description 56
- 230000004888 barrier function Effects 0.000 claims description 28
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000003822 epoxy resin Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229920000647 polyepoxide Polymers 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 48
- 238000000034 method Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Description
本發明是有關一種晶片封裝體及其製造方法。
指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor)需利用平坦的感測面來偵測訊號。若感測面不平整,會影響感測裝置偵測時的準確度。舉例來說,當指頭按壓於指紋感測裝置的感測面時,若感測面不平整,將難以偵測到完整的指紋。
此外,上述的感測裝置在製作時,會先於晶圓中形成矽穿孔(Through Silicon Via;TSV),使焊墊從矽穿孔裸露。接著,會以化學氣相沉積法(Chemical Vapor Deposition;CVD)在焊墊上與矽穿孔的壁面上形成絕緣層。之後,還需透過圖案化製程於焊墊上的絕緣層形成開口。一般而言圖案化製程包含曝光、顯影與蝕刻製程。在後續製程中,重佈線層便可形成在絕緣層上並電性連接絕緣層開口中的焊墊。
然而,化學氣相沉積與圖案化製程均需耗費大量的製程時間與機台的成本。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式,一種晶片封裝體包含晶片、雷射阻擋件、絕緣層、重佈線層、阻隔層與導電結構。晶片具有焊墊、及相對的第一表面與第二表面。焊墊位於第一表面上。第二表面具有第一穿孔,使焊墊從第一穿孔裸露。雷射阻擋件位於焊墊上。絕緣層位於第二表面上與第一穿孔中。絕緣層具有相對第二表面的第三表面。絕緣層與焊墊共同具有第二穿孔,使雷射阻擋件從第二穿孔裸露。重佈線層位於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。阻隔層位於第三表面上與重佈線層上。阻隔層具有開口,使重佈線層從開口裸露。導電結構位於開口中的重佈線層上,使導電結構電性連接焊墊。
本發明之一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式,一種晶片封裝體的製造方法包含下列步驟。(a)提供晶圓與雷射阻擋件,其中晶圓具有焊墊、及相對的第一表面與第二表面,且焊墊位於第一表面,雷射阻擋件位於焊墊上。(b)暫時接合支撐件於晶圓的第一表面。(c)在晶圓之第二表面中形成第一穿孔,使焊墊從第一穿孔裸露。(d)形成絕緣層於晶圓之第二表面上與第一穿孔中,其中絕緣層具有相對第二表面的第三表面。(e)使用雷射貫穿絕緣層與焊墊以形成第二穿孔,其中雷射由雷射阻擋件阻
擋,且雷射阻擋件從第二穿孔裸露。(f)電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。
在本發明上述實施方式中,由於雷射阻擋件位於焊墊上,因此當雷射貫穿絕緣層與焊墊時,雷射可由雷射阻擋件阻擋,並於絕緣層與焊墊中形成裸露雷射阻擋件的第二穿孔。待第二穿孔形成後,便可電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。其中,第二穿孔的壁面包含焊墊的表面與絕緣層的表面,使得重佈線層可電性連接焊墊。本發明之晶片封裝體及其製造方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程,能節省製程的時間與機台的成本。此外,晶片的第一表面未經額外的加工,因此平坦性佳,可提升晶片封裝體偵測時的準確度。
100‧‧‧晶片封裝體
110‧‧‧晶片
110a‧‧‧晶圓
111‧‧‧第一表面
112‧‧‧焊墊
113‧‧‧第二表面
114‧‧‧第一穿孔
115‧‧‧表面
120‧‧‧雷射阻擋件
122‧‧‧凹面
140‧‧‧絕緣層
141‧‧‧第三表面
142‧‧‧表面
150‧‧‧第二穿孔
152‧‧‧壁面
160‧‧‧重佈線層
170‧‧‧阻隔層
172‧‧‧開口
180‧‧‧導電結構
190‧‧‧空穴
210‧‧‧支撐件
2-2‧‧‧線段
D1~D2‧‧‧孔徑
D3~D5‧‧‧厚度
L1‧‧‧線段
L2‧‧‧線段
S1~S6‧‧‧步驟
第1圖繪示根據本發明一實施方式之晶片封裝體的俯視圖。
第2圖繪示第1圖之晶片封裝體沿線段2-2的剖面圖。
第3圖繪示第2圖之晶片封裝體的局部放大圖。
第4圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。
第5圖繪示根據本發明一實施方式之晶圓與雷射阻擋件的剖面圖。
第6圖繪示第5圖之晶圓接合支撐件後的剖面圖。
第7圖繪示第6圖之晶圓形成第一穿孔後的剖面圖。
第8圖繪示第7圖之晶圓的第二表面上與第一穿孔中形成絕緣層後的剖面圖。
第9圖繪示第8圖之絕緣層與焊墊中形成第二穿孔後的剖面圖。
第10圖繪示第9圖之絕緣層的第三表面、第二穿孔的壁面與雷射阻擋件上形成重佈線層後的剖面圖。
第11圖繪示第10圖之絕緣層與重佈線層上形成阻隔層後的剖面圖。
第12圖繪示第11圖之重佈線層上形成導電結構後的剖面圖。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片封裝體100的俯視圖。第2圖繪示第1圖之晶片封裝體100沿線段2-2的剖面圖。同時參閱第1圖與第2圖,晶片封裝體100包含感測晶片110、雷射阻擋件120、絕緣層140、重佈線層
160(Redistribution Layer;RDL)、阻隔層170與導電結構180。晶片110具有焊墊112、及相對的第一表面111與第二表面113。第一表面111為感測面。焊墊112位於第一表面111上。第二表面113具有第一穿孔114,使焊墊112從第一穿孔114裸露。雷射阻擋件120位於焊墊112上。絕緣層140位於晶片110的第二表面113上與第一穿孔114中,且絕緣層140具有相對第二表面113的第三表面141。絕緣層140與焊墊112共同具有第二穿孔150,使雷射阻擋件120從第二穿孔150裸露。重佈線層160位於絕緣層140的第三表面141上、第二穿孔150的壁面上與第二穿孔150中的雷射阻擋件120上。阻隔層170位於絕緣層140的第三表面141上與重佈線層160上。阻隔層170具有開口172,使重佈線層160從阻隔層170的開口172裸露。導電結構180位於開口172中的重佈線層160上,使導電結構180藉由重佈線層160電性連接焊墊112。
在本實施方式中,晶片封裝體100可以為指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor),但並不用以限制本發明。晶片110的材質可以包含矽。雷射阻擋件120的材質可以包含金,例如為金球(gold ball)。重佈線層160的材質可以包含銅,可採用電鍍的方式形成。絕緣層140的材質可以包含環氧樹脂(epoxy)。
第3圖繪示第2圖之晶片封裝體100的局部放大圖。雷射阻擋件120具有朝向重佈線層160的凹面122。第二穿孔150可利用雷射貫穿絕緣層140與焊墊112而形成。藉由雷射的使用,第二穿孔150的孔徑D2可小於第一穿孔114的孔徑
D1,對於微小化設計有所助益。由於第二穿孔150由雷射形成,因此雷射阻擋件120具有朝向第二穿孔150的凹面122,且第二穿孔150的壁面152與雷射阻擋件120的凹面122均為粗糙面。第二穿孔150的壁面152包含焊墊112的表面115與絕緣層140的表面142。也就是說,壁面152為焊墊112與絕緣層140朝向第二穿孔150的表面。
由於雷射阻擋件120位於焊墊112上,因此當雷射貫穿絕緣層140與焊墊112時,雷射可由雷射阻擋件120阻擋,並於絕緣層140與焊墊112中形成裸露雷射阻擋件120的第二穿孔150。待第二穿孔150形成後,便可以化鍍加電鍍重佈線層160於絕緣層140的第三表面141上、第二穿孔150的壁面152上與第二穿孔150中的雷射阻擋件120上,使得重佈線層160可電性連接焊墊112。也就是說,重佈線層160可穿過焊墊112而延伸至雷射阻擋件120的凹面122,使得重佈線層160至少部分凸出於焊墊112,如第3圖所示。
此外,由於重佈線層160係以電鍍的方式形成,因此重佈線層160在絕緣層140之第三表面141上的厚度D3大於重佈線層160在第二穿孔150的壁面152上的厚度D4,且重佈線層160在第二穿孔150的壁面152上的厚度D4大於重佈線層160在雷射阻擋件120上的厚度D5。在本實施方式中,晶片封裝體100還具有空穴190,且空穴190位於阻隔層170與第二穿孔150中的重佈線層160之間。
在以下敘述中,將說明晶片封裝體100的製造方法。
第4圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。晶片封裝體的製造方法包含下列步驟。在步驟S1中,提供晶圓與雷射阻擋件,其中晶圓具有焊墊、及相對的第一表面與第二表面,且焊墊位於第一表面,雷射阻擋件位於焊墊上。接著在步驟S2中,暫時接合支撐件於晶圓的第一表面。之後在步驟S3中,在晶圓之第二表面中形成第一穿孔,使焊墊從第一穿孔裸露。接著在步驟S4中,形成絕緣層於晶圓之第二表面上與第一穿孔中,其中絕緣層具有相對第二表面的第三表面。之後在步驟S5中,使用雷射貫穿絕緣層與焊墊以形成第二穿孔,其中雷射由雷射阻擋件阻擋,且雷射阻擋件從第二穿孔裸露。最後在步驟S6中,電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。在以下敘述中,將說明上述步驟。
第5圖繪示根據本發明一實施方式之晶圓110a與雷射阻擋件120的剖面圖。晶圓110a意指切割後可形成複數個第2圖的晶片110的半導體基板。首先,可提供晶圓110a與雷射阻擋件120,其中晶圓110a具有焊墊112、及相對的第一表面111與第二表面113,且焊墊112位於第一表面111,雷射阻擋件120位於焊墊112上。在本實施方式中,可透過打一導線(例如金線)於晶圓110a之焊墊112上,接著切除部分導線,使晶圓110a之焊墊112上殘留另一部分導線而形成雷射阻擋件120。雷射阻擋件120例如為金球。
第6圖繪示第5圖之晶圓110a接合支撐件210後的剖面圖。同時參閱第5圖與第6圖,待第5圖的結構形成後,可
暫時接合支撐件210於晶圓110a的第一表面111。支撐件210可提供晶圓110a支撐力,防止晶圓110a在後續製程中因受力而破裂。待接合支撐件210於晶圓110a後,可研磨晶圓110a之第二表面113,以減薄晶圓110a的厚度。
第7圖繪示第6圖之晶圓110a形成第一穿孔114後的剖面圖。同時參閱第6圖與第7圖,接著,可在晶圓110a之第二表面113中形成第一穿孔114,使焊墊112從第一穿孔114裸露。在此步驟中,可採用蝕刻製程在晶圓110a中形成第一穿孔114,例如乾蝕刻製程。
第8圖繪示第7圖之晶圓110a的第二表面113上與第一穿孔114中形成絕緣層140後的剖面圖。同時參閱第7圖與第8圖,待第一穿孔114形成後,便可形成絕緣層140於晶圓110a之第二表面113上與第一穿孔114中,其中絕緣層140具有相對第二表面113的第三表面141。在此步驟中,絕緣層140可採用印刷的方式形成於晶圓110a之第二表面113上與第一穿孔114中。接著,設計者可依需求塗佈、壓印、製模或研磨絕緣層140之第三表面141,以減薄絕緣層140的厚度。
第9圖繪示第8圖之絕緣層140與焊墊112中形成第二穿孔150後的剖面圖。同時參閱第8圖與第9圖,待第8圖的結構形成後,可使用雷射貫穿絕緣層140與焊墊112以形成第二穿孔150。雷射可由焊墊112上的雷射阻擋件120阻擋,使雷射阻擋件120從第二穿孔150裸露。此外,雷射係對準第一穿孔114與雷射阻擋件120發射,因此第二穿孔150可由第一穿孔114環繞。
第10圖繪示第9圖之絕緣層140的第三表面141、第二穿孔150的壁面與雷射阻擋件120上形成重佈線層160後的剖面圖。同時參閱第9圖與第10圖,待第二穿孔150形成於絕緣層140與焊墊112中後,可電鍍重佈線層160於絕緣層140的第三表面141上、第二穿孔150的壁面上與第二穿孔150中的雷射阻擋件120上。
第11圖繪示第10圖之絕緣層140與重佈線層160上形成阻隔層170後的剖面圖。同時參閱第10圖與第11圖,待第10圖的結構形成後,可形成阻隔層170於絕緣層140的第三表面141上與重佈線層160上。接著,可圖案化阻隔層170以形成開口172,使部分的重佈線層160可從阻隔層170的開口172裸露。
第12圖繪示第11圖之重佈線層160上形成導電結構180後的剖面圖。同時參閱第11圖與第12圖,待阻隔層170的開口172形成後,可形成導電結構180於開口172中的重佈線層160上,使得導電結構180可透過重佈線層160電性連接焊墊112。在此步驟後,便可移除晶圓110a的第一表面111上的支撐件210。
最後,可沿線段L1、L2切割晶圓110a、絕緣層140與阻隔層170,以形成第2圖之晶片封裝體100。
本發明之晶片封裝體及其製造方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程,能節省製程的時間與機台的成本。此外,晶片的第一表面未經額外的加工,因此平坦性佳,可提升晶片封裝體偵測時的準確度。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片封裝體
110‧‧‧晶片
111‧‧‧第一表面
112‧‧‧焊墊
113‧‧‧第二表面
114‧‧‧第一穿孔
120‧‧‧雷射阻擋件
140‧‧‧絕緣層
141‧‧‧第三表面
150‧‧‧第二穿孔
160‧‧‧重佈線層
170‧‧‧阻隔層
172‧‧‧開口
180‧‧‧導電結構
190‧‧‧空穴
Claims (18)
- 一種晶片封裝體,包含:一晶片,具有一焊墊、及相對的一第一表面與一第二表面,其中該焊墊位於該第一表面上,該第二表面具有一第一穿孔,使該焊墊從該第一穿孔裸露;一雷射阻擋件,位於該焊墊上;一絕緣層,位於該第二表面上與該第一穿孔中,該絕緣層具有相對該第二表面的一第三表面,該絕緣層與該焊墊共同具有一第二穿孔,使該雷射阻擋件從該第二穿孔裸露;該雷射阻擋件具有朝向該第二穿孔的一凹面;一重佈線層,位於該第三表面上、該第二穿孔的一壁面上與該第二穿孔中的該雷射阻擋件上,其中該重佈線層穿過該焊墊而延伸至該雷射阻擋件的該凹面,使得該重佈線層至少部分凸出於該焊墊;一阻隔層,位於該第三表面上與該重佈線層上,該阻隔層具有一開口,使該重佈線層從該開口裸露;以及一導電結構,位於該開口中的該重佈線層上,使該導電結構電性連接該焊墊。
- 如請求項1所述之晶片封裝體,其中該雷射阻擋件的材質包含金。
- 如請求項1所述之晶片封裝體,其中該第二穿孔的孔徑小於該第一穿孔的孔徑。
- 如請求項1所述之晶片封裝體,具有一空穴,且該空穴位於該阻隔層與該第二穿孔中的該重佈線層之間。
- 如請求項1所述之晶片封裝體,其中該第二穿孔的該壁面為一粗糙面。
- 如請求項1所述之晶片封裝體,其中該雷射阻擋件的該凹面為一粗糙面。
- 如請求項1所述之晶片封裝體,其中該重佈線層在該絕緣層之該第三表面上的厚度大於該重佈線層在該第二穿孔的該壁面上的厚度。
- 如請求項1所述之晶片封裝體,其中該重佈線層在該第二穿孔的該壁面上的厚度大於該重佈線層在該雷射阻擋件上的厚度。
- 如請求項1所述之晶片封裝體,其中該絕緣層的材質包含環氧樹脂。
- 一種晶片封裝體的製造方法,包含:(a)提供一晶圓與一雷射阻擋件,其中該晶圓具有一焊墊、及相對的一第一表面與一第二表面,該焊墊位於該第一表面,該雷射阻擋件位於該焊墊上;(b)暫時接合一支撐件於該晶圓的該第一表面; (c)在該晶圓之該第二表面中形成一第一穿孔,使該焊墊從該第一穿孔裸露;(d)形成一絕緣層於該晶圓之該第二表面上與該第一穿孔中,其中該絕緣層具有相對該第二表面的一第三表面;(e)使用一雷射貫穿該絕緣層與該焊墊以形成一第二穿孔,其中該雷射由該雷射阻擋件阻擋,且該雷射阻擋件從該第二穿孔裸露,該雷射阻擋件具有朝向該第二穿孔的一凹面;以及(f)電鍍一重佈線層於該絕緣層的該第三表面上、該第二穿孔的一壁面上與該第二穿孔中的該雷射阻擋件上,其中該重佈線層穿過該焊墊而延伸至該雷射阻擋件的該凹面,使得該重佈線層至少部分凸出於該焊墊。
- 如請求項10所述之晶片封裝體的製造方法,更包含:形成一阻隔層於該絕緣層的該第三表面上與該重佈線層上;以及圖案化該阻隔層以形成一開口,使該重佈線層從該開口裸露。
- 如請求項11所述之晶片封裝體的製造方法,更包含:形成一導電結構於該開口中的該重佈線層上。
- 如請求項11所述之晶片封裝體的製造方法,更包含:切割該晶圓、該絕緣層與該阻隔層,以形成該晶片封裝體。
- 如請求項10所述之晶片封裝體的製造方法,更包含:打一導線於該晶圓之該焊墊上;以及切除部分該導線,使該晶圓之該焊墊上殘留另一部分該導線而形成該雷射阻擋件。
- 如請求項10所述之晶片封裝體的製造方法,更包含:研磨該晶圓之該第二表面。
- 如請求項10所述之晶片封裝體的製造方法,其中該步驟(d)包含:印刷該絕緣層於該晶圓之該第二表面上與該第一穿孔中。
- 如請求項10所述之晶片封裝體的製造方法,更包含:塗佈、壓印、製模或研磨該絕緣層之該第三表面。
- 如請求項10所述之晶片封裝體的製造方法,更包含:移除該晶圓的該第一表面上的該支撐件。
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