TWI545882B - Two chips integrtated bridge rectifier - Google Patents

Description

Two-chip integrated bridge rectifier

This invention relates to a bridge rectifier, and more particularly to a bridge rectifier integrated into two wafers.

A conventional bridge rectifier is formed by coupling four PN diode chips in the manner shown in FIG. 1 for performing an operation of converting alternating current into direct current.

Referring to FIG. 1, when the input (In) terminal is given positive alternating current, the current passes through the diode 16 to the output terminal, the signal is positive, and the output ends through the diodes 12 and 14 are returned through the diode 14. To the input ground; when the input terminal is given negative AC power, the current flows through the diode 18 to the output terminal, the output signal is also positive, and the output terminal between the diodes 12 and 14 is returned to the diode 12 through the diode 12 Input.

As described above, bridge rectification is a function of converting a positive voltage into a positive sinusoidal (sin wave) mode voltage when an alternating current signal is applied to a negative voltage.

However, the prior art bridge rectifier contains four PN diode chips, so the circuit design is quite complicated.

The present invention provides a two-wafer integrated bridge rectifier in which two of the four diodes are integrated into one symmetrical PIN diode in one wafer, and the other two diodes are integrated into the control circuit. The CMOS process is obtained by coexisting with the control circuit in another wafer.

The equivalent circuit of the two-chip integrated bridge rectifier of the present invention includes first to fourth diodes, wherein the anode of the first diode and the anode of the second diode are coupled to the output ground, the first two poles The cathode of the body and the anode of the third diode are coupled to the input end, the cathode of the second diode and the anode of the fourth diode are coupled to the input ground, and the cathode of the third diode and the fourth The cathode of the diode is coupled to the output. The bridge rectifier includes: a symmetric PIN diode (P-intrinsic-N diode) integrated with the third and fourth diodes, and is located in the first wafer, wherein the structure belonging to the portion of the third diode Symmetrical with the structure of the portion belonging to the fourth diode; and an equivalent component of the first diode and the second diode, the equivalent component being integrated into a complementary metal oxide semiconductor (CMOS) process of a control circuit And coexisting with the control circuit in the second wafer.

In one embodiment, the symmetric PIN diode includes: a common cathode of the third diode and the fourth diode, at least one N-doped layer electrically connected to the common cathode, and a third An anode of each of the pole body and the fourth diode, two P-doped layers electrically connected to the two anodes, and an intrinsic layer between each of the P-doped layer and the N-doped layer. In one example, the N-doped layer includes a heavily doped N substrate disposed on the common cathode, the intrinsic layer including an N-type lightly doped layer and disposed on the heavily doped N substrate, And the two P doped layers comprise Two P wells in the N-type lightly doped layer. The symmetrical PIN diode may further comprise two or more guard rings located in the N-type lightly doped layer, each surrounding one of the two P wells.

In one embodiment, the equivalent element comprises a symmetrical structure in which the structure of the portion belonging to the first diode is symmetrical with the structure of the portion belonging to the second diode. The symmetrical structure has a common anode of a first diode and a second diode, a P-doped layer electrically connected to the common anode, a cathode of each of the first diode and the second diode, and Two N-doped layers electrically connected to the two cathodes and electrically connected to the P-doped layer.

In one embodiment, the symmetrical structure further includes two gates electrically connected to the common anode and belonging to the first diode and the second diode, respectively, to form a symmetrical metal oxide half structure. The symmetrical metal oxide half structure may comprise a symmetric laterally diffused gold oxide half (LDMOS) structure comprising: a P substrate; a P well as the P doped layer, located in the P substrate; The first N wells are located in the P base on both sides of the P well, belonging to the first diode and the second diode respectively, and the doping concentration is lower than the P well; the two field oxide layers are respectively located The two first N wells; the two gates are respectively located in one of the two field oxide layers, one of the two first N wells and the P well; Two second N wells of the two N-doped layers are respectively located outside the two first N wells, and belong to the first diode and the second diode respectively, and the doping concentration is higher than The two first N wells; the common anode is electrically connected to the P well and the two gates; and the cathodes of the first diode and the second diode.

In another embodiment, the symmetrical structure does not include the gate conductive layer formed in the complementary MOS process. The symmetrical structure may include: a P substrate; a P well as the P doped layer, located in the P substrate; and two first N wells located in the P substrate on both sides of the P well, respectively a first diode and a second diode, and a doping concentration lower than the P well; two field oxide layers respectively located on the two first N wells; and two as the two N doping layers a second N well, respectively located outside the two first N wells, belonging to the first diode and the second diode, respectively, and having a higher doping concentration than the two first N wells; a common anode electrically connected to the P well; and a cathode of each of the first diode and the second diode.

Since the present invention integrates two of the four diodes of the bridge rectification into one symmetrical PIN diode and integrates the other two into the CMOS process of the control circuit, the bridge can be formed by using only two wafers. Rectifiers simplify circuit design.

The above described features and advantages of the invention will be apparent from the following description.

12‧‧‧First Diode

14‧‧‧Secondary diode

16‧‧‧ Third Dipole

18‧‧‧ fourth diode

19‧‧‧Control circuit

20‧‧‧Symmetric PIN diode

22‧‧‧First chip

24‧‧‧second chip

300‧‧‧Concentrated doped N substrate

302‧‧‧N type doped layer

304‧‧‧P well

306‧‧‧ guard ring

308‧‧‧P type concentrated doping contact area

310‧‧‧Dielectric layer

312‧‧‧Anode

314‧‧‧Common cathode

400‧‧‧P base

402‧‧‧N type buried area

404‧‧‧First N Well

406‧‧ ‧ field oxide layer

408‧‧‧Second N well

410‧‧‧P well

412‧‧‧N type concentrated doping contact area

414‧‧‧P type concentrated doping contact area

416‧‧‧ gate

418‧‧‧ dielectric layer

420‧‧‧ cathode

422‧‧‧Common anode

1 is a circuit diagram of a conventional bridge rectifier.

2 is a schematic diagram of a two-wafer integrated bridge rectifier in accordance with an embodiment of the present invention.

3 is a cross-sectional view showing an example of a symmetrical PIN diode in which a third diode and a fourth diode are integrated in a two-wafer integrated bridge rectifier according to an embodiment of the present invention.

4 is a two-wafer integrated bridge rectifier according to an embodiment of the present invention, which is integrated into the control A cross-sectional view of an equivalent component of the first and second diodes of the CMOS process of the circuit.

5 is a cross-sectional view showing an equivalent element of a first and a second diode of a CMOS process integrated into a control circuit in a two-wafer integrated bridge rectifier according to another embodiment of the present invention.

2 is a schematic diagram of a two-wafer integrated bridge rectifier in accordance with an embodiment of the present invention.

Referring to FIG. 2, the equivalent circuit of the two-wafer integrated bridge rectifier of the present embodiment includes first to fourth diodes 12, 14, 16, and 18, wherein the anode and the second diode of the first diode 12 are The anode of the body 14 is coupled to the output ground, the cathode of the first diode 12 and the anode of the third diode 16 are coupled to the input end, and the cathode of the second diode 14 and the cathode of the second diode 18 The anode is coupled to the input ground, and the cathode of the third diode 16 and the cathode of the fourth diode 18 are coupled to the output. The bridge rectifier includes a symmetrical PIN diode 20 in which the third diode 16 and the fourth diode 18 are integrated, and an equivalent component of the first diode 12 and the second diode 14. The symmetrical PIN diode 20 is located in the first wafer 22, wherein the structure of the portion belonging to the third diode 16 is symmetrical with the structure of the portion belonging to the fourth diode 18, as shown in FIG. The above equivalent elements are integrated into a CMOS process of a control circuit 19, and coexist in the second wafer 24 with the control circuit.

3 is a diagram showing an example of a symmetrical PIN diode 20 in which a third diode 16 and a fourth diode 18 are integrated in a two-wafer integrated bridge rectifier according to an embodiment of the present invention. Sectional view.

Referring to FIG. 3, the symmetric PIN diode 20 includes a common cathode 314, a heavily doped N substrate 300, an N-type lightly doped layer 302 as an intrinsic layer, two P wells 304, and a P-type of each P well 304. The doped contact region 308, the dielectric layer 310, and the anode 312 electrically connected to the two contact regions 308. In this symmetric PIN diode 20, the structure of the portion belonging to the third diode 16 is symmetrical with the structure of the portion belonging to the fourth diode 18.

The heavily doped N substrate 300 is disposed on the common cathode 314, which is, for example, a germanium substrate. The N-type lightly doped layer 302 is disposed on the heavily doped N substrate 300, such as an N lightly doped epitaxial layer, which has a low dopant concentration. Two P wells 304 are located in the N-type doped layer 302 and belong to the third diode 16 and the fourth diode 18, respectively. Dielectric layer 310 covers N-type lightly doped layer 302 and P well 304. The two anodes 312 are electrically connected to the two P wells 304 via the two contact regions 308, respectively, and serve as anodes of the third diode 16 and anodes of the fourth diode 18, respectively. The symmetrical PIN diode 20 can further include two P-type guard rings 306 each surrounding one of the two P-wells 304 for evenly distributing the applied high voltage.

It should be particularly noted that the symmetric PIN diode 20 described above is only one example of a symmetric PIN diode that can be used in the present invention, and other common cathodes having a third diode and a fourth diode. At least one N-doped layer connected to the common cathode, an anode of each of the third diode and the fourth diode, two P-doped layers respectively connected to the two anodes, and each of the P-doped layers A PIN diode of the intrinsic layer between the N-doped layers can also be used.

4 is a cross-sectional view showing an equivalent element of a first diode 12 and a second diode 14 of a CMOS process integrated into a control circuit in a two-wafer integrated bridge rectifier according to an embodiment of the present invention.

Referring to FIG. 4, the equivalent element has a symmetrical metal oxide half structure in which the structure of the portion belonging to the first diode 12 is symmetrical with the structure of the portion belonging to the second diode 14. The control circuit integrated into the same CMOS process also has a gold oxide half structure of the same material. The symmetrical gold-oxygen half structure is, for example, a symmetric LDMOS structure, belonging to a high voltage component, comprising: a P substrate 400, two N-type buried regions 402, two first N wells 404, and two field oxide layers 406. Two second N wells 408, a P well 410, a second N well 408, an N-type heavily doped contact region 412, a P-well 410 P-type heavily doped contact region 414, two gates 416, a dielectric layer 418, two cathodes 420 and a common anode 422. The symmetrical LDMOS structure and the CMOS components integrated into the control circuit of the same CMOS process are, for example, 700V high voltage components having a line width of 1 micron.

In the above structure, the P well 410 is located in the P substrate 400 at the center of the above structure. The two first N wells 404 are respectively located in the P substrate 400 on both sides of the P well 410, below the two field oxide layers 406, belonging to the first diode 12 and the second diode 14, respectively. The doping concentration is lower than that of the P well 410 and serves as a withstand voltage region of the high voltage component. The two gates 416 are each located on one of the two field oxide layers 406, one of the two first N wells 404, and the P well 410. The two second N wells 408 are respectively located in the P substrate 400 outside the two first N wells 404, which belong to the first diode 12 and the second diode 14, respectively, and have a higher doping concentration. First N well 404. The two N-type buried regions 402 are each located adjacent to a pair of first N wells 404 and second In the P substrate 400 below the N well 408. The N-type heavily doped contact region 412 of the second N well 408 is N-type heavily doped, and the P-type heavily doped contact region 414 of the P-well 410 is P-type heavily doped. Dielectric layer 418 covers the various portions described above. The two cathodes 420 each pass through a dielectric layer 418 to connect the N-type heavily doped contact regions 412 of one of the two second N-wells 408. The common anode 422 passes through the dielectric layer 418 to connect with the P-type heavily doped contact region 414 of the P-well 410 and the gates 416.

5 is a cross-sectional view showing an equivalent element of a first diode 12 and a second diode 14 of a CMOS process integrated into a control circuit in a two-wafer integrated bridge rectifier according to another embodiment of the present invention.

Referring to FIG. 5, the difference between the equivalent component of the other embodiment and the previous embodiment (FIG. 4) is that there are two gates 416 and a contact window between the common anode 422 and each gate 416. That is to say, the equivalent element also has a symmetrical structure, but does not include the gate conductive layer formed in the CMOS process in which the control circuit, the first diode 12 and the second diode 14 are integrated.

It should be particularly noted that the above-described gate-symmetrical LDMOS structure and the gateless symmetrical structure are only two examples of equivalent components of the first second diode that can be used in the present invention, and other control circuits. CMOS process compatible with a common anode of the first two and second diodes, a P-doped layer connected to the common anode, a cathode of each of the first and second diodes, and respectively connected to the two cathodes And the structure of the two N-doped layers connected to the P-doped layer can also be used.

In summary, the present invention integrates two of the four diodes of the bridge rectification into one symmetrical PIN diode, and integrates the other two into the control circuit. CMOS process, so as long as two wafers can be used to form a bridge rectifier, which simplifies the circuit design. In addition, the equivalent elements of the two diodes of the CMOS process integrated into the control circuit may or may not include the gate conductive layer formed in the CMOS process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

12, 14, 16, 18‧ ‧ diodes

19‧‧‧Control circuit

20‧‧‧Symmetric PIN diode

22‧‧‧First chip

24‧‧‧second chip

Claims (10)

A two-chip integrated bridge rectifier, the equivalent circuit comprising first to fourth diodes, wherein an anode of the first diode and an anode of the second diode are coupled to an output ground, the first diode The cathode of the body is coupled to the anode of the third diode to an input end, the cathode of the second diode and the anode of the fourth diode are coupled to an input ground, and the cathode of the third diode The cathode of the fourth diode is coupled to an output terminal, and the bridge rectifier includes: a symmetric PIN diode integrated with the third diode and the fourth diode, located in the first chip, wherein The structure of the portion of the third diode is symmetrical with the structure of the portion belonging to the fourth diode; and an equivalent component of the first diode and the second diode, the equivalent component being integrated into a control circuit A complementary MOS process is coexisted with the control circuit in the second wafer. The two-chip integrated bridge rectifier according to claim 1, wherein the symmetric PIN diode comprises: a common cathode of the third diode and the fourth diode, and is electrically connected to the common cathode At least one N-doped layer, an anode of each of the third diode and the fourth diode, two P-doped layers electrically connected to the two anodes, and each of the P-doped layer and the N-doped layer The essential layer between layers. The two-wafer integrated bridge rectifier according to claim 2, wherein in the symmetric PIN diode, the N-doped layer comprises a concentrated doped N substrate disposed on the common cathode; The layer includes an N-type lightly doped layer disposed on the heavily doped N substrate; The two P-doped layers comprise two P-wells located in the N-type lightly doped layer. The two-chip integrated bridge rectifier according to claim 3, wherein the symmetric PIN diode further comprises: two or more guard rings located in the N-type doped layer, and each surrounding the two P One of the wells. The two-wafer integrated bridge rectifier according to claim 1, wherein the equivalent component comprises a symmetrical structure, wherein a structure of a portion belonging to the first diode is symmetric with a structure of a portion belonging to the second diode . The two-wafer integrated bridge rectifier according to claim 5, wherein the symmetrical structure has a common anode of the first diode and the second diode, and a P-doped layer electrically connected to the common anode, a cathode of each of the first diode and the second diode, and two N-doped layers electrically connected to the two cathodes and electrically connected to the P-doped layer. The two-chip integrated bridge rectifier according to claim 6, wherein the symmetrical structure further comprises two gates electrically connected to the common anode and belonging to the first diode and the second diode, respectively. It becomes a symmetrical gold-oxygen half structure. The two-wafer integrated bridge rectifier according to claim 7, wherein the symmetric gold-oxygen half structure comprises a symmetric laterally diffused gold-oxygen half structure, the symmetric laterally diffused gold-oxygen half structure comprising: a P a P-well as a P-doped layer, located in the P-substrate; and two first N-wells located in the P-base on both sides of the P-well, belonging to the first diode and the second diode Body, and the doping concentration is lower than the P well; a second field oxide layer, respectively located on the two first N wells; the two gates are respectively located in one of the two field oxide layers, one of the two first N wells and the P well; as the two N doped layers Two second N wells are respectively located outside the two first N wells, and belong to the first diode and the second diode respectively, and the doping concentration is higher than the two first N wells; the common anode, Electrically connecting with the P well and the second gate; and a cathode of each of the first diode and the second diode. The two-wafer integrated bridge rectifier of claim 6, wherein the symmetrical structure does not include the gate conductive layer formed in the complementary MOS process. The two-wafer integrated bridge rectifier according to claim 9, wherein the symmetrical structure comprises: a P substrate; a P well as the P doped layer, located in the P substrate; and two first N wells The P substrate on both sides of the P well belongs to the first diode and the second diode, respectively, and the doping concentration is lower than the P well; the two field oxide layers are respectively located in the first N The second N wells as the two N-doped layers are respectively located outside the two first N wells, and belong to the first diode and the second diode respectively, and the doping concentration is higher than the two a first N well; the common anode is electrically connected to the P well; a cathode of each of the first diode and the second diode; and two N-type buried regions respectively located in a pair of adjacent first N wells and second N wells and another pair of adjacent first N Well and under the second N well.