CN116113309B - A low-offset Hall device using double guard rings and its application method - Google Patents

Abstract

The invention discloses a low offset Hall device using double guard rings and a method for using the same. The low offset Hall device using double guard rings includes a lateral layer group, the lateral layer group includes a P-type substrate, an N+ buried layer arranged in the central region of the P-type substrate, and a P-buried layer arranged in the top central region of the N+ buried layer, an N-well active region is arranged above the P-buried layer, and the N+ buried layer and the P-buried layer form a lateral guard ring; side surrounding layer groups, the side surrounding layer group includes a P-type layer arranged outside the N-well active region An epitaxial layer, the P-type epitaxial layer is provided with a high-voltage N well connected to the top of the N+ buried layer, the P-type epitaxial layer is provided with a high-voltage P well connected to the top of the P-type substrate, the high-voltage P well is arranged outside the high-voltage N well, and the P-type epitaxial layer and the N+ buried layer form a longitudinal protection ring; the Hall device of the present invention has low imbalance, high sensitivity and strong anti-interference ability.

Description

A low-offset Hall device using double guard rings and its application method

technical field

The invention relates to the technical field of sensors, in particular to a low-offset Hall device using double guard rings and its application method.

Background technique

In recent years, the Hall sensor has become a mainstream magnetic sensor due to its advantages of low cost, low power consumption, and high integration. It can detect AC and DC magnetic fields and generate an output electrical signal proportional to the strength of the magnetic field. It is widely used in automotive control, battery chargers, brushless DC motors, power meters, and photovoltaic inverters. At present, the Hall sensor is developing towards the direction of high linearity, high precision and broadband, which puts forward higher requirements for the high sensitivity and low offset characteristics of the Hall device.

Silicon-based Hall devices have been the most widely researched and applied due to their low cost, high temperature stability, and good compatibility with standard CMOS processes. However, since the integrated CMOS Hall device uses an N-well with a high doping concentration as the active region, the impact of ionized impurity scattering on carrier movement is increased, and the mobility of the Hall device is reduced, resulting in a relatively low sensitivity of the Hall device. On the other hand, the uneven distribution of impurity concentration in the N-well under the CMOS process, the packaging stress, and the alignment error of the mask between the device contact hole and the N-well cause the output offset of the Hall device to be very large, and the offset voltage can reach several millivolts to tens of millivolts, drowning the weak Hall signal. In addition, traditional Hall devices usually only use P-well rings to isolate the active area, which cannot overcome the interference of high-frequency signals in the circuit and substrate noise, resulting in relatively poor anti-interference capabilities of Hall devices, making silicon-based Hall devices unable to meet the low magnetic field and high-resolution requirements. Therefore, how to reduce the offset of Hall devices and improve sensitivity and signal-to-noise ratio is a key technical problem that silicon-based Hall sensors need to solve urgently.

Contents of the invention

The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract of the specification and the title of the invention to avoid blurring the purpose of this section, the abstract of the specification and the title of the invention, and this simplification or omission cannot be used to limit the scope of the present invention.

In view of the problems mentioned above and/or in the prior art, the present invention is proposed.

Therefore, the technical problem to be solved by the present invention is the problems of large offset, low sensitivity, and poor anti-noise and interference ability of the Hall device under the existing CMOS technology.

In order to solve the above technical problems, the present invention provides the following technical solutions: a low offset Hall device using double guard rings, comprising,

A lateral layer group, the lateral layer group comprising a P-type substrate, an N+ buried layer arranged in the center region of the P-type substrate, and a P-buried layer arranged in the top center region of the N+ buried layer, an N well active region is arranged above the P-buried layer, and the N+ buried layer and the P-buried layer form a lateral guard ring;

The side surrounding layer group, the side surrounding layer group includes a P-type epitaxial layer arranged outside the N well active region, the P-type epitaxial layer is provided with a high-voltage N well connected to the top of the N+ buried layer, the P-type epitaxial layer is provided with a high-voltage P well connected to the top of the P-type substrate, the high-voltage P well is arranged outside the high-voltage N well, and the P-type epitaxial layer and the high-voltage N well form a longitudinal protection ring.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the side surrounding layer group has a symmetrical structure and is symmetrical with respect to the first axis of symmetry; the active region of the N-well is of a symmetrical structure and is symmetrical with respect to the second axis of symmetry, and the first axis of symmetry coincides with the second axis of symmetry.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the edge of the N-well active region is evenly distributed with first N+ regions, the first N+ region is symmetrical about the second symmetry axis, and the first N+ region is placed parallel to the edge of the N-well active region.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, metal is provided on each of the four first N+ regions to form four bias electrodes.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: a second N+ region is provided in the N-well active region at the center of the adjacent first N+ region, the second N+ region is symmetrical about the second symmetry axis, and the second N+ region is placed parallel to the edge of the N-well active region;

The size of the first N+ region is larger than that of the second N+ region.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the four second N+ regions are all provided with metal to form four output electrodes;

The two output electrodes at the opposite corners are short-circuited through metal wires.

As a preferred solution of the low offset Hall device using double guard rings in the present invention, wherein: the surface of the high-voltage N well is provided with a third N+ region, and metal is provided on the third N+ region to form a first contact electrode.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, wherein: the non-electrode part above the N-well active region is covered with a first P+ region;

A second P+ region is provided on the surface of the high-voltage P well, and metal is arranged on the second P+ region to form a second contact electrode.

As a preferred solution of the low-offset Hall device using double guard rings in the present invention, an isolation shallow trench is provided between the first N+ region and the third N+ region, between the first N+ region and the first P+ region, and between the third N+ region and the second P+ region.

The present invention also discloses a method of using the aforementioned low-offset Hall device using double guard rings:

Input current or voltage bias signals of equal magnitude and opposite directions to two opposite bias electrodes;

The other two opposite bias electrodes are grounded;

Output Hall current or Hall voltage signal between the output electrodes;

The first contact electrode is connected to high level; the second contact electrode is connected to ground.

Beneficial effects of the present invention: the Hall device of the present invention has low offset, high sensitivity and strong anti-interference ability.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without paying creative labor. in:

FIG. 1 is a schematic top view of a low-offset Hall device using double guard rings according to an embodiment of the present invention;

2 is a schematic diagram of the relative position of the N-well active region and the outer contour in the low-offset Hall device using double guard rings according to an embodiment of the present invention;

3 is a schematic cross-sectional structure diagram of a low-offset Hall device using double guard rings according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a double guard ring structure of a low offset Hall device using double guard rings according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a working bias structure of a low-offset Hall device using double guard rings according to an embodiment of the present invention;

FIG. 6 is a comparison diagram of output offset obtained by three-dimensional simulation between the present invention and the traditional cross-shaped Hall device structure.

Detailed ways

In order to make the above objects, features and advantages of the present invention more obvious and comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do similar promotion without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

Second, "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

Example 1

Referring to FIG. 1 and FIG. 3, it is a schematic top view and a schematic cross-sectional structure diagram of a low offset Hall device using double guard rings according to an embodiment of the present invention. This embodiment provides a low offset Hall device using double guard rings, including:

The lateral layer group 100, the lateral layer group 100 includes a P-type substrate 101, an N+ buried layer 102 arranged in the center region of the P-type substrate 101, and a P-buried layer 103 arranged in the top center region of the N+ buried layer 102, an N well active region 104 is arranged above the P-buried layer 103, and the N+ buried layer 102 and the P-buried layer 103 form a lateral guard ring;

The N+ buried layer 102 is above the center of the P-type substrate 101 , and the N+ buried layer 102 is partially embedded in the P-type substrate 101 .

Specifically, the P-type substrate 101 may be a semiconductor silicon material,

The side surrounding layer group 200, the side surrounding layer group 200 comprises the P type epitaxial layer 201 arranged on the outside of the N well active region 104, the high voltage N well 202 connected to the top of the N+ buried layer 102 is arranged in the P type epitaxial layer 201, the high voltage P well 203 connected to the top of the P type substrate 101 is arranged in the P type epitaxial layer 201, the high voltage P well 203 is arranged outside the high voltage N well 202, the P type epitaxial layer 201 and the high voltage N well 201 are arranged on the outside of the high voltage N well 202. Well 202 forms a longitudinal guard ring.

A P-type epitaxial layer 201 with a certain thickness is disposed between the high-voltage P-well 203 and the high-voltage N-well 202 .

It should be noted that the double guard rings proposed in the present invention are respectively a longitudinal guard ring and a transverse guard ring, as shown in FIG. 4 . The lateral guard ring is a PN junction formed between the N+ buried layer 102 and the P− buried layer 103 . The vertical guard ring is a PN junction formed between the high voltage N well 202 and the P-type epitaxial layer 201 .

Further, referring to FIG. 2 , the lateral surrounding layer group 200 has a symmetrical structure about the first axis of symmetry Y1; the N-well active region 104 has a symmetrical structure about the second axis of symmetry Y2, and the first axis of symmetry Y1 coincides with the second axis of symmetry Y2.

Specifically, referring to (a) of FIG. 2 , the square side surrounding layer group 200 is symmetrical about the first symmetry axis Y1, the corner-cut square N-well active region 104 is symmetrical about the second symmetry axis Y2, the first N+ region 104a is uniformly distributed on the edge of the N-well active region 104, and is symmetrical about the second symmetry axis Y2, and the second N+ region 104b is evenly distributed on the edge of the N-well active region 104, and is symmetric about the second symmetry axis Y2. The first N+ region 104a and the second N+ Region 104b is placed parallel to the edge of N-well active region 104 . The second N+ region 104b is distributed on the N-well active region 104 at the center of two adjacent first N+ regions.

Referring to (b) of FIG. 2 , the regular octagonal sidewall group 200 is symmetrical about the first symmetry axis Y1, and the corner-cut rhomboid N-well active region 104 is symmetrical about the second symmetry axis Y2. The first N+ region 104a is uniformly distributed on the edge of the N-well active region 104 and is symmetrical about the second symmetry axis Y2. The second N+ region 104b is evenly distributed on the edge of the N-well active region 104 and is symmetrical about the second symmetry axis Y2. The first N+ region 104a and the second N+ Region 104b is positioned parallel to the edge of N-well active region 104 . The second N+ region 104b is distributed on the N-well active region 104 at the center of two adjacent first N+ regions.

Referring to (c) of FIG. 2 , the square side surrounding layer group 200 is symmetrical about the first symmetry axis Y1, and the corner-cut diamond-shaped N-well active region 104 is symmetrical about the second symmetry axis Y2. The first N+ region 104a is evenly distributed on the edge of the N-well active region 104 and is symmetrical about the second symmetry axis Y2. The second N+ region 104b is evenly distributed on the edge of the N-well active region 104 and is symmetrical about the second symmetry axis Y2. The first N+ region 104a and the second N+ region 1 04b is placed parallel to the edge of the N-well active region 104 . The second N+ region 104b is distributed on the N-well active region 104 at the center of two adjacent first N+ regions.

Referring to (d) of FIG. 2 , the circular side surrounding layer group 200 is symmetrical about the first symmetry axis Y1, and the corner-cut diamond-shaped N-well active region 104 is symmetrical about the second symmetry axis Y2. The first N+ region 104a is evenly distributed on the edge of the N-well active region 104 and is symmetrical about the second symmetry axis Y2. The second N+ region 104b is evenly distributed on the edge of the N-well active region 104 and is symmetrical about the second symmetry axis Y2. The first N+ region 104a and the second N+ region 10 4b is placed parallel to the edge of the N-well active region 104 . The second N+ region 104b is distributed on the N-well active region 104 at the center of two adjacent first N+ regions.

The edge of the N-well active region 104 is evenly distributed with first N+ regions 104a, the first N+ regions 104a are symmetrical about the second symmetry axis Y2, and the first N+ regions 104a are placed parallel to the edge of the N-well active region 104 .

Metal is disposed on the four first N+ regions 104a to form four bias electrodes A, B, C and D.

A second N+ region 104b is arranged in the N well active region at the center of the adjacent first N+ region 104a, the second N+ region 104b is symmetrical about the second symmetry axis Y2, and the second N+ region 104b is placed parallel to the edge of the N well active region 104;

The size of the first N+ region 104a is larger than that of the second N+ region 104b.

Diagonally two first N+ regions 104a are at the same distance from the second N+ region 104b between them.

Metal is provided on the four second N+ regions 104b to form four output electrodes E, F, G and H;

The two opposite output electrodes E and H and F and G are short-circuited through metal wires.

A third N+ region 104c is disposed on the surface of the high voltage N well 202, and a metal is disposed on the third N+ region 104c to form a first contact electrode J.

The non-electrode portion above the N-well active region 104 is covered with a first P+ region 104d.

A second P+ region 203a is disposed on the surface of the high voltage P well 203, and metal is disposed on the second P+ region 203a to form a second contact electrode K.

Isolation shallow trenches 300 are provided between the first N+ region 104a and the third N+ region 104c, between the first N+ region 104a and the first P+ region 104d, between the third N+ region 104c and the second P+ region 203a.

Further, elaborating on the role of the hierarchy used,

The P-buried layer 103 can control the doping distribution, and form a more uniform PN junction with the N+ buried layer 102, that is, a lateral PN junction, which improves the impurity concentration distribution at the bottom of the N-well active region 104, thereby improving the symmetry of the Hall device and reducing output imbalance.

The built-in electric field formed by the lateral PN junction can reduce the current loss at the bottom of the N-well active region 104 and reduce external noise interference when the device is working.

A depletion layer is formed between the first P+ region 104d and the N well 104, so as to increase the current transport path, avoid the short circuit effect, and reduce the thickness of the N well to increase its current-related sensitivity. The first P+ region 104d can also form a PMOS transistor. Since the PMOS transistor is a "buried trench" device, it can effectively reduce device flicker noise and surface loss of current, and increase the Hall voltage.

A PN junction is formed between the high-voltage N-well 202 and the P-type epitaxial layer 201 , that is, the vertical guard ring effectively reduces lateral leakage current and 1/f noise.

The present invention uses the N+ buried layer 102 and the P- buried layer 103 to form a lateral PN junction as a guard ring, replacing the original PN junction between the P-type epitaxial layer and the N-well active region, effectively improving the impurity concentration distribution of the N-well active region 104, reducing the output imbalance of the Hall device due to the Gaussian distribution of the impurity concentration in the N-well active region 104, and forming a wider PN junction depletion layer, further improving the anti-interference ability of the Hall device, and reducing the bottom leakage current.

In the present invention, the high-voltage N well 202 is in contact with the N+ buried layer 102, and the first contact electrode J on the top of the high-voltage N well 202 is connected to a high level, so that the N+ buried layer 102 is connected to a high level, and the lateral PN junction between the N+ buried layer 102 and the P- buried layer 103 is reverse-biased, and the lateral PN junction depletion layer is further widened, so that the Hall device has stronger anti-interference ability and smaller imbalance. At the same time, this method reduces the effective depth of the N-well active region 104 and improves the sensitivity of the Hall device. The high-voltage N-well 202 can also form a vertical PN junction with the P-type epitaxial layer 201 to further reduce the lateral leakage current and noise of the Hall device and provide double protection for the Hall device.

Example 2

Referring to Figures 5 and 6, this embodiment also proposes the method of using the above-mentioned low-offset Hall device with double guard rings, which is:

Among the bias electrodes A, B, C, and D of the proposed Hall device, two opposite bias electrodes input current or voltage bias signals of equal magnitude and opposite direction, and the other two relative bias electrodes are grounded, for example, the bias electrodes B and D are grounded by inputting current or voltage bias signals of equal magnitude and opposite direction in bias electrodes A and C; the proposed Hall device outputs a Hall current or Hall voltage signal between two short-connected output electrodes E (or H) and F (or G); the proposed first contact electrode J is connected to a high level; The proposed second contact electrode K is grounded.

Furthermore, the substrate material of the proposed Hall device is not limited to silicon (Si) semiconductors, and various semiconductor materials such as silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC) and indium gallium arsenide (InGaAs) can also be used as substrates.

Further, the N-well active region 104 of the proposed Hall device can also be designed in octagonal, rhombus and circular structures.

The process steps for making the low offset Hall device structure proposed by the present invention are:

In step S1 , an N+ buried layer 102 is first formed on the central region of the P-type substrate 101 .

In step S2 , a P-type epitaxial layer 201 is grown on the P-type substrate 101 , and an isolation shallow trench 300 is formed on the top of the P-type epitaxial layer 201 .

In step S3 , a P-buried layer 103 is formed in the epitaxial layer above the N+ buried layer 102 , and the bottom of the P-buried layer 103 is connected to the top of the N+ buried layer 102 .

Step S4 , implanting the N-well active region 104 into the P-type epitaxial layer 201 on the P-buried layer 103 .

In step S5 , a high voltage N well 202 is formed in the P-type epitaxial layer 201 around the N well active region 104 , and the bottom of the high voltage N well is connected to the top of the N+ buried layer 102 .

Step S6 , forming a high voltage P well 203 in the P type epitaxial layer 201 around the high voltage N well 202 , and the bottom of the high voltage P well 203 is connected to the P type substrate 101 .

In step S7 , a first N+ region 104 a and a second N+ region 104 b are formed on the top of the N well active region 104 , and a third N+ region 104 c is formed on the surface of the high voltage N well 202 .

In step S8 , a first P+ region 104 d is formed on the surface of the N-well active region 104 , and a second P+ region 203 a is formed on the surface of the high-voltage P-well 203 .

In step S9, a contact hole is provided on the P-type epitaxial layer 201 to form a metal interconnection line.

Combined with the working bias diagram of the low offset Hall device in Figure 5, the proposed working method of the Hall device is further explained:

When the Hall bias electrodes A and C input current biases of equal magnitude and opposite polarity, and the other two bias electrodes B and D are connected to ground, and there is no external magnetic field, assuming that the overall concentration distribution of the N-well active region 104 is uniform, the current densities near the four output electrodes E, F, G, and H are the same, and ideally the output voltage is 0.

Furthermore, when a magnetic field perpendicular to the surface of the paper is applied inward, the carriers are deflected by the Lorentz force, and the four output electrodes are polarized at the same time. Due to the uneven distribution of impurities in the active region of the Hall device in practice, the current density near the four output electrodes is asymmetrical.

Further, in the present invention, the diagonal output electrodes E and H, F and G of the Hall device are short-circuited to force the current to be evenly distributed in the active area, reducing the offset caused by uneven resistivity, impurity concentration, or uneven process stress, realizing static elimination of offset signals, and reducing the parasitic capacitance of the front-end circuit without the need for spinning current technology.

Further, since the first contact electrode J is always connected to a high level and the second contact electrode K is always connected to the ground, the horizontal guard ring and the longitudinal guard ring can be reverse-biased, reducing leakage current and high-frequency signal interference in the circuit during operation, and enhancing the anti-interference capability of the Hall device.

Referring to FIG. 6 , it is a comparison simulation diagram of the output offset between the present invention and the traditional cross-shaped Hall device structure.

Specifically, for the device structure shown in Figure 1 and Figure 2, according to the process parameters of the high-voltage BCD process, the Silvaco TCAD simulation tool was used to simulate the device electrical characteristics of the low-offset Hall device structure, and the comparison of the output offset between the low-offset Hall device and the traditional four-contact Hall device in Figure 5 was obtained. It can be found that under the bias current of 0-5mA, the output offset of the low-offset Hall device is always below 1mV, while the output offset of the traditional cross-shaped Hall device reaches 4. 5mV or so, indicating that the low offset Hall device solution designed by the present invention is feasible.

It is important to note that the construction and arrangement of the application, shown in the various exemplary embodiments, are illustrative only. Although only a few embodiments have been described in detail in this disclosure, those who review this disclosure will readily appreciate that many modifications are possible (e.g., changes in the size, scale, structure, shape, and proportions of various elements, and parameter values (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientation, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be inverted or otherwise varied, and the nature or number or positions of discrete elements may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of this invention. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any "means-plus-function" clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operation and arrangement of the exemplary embodiments without departing from the scope of the invention. Accordingly, the invention is not limited to a particular embodiment, but extends to various modifications still falling within the scope of the appended claims.

Furthermore, in order to provide a concise description of exemplary embodiments, not all features of an actual embodiment (ie, those features not relevant to the best mode presently considered for carrying out the invention, or to practicing the invention) may not be described.

It should be appreciated that during the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort would be complex and time consuming, but would be a routine undertaking of design, fabrication, and production without undue experimentation to those of ordinary skill having the benefit of this disclosure.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the scope of the claims of the present invention.

Claims (10)

1. A low offset hall device employing a double guard ring, characterized by: comprising the steps of (a) a step of,

the device comprises a transverse layer group (100), wherein the transverse layer group (100) comprises a P-type substrate (101), an N+ buried layer (102) arranged in the central area of the P-type substrate (101) and a P-buried layer (103) arranged in the central area of the top of the N+ buried layer (102), an N well active region (104) is arranged above the P-buried layer (103), and the N+ buried layer (102) and the P-buried layer (103) form a transverse protection ring;

the side wall layer group (200), side wall layer group (200) is including setting up in P type epitaxial layer (201) in the N well active region (104) outside, be provided with in P type epitaxial layer (201) with N+ buried layer (102) top be connected high-pressure N well (202), be provided with in P type epitaxial layer (201) with P type substrate (101) top be connected high-pressure P well (203), high-pressure P well (203) set up in high-pressure N well (202) outside, P type epitaxial layer (201) and high-pressure N well (202) form vertical guard ring.

2. The low offset hall device employing a double guard ring as claimed in claim 1, wherein: the side wall layer group (200) is of a symmetrical structure and is symmetrical about a first symmetry axis (Y1); the N-well active region (104) is of a symmetrical structure and symmetrical about a second symmetry axis (Y2), and the first symmetry axis (Y1) and the second symmetry axis (Y2) are overlapped.

3. The low offset hall device employing a double guard ring as claimed in claim 1 or 2, wherein: the edges of the N well active region (104) are uniformly distributed with first N+ regions (104 a), the first N+ regions (104 a) are symmetrical about a second symmetry axis (Y2), and the first N+ regions (104 a) are placed parallel to the edges of the N well active region (104).

4. The low offset hall device employing a double guard ring as claimed in claim 3, wherein: metal is disposed on each of the four first n+ regions (104 a) to form four bias electrodes A, B, C and D.

5. The low offset hall device employing a double guard ring as claimed in claim 4, wherein: a second N+ region (104 b) is arranged in the N well active region (104) at the center of the adjacent first N+ region (104 a), the second N+ region (104 b) is symmetrical about a second symmetry axis (Y2), and the second N+ region (104 b) is arranged parallel to the edge of the N well active region (104);

the first N+ region (104 a) is larger in size than the second N+ region (104 b).

6. The low offset hall device employing a double guard ring as claimed in claim 5, wherein: the four second N+ regions (104 b) are provided with metal, so that four output electrodes E, F, G and H are formed;

the two output electrodes E and H and F and G on opposite angles are short-circuited by metal wires.

7. The low offset hall device employing a double guard ring according to any one of claims 4 to 6, wherein: the surface of the high-voltage N well (202) is provided with a third N+ region (104 c), and the third N+ region (104 c) is provided with metal to form a first contact electrode J.

8. The low offset hall device employing a double guard ring as claimed in claim 7, wherein: a non-electrode part above the N well active region (104) is covered with a first P+ region (104 d);

the surface of the high-voltage P well (203) is provided with a second P+ region (203 a), and the second P+ region (203 a) is provided with metal to form a second contact electrode K.

9. The low offset hall device employing a double guard ring as claimed in claim 8, wherein: an isolation shallow trench (300) is arranged between the first N+ region (104 a) and the third N+ region (104 c), and between the first N+ region (104 a) and the first P+ region (104 d), and between the third N+ region (104 c) and the second P+ region (203 a).

10. A method of using a low offset hall device employing a double guard ring as claimed in any one of claims 1 to 9:

inputting current or voltage bias signals with equal magnitudes and opposite directions to two opposite bias electrodes A and C;

the other two opposite bias electrodes B and D are grounded;

a Hall current or Hall voltage signal is output between the output electrodes E and F;

the first contact electrode J is connected with a high level; the second contact electrode K is grounded.