TWI438839B - Passivation layer formation by plasma clean process to reduce native oxide growth - Google Patents
Passivation layer formation by plasma clean process to reduce native oxide growth Download PDFInfo
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- TWI438839B TWI438839B TW097149788A TW97149788A TWI438839B TW I438839 B TWI438839 B TW I438839B TW 097149788 A TW097149788 A TW 097149788A TW 97149788 A TW97149788 A TW 97149788A TW I438839 B TWI438839 B TW I438839B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Description
本發明之實施例大致上關於用以處理基材的方法,並且特別是關於電漿清潔製程期間之氧化物蝕刻的方法。Embodiments of the present invention generally relate to methods for treating substrates, and in particular to methods of oxide etching during a plasma cleaning process.
在半導體、顯示器、太陽能電池與其他電子裝置製造中,當基材表面暴露於空氣中的氧和水,原生氧化物典型地會形成。氧暴露係發生在基材於大氣或外界(ambient)條件下移動於多個製程腔室之間時,或在少量氧留置在製程腔室中時。原生氧化物也可以從蝕刻製程期間的污染造成。原生氧化物膜通常非常薄,例如介於5-20之間,但厚到足以造成後續製造過程中的困難。所以,通常不樂見原生氧化物層,且需要在後續的製造過程之前將其去除。In the manufacture of semiconductors, displays, solar cells, and other electronic devices, native oxides are typically formed when the surface of the substrate is exposed to oxygen and water in the air. Oxygen exposure occurs when the substrate is moved between a plurality of process chambers under atmospheric or ambient conditions, or when a small amount of oxygen is retained in the process chamber. Primary oxides can also be caused by contamination during the etching process. Primary oxide films are usually very thin, for example between 5-20 Between, but thick enough to cause difficulties in the subsequent manufacturing process. Therefore, the native oxide layer is often not appreciated and needs to be removed prior to subsequent manufacturing processes.
這樣的困難通常會影響形成在基材上之電子元件的電氣性質。例如,特定問題出現在原生氧化矽膜形成於暴露的含矽層上時,尤其是在處理金屬氧化物矽場效應電晶體(“MOSFET”)結構期間。氧化矽膜是電氣絕緣的,並且不樂見在與接觸電極或內連電氣路徑之間的界面,這是因為氧化矽膜會造成高的電接觸電阻。在MOSFET結構中,電極與內連路徑係包括金屬矽化物層,其中該些金屬矽化物層是藉由沉積耐火金屬於裸矽上及將該層退火以產生金屬矽化物層來形成。位在基材與金屬之間界面的原生氧化矽膜係藉由阻礙用以形成金屬矽化物之擴散化學反應而降低金屬矽化物層的組成均勻性。由於電氣接點處的過熱,這會導致低的基材良率以及高的失效率。原生氧化矽膜也會阻礙其他CVD或濺射層的附著,其中該些CVD或濺射層係後續地被沉積在基材上。Such difficulties often affect the electrical properties of the electronic components formed on the substrate. For example, a particular problem arises when a native yttria film is formed on an exposed ruthenium containing layer, especially during the processing of a metal oxide 矽 field effect transistor ("MOSFET") structure. The hafnium oxide film is electrically insulating and is not expected to be at the interface with the contact electrode or the interconnected electrical path because the hafnium oxide film causes high electrical contact resistance. In the MOSFET structure, the electrode and interconnect paths comprise a metal telluride layer formed by depositing a refractory metal on the bare ridge and annealing the layer to produce a metal mash layer. The native ruthenium oxide film at the interface between the substrate and the metal reduces the compositional uniformity of the metal telluride layer by hindering the diffusion chemical reaction for forming the metal ruthenium. This can result in low substrate yield and high failure rate due to overheating at the electrical contacts. The native ruthenium oxide film also hinders the attachment of other CVD or sputtered layers that are subsequently deposited on the substrate.
濺射蝕刻製程已經用來減少深寬比小於約4:1之大特徵結構中或小特徵結構中的污染物。然而,濺射蝕刻製程會藉由物理轟擊損壞精緻的矽層。對此,使用氫氟酸的濕式蝕刻製程也已經用來去除原生氧化物。然而,濕式清潔蝕刻製程對於深寬比超過4:1且特別是深寬比超過10:1之更小的元件是不利的。尤其,水溶液具有穿透到介層洞、接點、或其他形成在基材表面內之小特徵結構的困難度。故,原生氧化物膜的去除並不完全。同樣地,若蝕刻溶液成功地穿夠小特徵結構,一旦蝕刻完成後,濕式蝕刻溶液更加難以從特徵結構去除。此外,濕式蝕刻製程通常具有嚴格的時序控制、會在基材上產生不期望的水痕、並且因大量的有毒廢水而具有環境考量。Sputter etching processes have been used to reduce contaminants in large or small features with aspect ratios less than about 4:1. However, the sputter etch process can damage the delicate ruthenium layer by physical bombardment. In this regard, a wet etching process using hydrofluoric acid has also been used to remove native oxides. However, the wet cleaning etch process is disadvantageous for components having an aspect ratio of more than 4:1 and especially a smaller aspect ratio of more than 10:1. In particular, aqueous solutions have the difficulty of penetrating into vias, joints, or other small features formed in the surface of the substrate. Therefore, the removal of the native oxide film is not complete. Likewise, if the etch solution successfully penetrates the small features, once the etch is complete, the wet etch solution is more difficult to remove from the features. In addition, wet etching processes typically have tight timing control, can create undesirable water marks on the substrate, and have environmental considerations due to the large amount of toxic waste water.
另一種去除原生氧化物膜的方式是乾式蝕刻製程,例如使用氟(F2 )氣體的乾式蝕刻製程。但是,使用含氟氣體的一缺失即是氟典型地會殘留在基材表面上。殘留在基材表面上的氟原子或氟基團是有害的。例如,殘留的氟原子會持續蝕刻基材,在基材內形成孔隙。Another way to remove the native oxide film is a dry etch process, such as a dry etch process using fluorine (F 2 ) gas. However, the absence of a fluorine-containing gas, that is, fluorine, typically remains on the surface of the substrate. Fluorine or fluorine groups remaining on the surface of the substrate are detrimental. For example, residual fluorine atoms continue to etch the substrate to form pores within the substrate.
更近來的一種去除原生氧化物的方式已經在基材表面形成一氟/含矽鹽,該鹽隨後藉由熱退火製程來去除。在此方式中,藉由將含氟氣體與氧化矽表面反應來形成一薄的鹽層。然後,鹽被加熱到足以將鹽分解成揮發性副產物的高溫,其中該副產物隨後從製程腔室來去除,反應性含氟氣體的形成通常是藉由熱加成或藉由電漿能量來輔助。鹽通常形成在需要冷卻基材表面的低溫。此種冷卻而接著加熱的順序是藉由將基材從一冷卻腔室(在此處基材係被冷卻)傳送到一獨立的退火腔室或爐(在此處基材係被加熱)來達成。A more recent way to remove native oxide has formed a fluorine/barium containing salt on the surface of the substrate which is subsequently removed by a thermal annealing process. In this manner, a thin salt layer is formed by reacting a fluorine-containing gas with a surface of cerium oxide. The salt is then heated to a temperature sufficient to decompose the salt into volatile by-products, which are subsequently removed from the process chamber, and the formation of the reactive fluorine-containing gas is typically by thermal addition or by plasma energy. To assist. Salts are typically formed at low temperatures where it is desirable to cool the surface of the substrate. This cooling followed by heating is carried out by transferring the substrate from a cooling chamber where the substrate is cooled to a separate annealing chamber or furnace where the substrate is heated. Achieved.
基於各種理由,此反應性氟製程順序是不樂見的。也就是,由於其涉及基材傳送的時間,產能會大幅地降低。此外,在多個腔室之間傳送基材的期間,基材極容易遭受進一步的氧化或其他的污染。再者,因需要兩個獨立的腔室來完成氧化物去除製程,這會使成本加倍。This reactive fluorine process sequence is unpleasant for a variety of reasons. That is, since it involves the time of substrate transfer, the productivity is greatly reduced. Furthermore, during the transfer of the substrate between the plurality of chambers, the substrate is extremely susceptible to further oxidation or other contamination. Furthermore, the need for two separate chambers to complete the oxide removal process doubles the cost.
因此,需要一種方法來去除或蝕刻原生氧化物,同時可鈍化下方的基材表面,較佳是在單個製程腔室內。Therefore, a need exists for a method to remove or etch native oxide while passivating the underlying substrate surface, preferably within a single process chamber.
本文描述的實施例係提供用於去除基材上原生氧化物,同時將下方的基材表面予以鈍化之方法。在一實施例中,本發明提供一種用於從一基材表面去除原生氧化物之方法方法,其包括:放置一基材於一製程腔室內,該基材在基材表面上含有一氧化物層;調整該基材之一第一溫度到約80℃或更小;在該製程腔室內從一氣體混合物產生一清潔電漿,其中該氣體混合物包含氨和三氟化氮且NH3 /NF3 莫耳比例為約10或更大;及在一電漿清潔製程期間,使該清潔電漿凝結到該基材上且形成一薄膜。該薄膜包含部分從原生氧化矽層之矽形成的六氟矽酸銨。該方法更包括在該製程腔室內加熱該基材到約100℃或更大之一第二溫度,同時從該基材去除該薄膜且在該基材上形成一鈍化表面。在一實例中,該基材之第一溫度介於約20℃至約80℃之間,且該基材之第二溫度介於約100℃至約200℃之間。在另一實例中,該基材之第一溫度介於約22℃至約40℃之間,且該基材之第二溫度介於約110℃至約150℃之間。The embodiments described herein provide a method for removing native oxide on a substrate while passivating the underlying substrate surface. In one embodiment, the present invention provides a method for removing native oxide from a surface of a substrate, comprising: placing a substrate in a process chamber, the substrate containing an oxide on the surface of the substrate a layer; adjusting a first temperature of the substrate to about 80 ° C or less; generating a cleaning plasma from a gas mixture in the process chamber, wherein the gas mixture comprises ammonia and nitrogen trifluoride and NH 3 /NF The 3 molar ratio is about 10 or greater; and during a plasma cleaning process, the cleaning plasma is condensed onto the substrate and a film is formed. The film comprises ammonium hexafluoroantimonate partially formed from the ruthenium of the native ruthenium oxide layer. The method further includes heating the substrate to a second temperature of about 100 ° C or greater in the process chamber while removing the film from the substrate and forming a passivated surface on the substrate. In one example, the first temperature of the substrate is between about 20 ° C and about 80 ° C, and the second temperature of the substrate is between about 100 ° C to about 200 ° C. In another example, the first temperature of the substrate is between about 22 ° C and about 40 ° C and the second temperature of the substrate is between about 110 ° C to about 150 ° C.
在另一實施例中,本文提供一種用於從一基材表面去除原生氧化物之方法,其包括:放置一基材於一製程腔室內,該基材在基材表面上含有一氧化物層;調整該基材之一第一溫度到小於約100℃;在該製程腔室內從一氣體混合物產生一清潔電漿。該氣體混合物包含氨和三氟化氮且NH3 /NF3 莫耳比例為約20或更大,並且該清潔電漿係以約5瓦至約50瓦之間的RF功率來產生。該方法更包括在一電漿清潔製程期間,將該基材暴露於該清潔電漿以形成一含六氟矽酸銨的薄膜。該方法更包括在該製程腔室內加熱該基材到約100℃或更大之一第二溫度,同時從該基材去除該薄膜且在該基材上形成一鈍化表面。In another embodiment, a method for removing native oxide from a surface of a substrate is provided herein, comprising: placing a substrate in a process chamber, the substrate comprising an oxide layer on a surface of the substrate Adjusting a first temperature of the substrate to less than about 100 ° C; producing a cleaning plasma from a gas mixture within the processing chamber. The gas mixture comprises ammonia and nitrogen trifluoride and NH 3 / NF 3 mole ratio of about 20 or greater, and the plasma cleaning system to a RF power between about 5 watts to about 50 watts to produce. The method further includes exposing the substrate to the cleaning plasma during a plasma cleaning process to form a film comprising ammonium hexafluoroantimonate. The method further includes heating the substrate to a second temperature of about 100 ° C or greater in the process chamber while removing the film from the substrate and forming a passivated surface on the substrate.
在另一實施例中,本文提供一種用於從一基材表面去除原生氧化物之方法,其包括:放置一基材於一製程腔室內,該基材在基材表面上含有一氧化物層;調整該基材之一第一溫度到小於約100℃;在該製程腔室內從一氣體混合物產生一清潔電漿。該氣體混合物包含氨和三氟化氮且NH3 /NF3 莫耳比例為約10或更大,並且該清潔電漿係以約5瓦至約50瓦之間的RF功率來產生。該方法更包括:在一電漿清潔製程期間,將該基材暴露於該清潔電漿以形成一薄膜,其中該薄膜包含部分從氧化矽層形成的六氟矽酸銨;在該製程腔室內加熱該基材到約100℃或更大之一第二溫度,同時從該基材去除該薄膜且在該基材上形成一鈍化表面;及在該基材之鈍化表面上生長一磊晶層。In another embodiment, a method for removing native oxide from a surface of a substrate is provided herein, comprising: placing a substrate in a process chamber, the substrate comprising an oxide layer on a surface of the substrate Adjusting a first temperature of the substrate to less than about 100 ° C; producing a cleaning plasma from a gas mixture within the processing chamber. The gas mixture comprises ammonia and nitrogen trifluoride and NH 3 / NF 3 mole ratio of about 10 or more, and the plasma cleaning system to a RF power between about 5 watts to about 50 watts to produce. The method further includes: exposing the substrate to the cleaning plasma to form a film during a plasma cleaning process, wherein the film comprises ammonium hexafluoroantimonate partially formed from a ruthenium oxide layer; in the process chamber Heating the substrate to a second temperature of about 100 ° C or greater while removing the film from the substrate and forming a passivated surface on the substrate; and growing an epitaxial layer on the passivated surface of the substrate .
本發明之實施例係提供使NH3 /NF3 莫耳比例可以為約10、約15、約20或更大,同時該清潔電漿係以約5瓦至約50瓦之間(較佳為約15瓦至約30瓦)的RF功率來產生。該氣體混合物是藉由將氨和三氟化氮流到且結合到該製程腔室內來形成。氨之流速可以介於約20sccm至約300sccm之間,較佳為介於約40sccm至約200sccm之間,更佳為介於約60sccm至約150sccm之間,且更佳為介於約75sccm至約100sccm之間。三氟化氮之流速可以介於約1sccm至約60sccm之間,較佳為介於約2sccm至約50sccm之間,更佳為介於約3sccm至約25sccm之間,且更佳為介於約5sccm至約15sccm之間。Embodiments of the present invention provide that the NH 3 /NF 3 molar ratio can be about 10, about 15, about 20 or greater, while the cleaning plasma is between about 5 watts and about 50 watts (preferably RF power is generated from about 15 watts to about 30 watts. The gas mixture is formed by flowing ammonia and nitrogen trifluoride into and into the process chamber. The flow rate of ammonia can be between about 20 sccm and about 300 sccm, preferably between about 40 sccm and about 200 sccm, more preferably between about 60 sccm and about 150 sccm, and more preferably between about 75 sccm and about. Between 100sccm. The flow rate of the nitrogen trifluoride may be between about 1 sccm and about 60 sccm, preferably between about 2 sccm and about 50 sccm, more preferably between about 3 sccm and about 25 sccm, and more preferably between about 5sccm to about 15sccm.
於隨後暴露於該製程腔室外面的外界條件時,該鈍化表面係限制該基材上額外的原生氧化物生長之進一步形成。例如,在一外界環境中,後來的原生氧化物層可以在約5小時至約25小時之間的期間內形成為具有約6或更小的厚度。在另一實施例中,在一外界環境中,後來的原生氧化物層可以在約15小時至約30小時之間的期間內形成為具有約8或更小的厚度。在另一實施例中,在去除原生氧化物層之後,可以在該基材之鈍化表面上生長一磊晶層。The passivated surface limits further formation of additional native oxide growth on the substrate upon subsequent exposure to ambient conditions outside the process chamber. For example, in an external environment, a subsequent native oxide layer can be formed to have about 6 between about 5 hours and about 25 hours. Or smaller thickness. In another embodiment, in an external environment, the subsequent native oxide layer can be formed to have about 8 during a period of between about 15 hours and about 30 hours. Or smaller thickness. In another embodiment, an epitaxial layer can be grown on the passivated surface of the substrate after the native oxide layer is removed.
第1圖示出基材10的部分透視圖,其中該基材10具有形成在其中的一淺溝渠隔離區。圖中顯示的基材10僅部分地製造,並且具有形成在矽層1中的淺溝渠2。矽層1可以是一含矽下層或可以是確實的下方基材。淺溝渠2被填以氧化物,並用來隔離內建的電子元件(在此例中為電晶體)。源極3和汲極4可以藉由佈植離子到其內來形成在淺溝渠2中。多晶矽5設置在源極3與汲極4之間,而閘極氧化物層6設置在矽層1與多晶矽5之間。Figure 1 shows a partial perspective view of a substrate 10 having a shallow trench isolation region formed therein. The substrate 10 shown in the figures is only partially fabricated and has shallow trenches 2 formed in the ruthenium layer 1. The enamel layer 1 may be a sub-layer containing or may be a sub-substrate. The shallow trench 2 is filled with oxide and is used to isolate built-in electronic components (in this case, transistors). The source 3 and the drain 4 can be formed in the shallow trench 2 by implanting ions therein. The polysilicon 5 is disposed between the source 3 and the drain 4, and the gate oxide layer 6 is disposed between the germanium layer 1 and the polysilicon 5.
第2圖示出沿著切線2-2之基材10的部分截面圖。第2圖顯示多晶矽5接觸淺溝渠2之處。淺溝渠2是經由熱氧化物層7與沉積的氧化物層8來形成。預-多晶矽蝕刻/清潔步驟是藉由使用HF的濕式蝕刻製程來執行。因HF蝕刻熱氧化物層7之速度比蝕刻沉積的氧化物層8更快,間隙9形成在淺溝渠2中。隨後的多晶矽沉積使得多晶矽5填入間隙9且包覆源極3或汲極4,造成了寄生接合或漏電流。Figure 2 shows a partial cross-sectional view of the substrate 10 along the tangent 2-2. Figure 2 shows where the polysilicon 5 contacts the shallow trench 2. The shallow trench 2 is formed via the thermal oxide layer 7 and the deposited oxide layer 8. The pre-polysilicon etch/clean step is performed by a wet etch process using HF. Since the HF etches the thermal oxide layer 7 faster than the etch-deposited oxide layer 8, the gap 9 is formed in the shallow trench 2. Subsequent polysilicon deposition causes the polysilicon 5 to fill the gap 9 and coat the source 3 or the drain 4, causing parasitic bonding or leakage current.
第3圖示出根據本發明一實施例之製程腔室100的截面圖。在此實施例中,製程腔室100包括一設置在腔室主體112之上端的蓋組件200、以及一至少部分設置在腔室主體112內的支撐組件300。製程腔室也包括遠端電漿產生器140,遠端電漿產生器140具有一U型截面的遠端電極。較佳地,製程腔室100與相關的硬體是由一或多種與製程相容的材料來形成,例如鋁、陽極化鋁、鍍鎳的鋁、鍍鎳的鋁6061-T6、不銹鋼、以及前述組合和其合金。Figure 3 shows a cross-sectional view of process chamber 100 in accordance with an embodiment of the present invention. In this embodiment, the process chamber 100 includes a lid assembly 200 disposed at an upper end of the chamber body 112, and a support assembly 300 disposed at least partially within the chamber body 112. The process chamber also includes a distal plasma generator 140 having a U-shaped cross-section distal electrode. Preferably, the process chamber 100 and associated hardware are formed from one or more process compatible materials such as aluminum, anodized aluminum, nickel plated aluminum, nickel plated aluminum 6061-T6, stainless steel, and The foregoing combinations and alloys thereof.
支撐組件300係部分地設置在腔室主體112中。支撐組件300藉由軸314來上升和下降,其中該軸314被摺箱(bellow)333圍繞。腔室主體112包括形成於其側壁中的狹縫閥開口160,以提供存取製程腔室100的內部。選擇性開啟和關閉狹縫閥開口160,以便允許基材處理機器手臂(未示出)存取腔室主體112內部。在一實施例中,可透過狹縫閥開口160將基材傳送進出製程腔室100到鄰近的傳送腔室和/或負載閉鎖腔室(未示出),或叢集工具內的其他腔室。示範的叢集工具包括但不限於可從加州的聖克拉拉市的應用材料公司購得的、、和平台。The support assembly 300 is partially disposed in the chamber body 112. The support assembly 300 is raised and lowered by a shaft 314 that is surrounded by a bellows 333. The chamber body 112 includes a slit valve opening 160 formed in a sidewall thereof to provide access to the interior of the process chamber 100. The slit valve opening 160 is selectively opened and closed to allow a substrate processing robotic arm (not shown) to access the interior of the chamber body 112. In one embodiment, the substrate can be transported through the slit valve opening 160 into and out of the process chamber 100 to an adjacent transfer chamber and/or load lock chamber (not shown), or other chamber within the cluster tool. Exemplary clustering tools include, but are not limited to, available from Applied Materials, Inc. of Santa Clara, California. , , with platform.
腔室主體112亦包括形成於其中的通道113,用於在其中流通熱傳流體。熱傳流體可以是加熱流體或冷卻劑,且用於在製程和基材傳送期間控制腔室主體112的溫度。腔室主體112的溫度是重要的,以防止氣體或副產物在腔室壁上的不期望凝結。示範性熱傳流體包括水、乙二醇或其混合物。示範性熱傳流體亦可包括氮氣。The chamber body 112 also includes a channel 113 formed therein for circulating a heat transfer fluid therein. The heat transfer fluid can be a heating fluid or a coolant and is used to control the temperature of the chamber body 112 during processing and substrate transfer. The temperature of the chamber body 112 is important to prevent undesired condensation of gases or by-products on the walls of the chamber. Exemplary heat transfer fluids include water, ethylene glycol, or mixtures thereof. Exemplary heat transfer fluids can also include nitrogen.
腔室主體112進一步包括一內襯133,內襯133圍繞支撐組件300並且為了維護和清洗是可移除的。內襯133較佳係由例如鋁的金屬或陶瓷材料所製成。然而,在製程期間可以使用相容之材料。為了增加沉積於內襯133上之任何材料的附著,可噴砂處理內襯133,藉此避免導致製程腔室100之污染的材料剝落。內襯133通常包括一或多個孔洞135和一形成於其中之泵送通道129(其流體連通於一真空系統)。孔洞135提供氣體進入泵送通道129的流動路徑,而泵送通道提供通過內襯133的流動路徑,以便氣體可以離開製程腔室100。The chamber body 112 further includes a liner 133 that surrounds the support assembly 300 and is removable for maintenance and cleaning. The inner liner 133 is preferably made of a metal or ceramic material such as aluminum. However, compatible materials can be used during the process. To increase the adhesion of any material deposited on the liner 133, the liner 133 can be grit blasted, thereby avoiding material spalling that causes contamination of the process chamber 100. Liner 133 typically includes one or more apertures 135 and a pumping passage 129 formed therein (which is in fluid communication with a vacuum system). The bore 135 provides a flow path for gas to enter the pumping passage 129, while the pumping passage provides a flow path through the liner 133 so that gas can exit the process chamber 100.
真空系統可以包括真空泵125和節流閥127,以用於調節製程腔室100內的氣體流動。真空泵125連接到設置在腔室主體112上的真空埠131,並且流體連通於形成在內襯133中的泵送通道129。為了調節製程腔室100內的氣體流動,可通過節流閥127選擇性隔離真空泵125和腔室主體112。除非另外指出,可交替地使用術語「氣體」和「多種氣體」,且其是指一或多種前驅物、反應物、催化劑、載體、淨化(purge)、清潔、其組合、以及任何導入腔室主體112內的其他流體。The vacuum system can include a vacuum pump 125 and a throttle valve 127 for regulating gas flow within the process chamber 100. The vacuum pump 125 is connected to a vacuum crucible 131 disposed on the chamber body 112 and is in fluid communication with a pumping passage 129 formed in the liner 133. To regulate the flow of gas within the process chamber 100, the vacuum pump 125 and the chamber body 112 can be selectively isolated by a throttle valve 127. The terms "gas" and "multiple gases" are used interchangeably unless otherwise indicated, and refer to one or more precursors, reactants, catalysts, carriers, purges, cleaning, combinations thereof, and any introduction chambers. Other fluids within the body 112.
蓋組件200包括堆疊在一起的多個部件。例如,蓋組件200包括一蓋緣210、一氣體輸送組件220和一頂板250。蓋緣210係設計成支撐構成蓋組件200之多個部件的重量,並耦接到腔室主體112的上表面,以提供對內部腔室部件的存取。氣體輸送組件220係耦接到蓋緣210的上表面,並佈置成使其與蓋緣的熱接觸達到最小。蓋組件200的部件較佳係由具有高熱導率和低熱阻的材料所製成,諸如具有高光滑度表面的鋁合金。部件的熱阻較佳係小於約5×10-4 m2 K/W。The lid assembly 200 includes a plurality of components stacked together. For example, the lid assembly 200 includes a lid edge 210, a gas delivery assembly 220, and a top plate 250. The cover rim 210 is designed to support the weight of the various components that make up the lid assembly 200 and is coupled to the upper surface of the chamber body 112 to provide access to the interior chamber components. The gas delivery assembly 220 is coupled to the upper surface of the cover rim 210 and is arranged to minimize thermal contact with the cover rim. The components of the lid assembly 200 are preferably made of a material having high thermal conductivity and low thermal resistance, such as an aluminum alloy having a high smoothness surface. The thermal resistance of the component is preferably less than about 5 x 10 -4 m 2 K/W.
氣體輸送組件220可包括一氣體分佈板225或噴頭。通常係用氣體供應面板(未示出)向製程腔室100提供一或多種氣體。取決於將要在製程腔室100內執行的製程而使用特定的氣體或數種氣體。例如,典型的氣體包括一或多種前驅物、還原劑、催化劑、載體、淨化、清潔、或其混合物或組合。通常,使導入製程腔室100的一或多種氣體進入蓋組件200並隨後經由氣體輸送組件220進入腔室主體112。一電子操作閥和/或流動控制機構(未示出)可用來控制從氣體供應器到製程腔室100內的氣體流動。Gas delivery assembly 220 can include a gas distribution plate 225 or a showerhead. One or more gases are typically supplied to the process chamber 100 using a gas supply panel (not shown). A particular gas or gases are used depending on the process to be performed within the process chamber 100. For example, typical gases include one or more precursors, reducing agents, catalysts, supports, purification, cleaning, or mixtures or combinations thereof. Typically, one or more gases introduced into the process chamber 100 are introduced into the lid assembly 200 and then enter the chamber body 112 via the gas delivery assembly 220. An electronically operated valve and/or flow control mechanism (not shown) can be used to control the flow of gas from the gas supply to the process chamber 100.
在一態樣中,將氣體從氣體供應面板輸送到製程腔室100,其中氣體線路分成兩個獨立的氣體線路,該些獨立的氣體線路如上述般提供氣體給腔室主體112。取決於製程,任何數目的氣體可以用該方式來輸送,並可在製程腔室100中或在將其傳送到製程腔室100之前將其混合。In one aspect, gas is delivered from the gas supply panel to the process chamber 100, wherein the gas line is split into two separate gas lines that provide gas to the chamber body 112 as described above. Depending on the process, any number of gases can be delivered in this manner and can be mixed in the process chamber 100 or prior to being transferred to the process chamber 100.
仍然參照第3圖,蓋組件200可以進一步包括電極240,用以在蓋組件200內產生反應物種的電漿。在此實施例中,電極240被支撐在頂板250上,並且與其電氣隔離。一隔離體填充環(未示出)設置在電極240的底部周圍,使電極240與頂板250分離。一環形隔離體(未示出)設置在隔離體填充環的上部周圍並座落在頂板250之上表面上,如第3圖所示。接著將一環形隔離體(未示出)設置在電極240的上部附近,以便讓電極240與蓋組件200的其他部件電氣隔離。各個這些環、隔離體填充環和環形隔離體可以由氧化鋁或任何其他與製程相容之電氣絕緣材料製成。Still referring to FIG. 3, the lid assembly 200 can further include an electrode 240 for generating a plasma of the reactive species within the lid assembly 200. In this embodiment, the electrode 240 is supported on the top plate 250 and is electrically isolated therefrom. A spacer fill ring (not shown) is disposed around the bottom of the electrode 240 to separate the electrode 240 from the top plate 250. An annular spacer (not shown) is disposed around the upper portion of the spacer filling ring and is seated on the upper surface of the top plate 250 as shown in FIG. An annular spacer (not shown) is then placed adjacent the upper portion of electrode 240 to electrically isolate electrode 240 from other components of cover assembly 200. Each of these rings, the spacer fill ring and the annular spacer may be made of alumina or any other electrically insulating material compatible with the process.
電極240耦接到一電源340,同時氣體輸送組件220係接地。因此,一或多種製程氣體的電漿可在電極240和氣體輸送組件220之間形成的空間內引燃。電漿亦可容納於區隔板形成的空間中。在缺少區隔板組件的情況下,電漿被引燃並被容納於電極240和氣體輸送組件220之間。在任一實施例中,電漿可良好地被限制或被容納於蓋組件200內。The electrode 240 is coupled to a power source 340 while the gas delivery assembly 220 is grounded. Thus, plasma of one or more process gases can ignite within the space formed between electrode 240 and gas delivery assembly 220. The plasma can also be contained in the space formed by the partition. In the absence of a zone separator assembly, the plasma is ignited and contained between the electrode 240 and the gas delivery assembly 220. In either embodiment, the plasma can be well confined or housed within the lid assembly 200.
可使用能夠將氣體活化成反應物種並保持反應物種之電漿的任何電源。例如,可使用射頻(RF)、直流電流(DC)、交流電流(AC)或微波(MW)基功率放電技術。還可由熱基技術、氣體崩潰技術、高強度光源(例如UV能量)、或暴露於x-射線源來產生活化。替代地,可使用例如遠端電漿產生器的遠端活化源,來產生隨後將傳送到製程腔室100中之反應物種的電漿。示範性遠端電漿產生器可由諸如MKS Instruments,Inc.和Advanced Energy Industries,Inc.的販售商提供。較佳地,RF電源係耦接至電極240。Any power source capable of activating the gas into a reactive species and maintaining the plasma of the reactive species can be used. For example, radio frequency (RF), direct current (DC), alternating current (AC), or microwave (MW) based power discharge techniques can be used. Activation can also be produced by thermal based techniques, gas collapse techniques, high intensity light sources (eg, UV energy), or exposure to x-ray sources. Alternatively, a remote activation source, such as a remote plasma generator, can be used to generate a plasma that will subsequently be delivered to the reactive species in the process chamber 100. Exemplary distal plasma generators are available from vendors such as MKS Instruments, Inc. and Advanced Energy Industries, Inc. Preferably, the RF power source is coupled to the electrode 240.
取決於製程氣體和將要在製程腔室100內執行的操作,可加熱氣體輸送組件220。在一實施例中,例如電阻式加熱器的加熱構件270係耦接至氣體輸送組件220。在一實施例中,加熱構件270是管狀構件,並且被嵌入氣體輸送組件220的上表面。氣體輸送組件220的上表面包括具有略小於加熱構件270之外徑的寬度之溝槽或凹陷通道,以便使用抵觸配合(interference fit)將加熱構件270固持在溝槽中。Gas delivery assembly 220 may be heated depending on process gases and operations to be performed within process chamber 100. In an embodiment, a heating member 270, such as a resistive heater, is coupled to the gas delivery assembly 220. In an embodiment, the heating member 270 is a tubular member and is embedded in the upper surface of the gas delivery assembly 220. The upper surface of the gas delivery assembly 220 includes a groove or recessed passage having a width that is slightly smaller than the outer diameter of the heating member 270 to retain the heating member 270 in the groove using an interference fit.
由於輸送組件220(包括氣體輸送組件220和區隔元件230)的每個部件是彼此導電耦接的,加熱構件270可調節氣體輸送組件220的溫度。可以在2005年2月22日申請的美國專利申請案號11/063,645而公開為US 2005-0230350中獲得製程腔室的額外細節,這裏將其作為參考文獻。Since each component of the delivery assembly 220 (including the gas delivery assembly 220 and the compartment component 230) is electrically coupled to one another, the heating member 270 can adjust the temperature of the gas delivery assembly 220. Additional details of the process chamber can be found in U.S. Patent Application Serial No. 11/063,645, filed on Feb. 22, 2005, which is incorporated herein by reference.
對於執行需要不破壞真空而加熱和冷卻基材表面的電漿輔助乾式蝕刻製程而言,製程腔室100是特別有用的。在一實施例中,製程腔室100可用來選擇性去除基材上的一或多種氧化物。Process chamber 100 is particularly useful for performing a plasma assisted dry etch process that requires heating and cooling the surface of the substrate without breaking the vacuum. In an embodiment, the process chamber 100 can be used to selectively remove one or more oxides on the substrate.
在一實例中,使用氨(NH3 )和三氟化氮(NF3 )的氣體混合物來去除一或多種矽氧化物的乾式蝕刻製程可以執行於製程腔室100內。吾人相信除了均在單一製程環境內的基材加熱和冷卻以外,對於可從電漿製程受益的任何乾式蝕刻製程(包括退火製程)而言,製程腔室100是有利的。In one example, ammonia (NH 3) and nitrogen trifluoride (NF 3) gas mixture to remove one or more oxides of silicon dry etching process may be performed within the processing chamber 100. It is believed that the process chamber 100 is advantageous for any dry etch process (including annealing processes) that can benefit from the plasma process, in addition to substrate heating and cooling, all in a single process environment.
參照第3圖,乾式蝕刻製程開始於將基材110放入製程腔室100中。基材通常係通過狹縫閥開口160被放入腔室主體112中,並設置在支撐構件310的上表面上。可將基材110夾持到支撐構件310的上表面。較佳地,可藉由抽取真空將基材110夾持到支撐構件310的上表面。接著,如果支撐構件310還沒有處於製程位置,將支撐構件310上升至腔室主體112內的製程位置。較佳係將腔室主體112加熱至約50℃至約80℃之間的溫度,例如約65℃。藉由使熱傳介質流過通道113而保持腔室主體112的溫度。Referring to FIG. 3, the dry etch process begins by placing substrate 110 into process chamber 100. The substrate is typically placed into the chamber body 112 through the slit valve opening 160 and disposed on the upper surface of the support member 310. The substrate 110 can be clamped to the upper surface of the support member 310. Preferably, the substrate 110 can be clamped to the upper surface of the support member 310 by evacuating the vacuum. Next, if the support member 310 is not yet in the process position, the support member 310 is raised to a process position within the chamber body 112. Preferably, chamber body 112 is heated to a temperature between about 50 ° C to about 80 ° C, such as about 65 ° C. The temperature of the chamber body 112 is maintained by flowing the heat transfer medium through the passage 113.
藉由將熱傳介質或冷卻劑流過形成於支撐組件300內的通道,基材110被冷卻至約65℃以下,例如約15℃至約50℃之間。在一實施例中,將基材保持在室溫或室溫以下。在另一實施例中,將基材加熱到約22℃至約40℃之間的溫度下。通常,為了達到期望的基材溫度,將支撐構件310保持在約22℃以下。為了冷卻支撐構件310,使冷卻劑流過形成於支撐組件300內的流體通道。為了更好地控制支撐構件310的溫度,較佳係使用連續流動的冷卻劑。在一實例中,冷卻劑含有約50體積百分比(vol%)的乙二醇和50體積百分比(vol%)的水。只要能將基材保持在期望的溫度,可以使用其他比例的水和乙二醇。Substrate 110 is cooled to below about 65 °C, such as between about 15 °C and about 50 °C, by flowing a heat transfer medium or coolant through a passage formed in support assembly 300. In one embodiment, the substrate is maintained at or below room temperature. In another embodiment, the substrate is heated to a temperature between about 22 ° C to about 40 ° C. Typically, to achieve a desired substrate temperature, support member 310 is maintained below about 22 °C. To cool the support member 310, coolant is caused to flow through the fluid passage formed in the support assembly 300. In order to better control the temperature of the support member 310, it is preferred to use a continuously flowing coolant. In one example, the coolant contains about 50 volume percent (vol%) ethylene glycol and 50 volume percent (vol%) water. Other ratios of water and ethylene glycol can be used as long as the substrate can be maintained at the desired temperature.
為了選擇性去除基材110表面上的各種氧化物,將蝕刻氣體混合物導入製程室100。在一實施例中,接著將氨和三氟化氮氣體導入製程腔室100內以形成蝕刻氣體混合物。導入腔室內之各氣體的量是可變的並且可進行調整,以便相配於例如將要去除之氧化物層的厚度、被清洗之基材的幾何形態、電漿的體積容量、腔室主體112的體積容量、以及耦接至腔室主體112之真空系統的能力。In order to selectively remove various oxides on the surface of the substrate 110, an etching gas mixture is introduced into the process chamber 100. In one embodiment, ammonia and nitrogen trifluoride gas are then introduced into the process chamber 100 to form an etching gas mixture. The amount of each gas introduced into the chamber is variable and can be adjusted to match, for example, the thickness of the oxide layer to be removed, the geometry of the substrate being cleaned, the volumetric capacity of the plasma, and the chamber body 112. Volume capacity, and the ability to couple to the vacuum system of the chamber body 112.
可預先決定蝕刻氣體混合物的比例,以選擇性去除基材表面上的多種氧化物。在一實施例中,可調整蝕刻氣體混合物中的多種氣體的比例,以去除諸如熱氧化物、沉積氧化物、和/或原生氧化物的多種氧化物。在一實施例中,可設定蝕刻氣體混合物中之氨與三氟化氮的莫耳比例(在本文中稱為NH3 /NF3 莫耳比例)以去除原生氧化物。在一實施例中,添加氣體好提供氨與三氟化氮的莫耳比例為至少1:1之氣體混合物。在另一實施例中,蝕刻氣體混合物的NH3 /NF3 莫耳比例係至少為約10,較佳為約15或更大,且更佳為約20或更大(例如約30)。The ratio of the etching gas mixture can be predetermined to selectively remove various oxides on the surface of the substrate. In an embodiment, the ratio of the plurality of gases in the etching gas mixture can be adjusted to remove various oxides such as thermal oxides, deposited oxides, and/or native oxides. In one embodiment, the molar ratio may be set in the etching gas mixture of ammonia and nitrogen trifluoride (referred to as NH 3 / NF 3 mole ratio herein) to remove the native oxide. In one embodiment, the gas is added to provide a gas mixture having a molar ratio of ammonia to nitrogen trifluoride of at least 1:1. NH embodiment, the etching gas mixture In another embodiment of the 3 / NF 3 mole ratio based at least about 10, preferably about 15 or more, and more preferably about 20 or greater (e.g., about 30).
NH3 /NF3 莫耳比例係正比於氨與三氟化氮的氣體流速比例。在一實施例中,氨流入製程腔室內的流速可以介於約20sccm至約300sccm之間,較佳為介於約40sccm至約200sccm之間,更佳為介於約60sccm至約150sccm之間,且更佳為介於約75sccm至約100sccm之間。三氟化氮流入製程腔室內的流速可以介於約1sccm至約60sccm之間,較佳為介於約2sccm至約50sccm之間,更佳為介於約3sccm至約25sccm之間,且更佳為介於約5sccm至約15sccm之間。The NH 3 /NF 3 molar ratio is proportional to the gas flow rate ratio of ammonia to nitrogen trifluoride. In one embodiment, the flow rate of ammonia into the process chamber may be between about 20 sccm and about 300 sccm, preferably between about 40 sccm and about 200 sccm, more preferably between about 60 sccm and about 150 sccm. More preferably, it is between about 75 sccm and about 100 sccm. The flow rate of nitrogen trifluoride flowing into the process chamber may be between about 1 sccm and about 60 sccm, preferably between about 2 sccm and about 50 sccm, more preferably between about 3 sccm and about 25 sccm, and more preferably. It is between about 5 sccm and about 15 sccm.
亦可將淨化氣體或載氣加入蝕刻氣體混合物。可以使用任何合適的淨化氣體/載氣,例如氬、氦、氫、氮、或其混合物。通常,整個蝕刻氣體混合物之氨和三氟化氮為介於約0.05%至約20%體積百分比。載氣流入製程腔室內的流速可以介於約200sccm至約5000sccm之間,較佳為介於約500sccm至約4000sccm之間,更佳為介於約1000sccm至約3000sccm之間。在一實施例中,為了穩定腔室主體112內的壓力,在反應氣體前先將淨化氣體或載氣導入腔室主體112中。腔室主體112內的操作壓力是可變的。通常,腔室主體112的內部壓力可以介於約500mTorr至約30Torr之間,較佳為約1Torr至約10Torr之間,且更佳為介於約3Torr至約6Torr之間。A purge gas or carrier gas may also be added to the etching gas mixture. Any suitable purge gas/carrier gas can be used, such as argon, helium, hydrogen, nitrogen, or mixtures thereof. Typically, the ammonia and nitrogen trifluoride of the entire etching gas mixture is between about 0.05% and about 20% by volume. The flow rate of the carrier gas stream into the process chamber can be between about 200 sccm and about 5000 sccm, preferably between about 500 sccm and about 4000 sccm, more preferably between about 1000 sccm and about 3000 sccm. In one embodiment, to stabilize the pressure within the chamber body 112, a purge gas or carrier gas is introduced into the chamber body 112 prior to the reaction gas. The operating pressure within the chamber body 112 is variable. Generally, the internal pressure of the chamber body 112 can be between about 500 mTorr and about 30 Torr, preferably between about 1 Torr and about 10 Torr, and more preferably between about 3 Torr and about 6 Torr.
為了在容納於氣體輸送組件220中之空間261、262和263內引燃氣體混合物的電漿,可對電極240施加RF功率。RF功率可以介於約5瓦至約600瓦之間,較佳為小於約100瓦(例如約60瓦或更小),較佳為約50瓦或更小,且更佳為約40瓦或更小。在一實施例中,可在製程期間使用較低的RF功率來點燃氣體混合物並形成清潔電漿。RF功率可以介於約5瓦至約50瓦之間,較佳為介於約15瓦至約30瓦之間。在一實例中,電漿係使用約30瓦或更小的RF功率來生。在另一實例中,電漿係使用約15瓦或更小的RF功率來生。通常,施加功率的頻率是非常低的,例如小於100kHz。較佳地,頻率可以介於約50kHz至約90kHz之間。In order to align the plasma of the gas mixture within the spaces 261, 262 and 263 contained in the gas delivery assembly 220, RF power can be applied to the electrode 240. The RF power can be between about 5 watts and about 600 watts, preferably less than about 100 watts (e.g., about 60 watts or less), preferably about 50 watts or less, and more preferably about 40 watts or less. smaller. In an embodiment, lower RF power may be used during the process to ignite the gas mixture and form a clean plasma. The RF power can be between about 5 watts and about 50 watts, preferably between about 15 watts and about 30 watts. In one example, the plasma is produced using RF power of about 30 watts or less. In another example, the plasma is produced using RF power of about 15 watts or less. Typically, the frequency of applied power is very low, such as less than 100 kHz. Preferably, the frequency can be between about 50 kHz and about 90 kHz.
電漿能量將氨和三氟化氮分解為反應物種,該些反應物種會結合而形成諸如氟化銨(NH4 F)和/或氟化氫銨(NH4 F.HF2 )的反應氣體。此氣體混合物經由氣體分佈板225的孔洞225A流過氣體輸送組件220,以便與含有氧化物層(例如原生氧化矽層)的基材表面反應。在一實施例中,首先將載氣導入製程腔室100中,產生載氣的電漿,並且隨後將反應氣體、氨和三氟化氮加到電漿。The plasma energy decomposes ammonia and nitrogen trifluoride into reaction species that combine to form a reaction gas such as ammonium fluoride (NH 4 F) and/or ammonium hydrogen fluoride (NH 4 F.HF 2 ). This gas mixture flows through the gas delivery assembly 220 via the holes 225A of the gas distribution plate 225 to react with the surface of the substrate containing an oxide layer, such as a native yttria layer. In one embodiment, a carrier gas is first introduced into the process chamber 100 to produce a plasma of the carrier gas, and then the reactant gases, ammonia, and nitrogen trifluoride are added to the plasma.
不希望受理論限制,吾人相信蝕刻氣體、氟化銨和/或氟化氫銨與氧化矽表面反應,以形成六氟矽酸銨((NH4 )2 SiF6 )、氨和水。可藉由真空泵125將氣體的氨和水從製程腔室100中去除。特別地,在氣體經由真空埠131離開製程腔室100進入真空泵125之前,揮發性氣體流過形成於內襯133中之孔洞135而進入泵送通道129。一含六氟矽酸銨的薄膜形成在基材表面上。可以如下概述該反應機制:Without wishing to be bound by theory, it is believed that the etching gas, ammonium fluoride and/or ammonium hydrogen fluoride react with the surface of the cerium oxide to form ammonium hexafluoroantimonate ((NH 4 ) 2 SiF 6 ), ammonia and water. The ammonia and water of the gas can be removed from the process chamber 100 by a vacuum pump 125. In particular, the volatile gas flows through the holes 135 formed in the liner 133 into the pumping passage 129 before the gas exits the process chamber 100 through the vacuum crucible 131 into the vacuum pump 125. A film containing ammonium hexafluoroantimonate is formed on the surface of the substrate. The reaction mechanism can be summarized as follows:
NF3 +XS NH3 →NH4 F+NH4 F‧HF2 +N2 2NH4 F+2NH4 F‧HF2 +SiO2 →(NH4 )2 SiF6 +2H2 O+2NH3 (NH4 )2 SiF6 +熱量→2NH3 +2HF+SiF4 NF 3 + XS NH 3 →NH 4 F+NH 4 F‧HF 2 +N 2 2NH 4 F+2NH 4 F‧HF 2 +SiO 2 →(NH 4 ) 2 SiF 6 +2H 2 O+2NH 3 (NH 4 ) 2 SiF 6 + heat → 2NH 3 + 2HF + SiF 4
在基材表面上形成薄膜之後,可將支撐構件310上升到緊靠加熱之氣體分佈板225的退火位置。從氣體分佈板225輻射的熱量可將六氟矽酸鍍薄膜分解或昇華為諧如四氟化矽、氨和氟化氫的揮發性化合物。如上所述,接著可透過真空泵125將這些揮發性產物從製程腔室100中去除。通常,在約75℃或更大的溫度下,較佳為約100℃炙更大(例如介於約115℃至約200℃之間),將薄膜從基材分解且去除。After the film is formed on the surface of the substrate, the support member 310 can be raised to an annealing position against the heated gas distribution plate 225. The heat radiated from the gas distribution plate 225 can decompose or sublimate the hexafluoroantimonic acid plating film into volatile compounds such as antimony tetrafluoride, ammonia, and hydrogen fluoride. These volatile products are then removed from the process chamber 100 by a vacuum pump 125 as described above. Typically, the film is decomposed and removed from the substrate at a temperature of about 75 ° C or greater, preferably about 100 ° C and greater (e.g., between about 115 ° C to about 200 ° C).
將六氟矽酸銨薄膜分解成揮發性成分的熱能是藉由氣體分佈板225來對流或輻射。如上所述,將加熱構件270直接耦接到分佈板225,並且使加熱構件270工作,以便將分佈板225及與其熱接觸的部件加熱至介於約75℃至約300℃之間的溫度,較佳為介於約100℃至約200℃,更佳為介於約110℃至約150℃(例如約120℃)。The thermal energy which decomposes the ammonium hexafluoroantimonate film into a volatile component is convection or radiation by the gas distribution plate 225. As described above, the heating member 270 is directly coupled to the distribution plate 225 and the heating member 270 is operated to heat the distribution plate 225 and the components in thermal contact therewith to a temperature between about 75 ° C and about 300 ° C, It is preferably between about 100 ° C and about 200 ° C, more preferably between about 110 ° C and about 150 ° C (eg, about 120 ° C).
可以多種方式實現該上升變化。例如,升降機構330可以上升支撐構件310朝向分佈板225的下表面。在此上升步驟期間,將基材110固定至支撐構件310,例如藉由如上所述的真空夾持或靜電夾持。替代地,可以藉由透過升降環320來上升升降梢325,將基材110自支撐構件310上升並且置於緊靠加熱的分佈板225之處。This rising change can be achieved in a variety of ways. For example, the lifting mechanism 330 can raise the support member 310 toward the lower surface of the distribution plate 225. During this ascending step, the substrate 110 is secured to the support member 310, such as by vacuum or electrostatic clamping as described above. Alternatively, the substrate 110 can be raised from the support member 310 and placed in close proximity to the heated distribution plate 225 by raising the lift tip 325 through the lift ring 320.
其上具有薄膜之基材110的上表面與分佈板225之間的距離不是決定性的,而是例行實驗的結果。任何熟悉此技術領域之人士可以輕易地決定可快速且有效地蒸發薄膜且不損傷下方基材所需的間隔。然而,吾人相信約0.254mm(10mils)和5.08mm(200mils)之間的間隔是有效的。The distance between the upper surface of the substrate 110 having the film thereon and the distribution plate 225 is not critical, but is a result of routine experimentation. Anyone familiar with the art can readily determine the spacing required to evaporate the film quickly and efficiently without damaging the underlying substrate. However, we believe that the spacing between about 0.254 mm (10 mils) and 5.08 mm (200 mils) is effective.
一旦已經將薄膜從基材上去除,便淨化(purge)並排空(evacuate)製程腔室100。隨後透過將基材支撐件300下降到傳送位置、鬆持基材、以及經由狹縫閥開口160傳送基材,而將處理的基材移出腔室主體112。Once the film has been removed from the substrate, the process chamber 100 is purged and evacuated. The treated substrate is then removed from the chamber body 112 by lowering the substrate support 300 to the transfer position, loosening the substrate, and transporting the substrate via the slit valve opening 160.
本發明的一實施例可用來在淺溝渠隔離區的製造期間均勻地去除多種氧化物。STI是用於次-0.25微米製程之元件隔離技術的主要形式。STI製造通常包括溝渠遮罩和蝕刻、側壁氧化、溝渠填充和平坦化。第4A-4I圖是根據本發明一實施例之用於形成淺溝渠隔離區之製程順序的截面示意圖。An embodiment of the invention can be used to uniformly remove multiple oxides during fabrication of shallow trench isolation regions. STI is the primary form of component isolation technology for the sub-0.25 micron process. STI fabrication typically includes trench masking and etching, sidewall oxidation, trench filling, and planarization. 4A-4I are cross-sectional schematic views of a process sequence for forming shallow trench isolation regions in accordance with an embodiment of the present invention.
第4A圖示出形成阻障氧化物層402和沉積氮化物層403之後的半導體基材401。基材401可以是具有<100>晶體方位且直徑為150mm(6英吋)、200mm(8英吋)或300mm(12英吋)的矽基材。可在高溫氧化爐中在基材401上生長阻障氧化物層402。阻障氧化物層402的厚度可以為約150。在後續的氮化物剝離步驟期間,阻障氧化物層402可保護基材401免受污染。可在高溫低壓化學氣相沉積(LPCVD)爐中形成氮化物層403。氮化物層403一般是由氨和二氯矽烷氣體反應所形成之氮化矽(例如Si3 N4 )的薄膜。氮化物層403是耐用的遮罩材料,其在氧化物沉積期間保護基材401並且在後續化學機械研磨(CMP)期間作為研磨終止材料。FIG. 4A illustrates the semiconductor substrate 401 after forming the barrier oxide layer 402 and depositing the nitride layer 403. The substrate 401 may be a tantalum substrate having a <100> crystal orientation and having a diameter of 150 mm (6 inches), 200 mm (8 inches), or 300 mm (12 inches). The barrier oxide layer 402 can be grown on the substrate 401 in a high temperature oxidation furnace. The barrier oxide layer 402 may have a thickness of about 150 . The barrier oxide layer 402 can protect the substrate 401 from contamination during subsequent nitride stripping steps. The nitride layer 403 can be formed in a high temperature low pressure chemical vapor deposition (LPCVD) furnace. The nitride layer 403 is generally a thin film of tantalum nitride (e.g., Si 3 N 4 ) formed by the reaction of ammonia and methane chloride gas. Nitride layer 403 is a durable masking material that protects substrate 401 during oxide deposition and as a polishing termination material during subsequent chemical mechanical polishing (CMP).
第4B圖示出在氮化物層403上形成、曝光和顯影的光阻層404。可在光阻層404上形成溝渠圖案。後續的氮化物蝕刻和氧化物蝕刻步驟可在氮化物層403和阻障層402中形成溝渠圖案405,其暴露基材401中指定為隔離區域之位置。FIG. 4B illustrates a photoresist layer 404 formed, exposed, and developed on the nitride layer 403. A trench pattern can be formed on the photoresist layer 404. Subsequent nitride etch and oxide etch steps may form trench patterns 405 in nitride layer 403 and barrier layer 402 that expose locations in substrate 401 that are designated as isolation regions.
第4C圖示出使用例如乾式電漿蝕刻的蝕刻製程在基材401內形成淺溝渠406。淺溝渠406稍後將以介電質材料來填充且其將作為建構在基材401上之電子元件(例如,基材上金屬場效電晶體(MOSFET))間的隔離材料。FIG. 4C illustrates the formation of shallow trenches 406 within substrate 401 using an etching process such as dry plasma etching. The shallow trenches 406 will later be filled with a dielectric material and will serve as an isolation material between the electronic components (eg, metal field effect transistors (MOSFETs) on the substrate) that are built onto the substrate 401.
第4D圖示出在淺溝渠406內部形成的內襯氧化物層407。通常係在高溫氧化爐中生長內襯氧化物層407。內襯氧化物層407的目的是為了改善基材401與將要填充之溝渠氧化物之間的界面。4D shows a liner oxide layer 407 formed inside the shallow trenches 406. The liner oxide layer 407 is typically grown in a high temperature oxidation furnace. The purpose of the liner oxide layer 407 is to improve the interface between the substrate 401 and the trench oxide to be filled.
第4E圖示出在淺溝渠406內部之內襯氧化物層407上形成的氮化物內襯408。可透過電漿輔助化學氣相沉積(PECVD)製程從載氣(諸如氮或氬)中的矽烷和氨形成氮化物內襯408。氮化物內襯408的目的是為了在淺溝渠406中引發應力並避免由受應力之氧化物引起的機械失效。4E illustrates a nitride liner 408 formed on the inner liner oxide layer 407 inside the shallow trench 406. A nitride liner 408 can be formed from decane and ammonia in a carrier gas such as nitrogen or argon through a plasma assisted chemical vapor deposition (PECVD) process. The purpose of the nitride liner 408 is to induce stress in the shallow trenches 406 and to avoid mechanical failure caused by stressed oxides.
第4F圖示出填充在淺溝渠406和溝渠圖案405內部的溝渠氧化物409。通常係透過CVD製程以相當高的沉積速率來形成溝渠氧化物409。過度填充(overfill)溝渠氧化物409,以致溝渠氧化物409高於基材401之頂表面。FIG. 4F shows the trench oxide 409 filled in the shallow trench 406 and the trench pattern 405. The trench oxide 409 is typically formed by a CVD process at a relatively high deposition rate. The trench oxide 409 is overfilled such that the trench oxide 409 is higher than the top surface of the substrate 401.
為了獲得如第4G圖所示的平坦表面,可應用CMP製程。CMP製程可從溝渠氧化物409去除過量的氧化物。In order to obtain a flat surface as shown in Fig. 4G, a CMP process can be applied. The CMP process removes excess oxide from the trench oxide 409.
為了去除氮化物層403及暴露多種氧化物、阻障層402的熱氧化物、溝渠氧化物409的沉積氧化物、內襯氧化物層407的熱氧化物、和氮化物內襯408的氮化氧化物,可執行氮化物剝離步驟,如第4H圖所示。In order to remove the nitride layer 403 and expose the plurality of oxides, the thermal oxide of the barrier layer 402, the deposited oxide of the trench oxide 409, the thermal oxide of the liner oxide layer 407, and the nitride of the nitride liner 408. The oxide can be subjected to a nitride stripping step as shown in Figure 4H.
通常,將執行氧化物蝕刻步驟,以便使淺溝渠結構可用於後續製程步驟,例如各種井佈植。第4I圖示出在乾式蝕刻製程之後的STI。本發明的乾式蝕刻製程可用於蝕刻第4H圖中暴露的多種氧化物,以便在淺溝渠409上獲得大致上平坦的頂表面並避免不期望之接合或漏電流。在一實施例中,可在與製程腔室100相似的製程腔室內執行乾式蝕刻製程。可將基材400放置在製程腔室內並將其加熱到約100℃或更小的溫度,較佳為約80℃或更小,且更佳為約60℃或更小,例如介於約20℃至約60℃之間,較佳為介於約25℃至約50℃之間,且更佳為介於約30℃至約40℃之間(例如約35℃)。Typically, an oxide etch step will be performed to make the shallow trench structure available for subsequent processing steps, such as various well implants. Figure 4I shows the STI after the dry etch process. The dry etch process of the present invention can be used to etch various oxides exposed in Figure 4H to achieve a substantially flat top surface on shallow trenches 409 and to avoid undesirable bonding or leakage currents. In an embodiment, a dry etch process can be performed in a process chamber similar to process chamber 100. The substrate 400 can be placed in a process chamber and heated to a temperature of about 100 ° C or less, preferably about 80 ° C or less, and more preferably about 60 ° C or less, such as between about 20 Between ° C and about 60 ° C, preferably between about 25 ° C and about 50 ° C, and more preferably between about 30 ° C and about 40 ° C (eg, about 35 ° C).
為了去除基材400表面上的多種氧化物,將蝕刻氣體混合物導入製程腔室100。在一實施例中,將包含氨和三氟化氮氣體的蝕刻氣體混合物導入製程腔室中。為了相配於例如將要去除之氧化物層的厚度、基材400的幾何形態、電漿的體積容量、腔室的體積容量、真空系統的能力、以及基材400上不同氧化物的性質,可調整氨和三氟化氮的量和比例。亦可將淨化氣體或載氣加到蝕刻氣體混合物。接著引燃蝕刻氣體混合物的電漿。電漿與氧化物反應而在基材400上留下一層含六氟矽酸銨的薄膜。In order to remove various oxides on the surface of the substrate 400, an etching gas mixture is introduced into the process chamber 100. In one embodiment, an etching gas mixture comprising ammonia and nitrogen trifluoride gas is introduced into the process chamber. Adjustable to match, for example, the thickness of the oxide layer to be removed, the geometry of the substrate 400, the volumetric capacity of the plasma, the volumetric capacity of the chamber, the capabilities of the vacuum system, and the nature of the different oxides on the substrate 400. Amount and ratio of ammonia and nitrogen trifluoride. A purge gas or a carrier gas may also be added to the etching gas mixture. The plasma of the etching gas mixture is then ignited. The plasma reacts with the oxide to leave a film of ammonium hexafluoroantimonate on the substrate 400.
然後,為了將薄膜昇華,將基材400加熱到約100℃或更大的溫度,例如介於約100℃至約200℃之間,較佳為介於約100℃至約150℃之間,且更佳為介於約110℃至約125℃之間。接著可淨化和排空製程腔室,並且基材100準備好進行後續步驟。在一實施例中,基材在蝕刻製程期間係介於約20℃至約80℃之間的第一溫度,並且接著在昇華製程期間基材被加熱到介於約100℃至約150℃之間的第二溫度。在另一實例中,基材在蝕刻製程期間係介於約22℃至約40℃之間的第一溫度,並且接著在昇華製程期間基材被加熱到介於約110℃至約125℃之間的第二溫度。Then, in order to sublimate the film, the substrate 400 is heated to a temperature of about 100 ° C or greater, such as between about 100 ° C to about 200 ° C, preferably between about 100 ° C and about 150 ° C. More preferably, it is between about 110 ° C and about 125 ° C. The process chamber can then be purged and evacuated, and the substrate 100 is ready for the next steps. In one embodiment, the substrate is at a first temperature between about 20 ° C and about 80 ° C during the etching process, and then the substrate is heated to between about 100 ° C and about 150 ° C during the sublimation process. The second temperature between. In another example, the substrate is at a first temperature between about 22 ° C and about 40 ° C during the etching process, and then the substrate is heated to between about 110 ° C and about 125 ° C during the sublimation process. The second temperature between.
此處描述的蝕刻製程可用於製造期間的各種蝕刻步驟,特別是用於去除一或多種氧化物的步驟中。例如,佈植和沉積之前的多種回蝕可使用此處描述的蝕刻製程。在一實施例中,可在用來形成含矽材料之磊晶生長/沉積製程、多晶矽沉積製程、或矽化製程之前使用此處描述的蝕刻製程The etching process described herein can be used in various etching steps during fabrication, particularly in the step of removing one or more oxides. For example, multiple etch backs prior to implantation and deposition can use the etching process described herein. In one embodiment, the etching process described herein can be used prior to the epitaxial growth/deposition process, polysilicon deposition process, or deuteration process used to form the germanium containing material.
第5A-5H圖示出用於形成例如MOSFET結構500之電子元件之製程順序的截面示意圖,包括此處描述的乾式蝕刻製程和製程腔室100。可在例如矽或砷化鍺基材525的半導體材料上形成MOSFET結構500。基材525較佳是具有<100>晶體方位且直徑為150mm(6英吋)、200mm(8英吋)、或300mm(12英吋)的矽基材。通常,MOSFET結構500包括以下的組合:(i)介電質層,諸如二氧化矽、有機矽酸鹽、碳摻雜的氧化矽、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氮化矽、或其組合;(ii)半導體層,諸如摻雜的多晶矽、n-型或p-型摻雜的單晶矽;以及(iii)從金屬層或金屬矽化物層(諸如鎢、矽化鎢、鈦、矽化鈦、矽化鈷、矽化鎳、或其組合)形成的電氣接點和互連線。5A-5H illustrate cross-sectional schematic views of a process sequence for forming electronic components such as MOSFET structure 500, including the dry etch process and process chamber 100 described herein. MOSFET structure 500 can be formed on a semiconductor material such as tantalum or arsenide substrate 525. Substrate 525 is preferably a tantalum substrate having a <100> crystal orientation and a diameter of 150 mm (6 inches), 200 mm (8 inches), or 300 mm (12 inches). Typically, MOSFET structure 500 includes the following combinations: (i) a dielectric layer such as cerium oxide, an organic cerium oxide, a carbon doped cerium oxide, a phosphonium silicate glass (PSG), a borophosphonite glass. (BPSG), tantalum nitride, or a combination thereof; (ii) a semiconductor layer such as doped polysilicon, n-type or p-type doped single crystal germanium; and (iii) a metal layer or a metal telluride layer Electrical contacts and interconnects formed by tungsten, tungsten telluride, titanium, titanium telluride, cobalt telluride, nickel telluride, or combinations thereof.
參照第5A圖,主動電子元件的製造開始於形成可使主動電子元件與其他元件電氣隔離之電氣隔離區結構。存在幾種類型的電氣隔離區結構,諸如場氧化物阻障物、或淺溝渠隔離區。在此情況中,淺溝渠隔離區545A和545B係圍繞其中形成並準備元件的電子主動構件之暴露區域。STI可包括如第4A-I圖所述的兩種或多種氧化物。為了形成厚度約50到300埃的薄閘極氧化物層550,而熱氧化暴露區域。接著沉積、圖案化並蝕刻多晶矽層,以便形成閘極電極555。為了形成絕緣介電質層560,可以再氧化多晶矽閘極電極555的表面,以提供第5A圖所示結構。Referring to Figure 5A, the fabrication of active electronic components begins with the formation of an electrically isolated region structure that electrically isolates the active electronic components from other components. There are several types of electrical isolation region structures, such as field oxide barriers, or shallow trench isolation regions. In this case, shallow trench isolation regions 545A and 545B surround the exposed regions of the electronic active components in which the components are formed and prepared. The STI can include two or more oxides as described in Figures 4A-I. In order to form a thin gate oxide layer 550 having a thickness of about 50 to 300 angstroms, the exposed regions are thermally oxidized. The polysilicon layer is then deposited, patterned, and etched to form a gate electrode 555. To form the insulating dielectric layer 560, the surface of the polysilicon gate electrode 555 can be reoxidized to provide the structure shown in FIG. 5A.
第5B圖示出源極570A和汲極570B,其係藉由以適當之摻雜原子來摻雜合適區域來形成。例如,對於p-型基材525,使用包含砷或磷的n-型摻雜物種。通常,摻雜係透過離子佈植器加以執行,並且可包括例如濃度為約1013 原子/cm2 且能量約30到80keV的磷、或劑量約1×1015 到1×1017 原子/cm2 且能量約10到100keV的砷。在佈植製程之後,通過加熱基材(例如在快速熱製程(RTP)設備中)促使摻雜物進入基材525。此後,透過如上所述的乾式蝕刻製程剝離覆蓋源極570A和汲極570B區域的薄閘極氧化物層550,以便去除由佈植製程導致薄閘極氧化物層550中捕獲的任何雜質。亦可蝕刻淺溝渠隔離區545A和545B中的兩種或多種氧化物。為了相配於不同氧化物所需的各種蝕刻速率,可調整蝕刻氣體混合物。Figure 5B shows source 570A and drain 570B formed by doping a suitable region with appropriate dopant atoms. For example, for p-type substrate 525, an n-type dopant species comprising arsenic or phosphorus is used. Typically, the doping is performed by an ion implanter and may include, for example, phosphorus having a concentration of about 10 13 atoms/cm 2 and an energy of about 30 to 80 keV, or a dose of about 1 x 10 15 to 1 x 10 17 atoms/cm. 2 and arsenic with an energy of about 10 to 100 keV. After the implant process, the dopant is introduced into the substrate 525 by heating the substrate, such as in a rapid thermal process (RTP) device. Thereafter, the thin gate oxide layer 550 covering the source 570A and drain 570B regions is stripped through a dry etch process as described above to remove any impurities trapped in the thin gate oxide layer 550 caused by the implant process. Two or more oxides in the shallow trench isolation regions 545A and 545B may also be etched. The etching gas mixture can be adjusted to match the various etch rates required for different oxides.
參照第5C和第5D圖,藉由低壓化學氣相沉積(LPCVD)使用矽烷(SiH4 )、氯(Cl2 )和氨(NH3 )的氣體混合物在閘極電極555上和基材525表面上沉積氮化矽層575。如第5D圖所示,為了在閘極電極555的側壁上形成氮化物間隙壁580,隨後使用反應離子蝕刻(RIE)技術來蝕刻氮化矽層575。間隙壁580將閘極電極555頂表面上形成的矽化物層與源極570A和汲極570B上沉積的其他矽化物層電氣隔離。應該注意的是,可以由例如氧化矽的其他材料來製造電氣隔離側壁間隙壁580。通常係透過CVD或PECVD從四乙氧矽烷(TEOS)的饋入氣體在約600℃到約1000℃的溫度下沉積用於形成側壁間隙壁580之氧化矽層。雖然圖中示出的是在佈植和RTP活化之後形成間隙壁580,但是可在源極/汲極佈植和RTP活化之前形成間隙壁580。Referring to FIGS. 5C and 5D, a gas mixture of decane (SiH 4 ), chlorine (Cl 2 ), and ammonia (NH 3 ) is used on the gate electrode 555 and the surface of the substrate 525 by low pressure chemical vapor deposition (LPCVD). A tantalum nitride layer 575 is deposited thereon. As shown in FIG. 5D, in order to form a nitride spacer 580 on the sidewall of the gate electrode 555, a tantalum nitride layer 575 is subsequently etched using a reactive ion etching (RIE) technique. The spacer 580 electrically isolates the germanide layer formed on the top surface of the gate electrode 555 from the other germanide layers deposited on the source 570A and the drain 570B. It should be noted that the electrically isolated sidewall spacers 580 can be fabricated from other materials such as yttria. The ruthenium oxide layer for forming the sidewall spacers 580 is typically deposited by CVD or PECVD from a feed gas of tetraethoxy decane (TEOS) at a temperature of from about 600 ° C to about 1000 ° C. Although shown in the figures to form spacers 580 after implantation and RTP activation, spacers 580 may be formed prior to source/drain implantation and RTP activation.
參照第5E圖,通常係透過在製程之前和之後暴露於大氣中,而在暴露的矽表面形成原生氧化矽層585。為了改進所形成之金屬矽化物的合金化反應和電導率,必須在形成閘極電極555上的導電金屬矽化物接點、源極570A和汲極570B上之導電金屬矽化物觸點前去除原生氧化矽層585。原生氧化矽層585可增加半導體材料的電阻,且不良地影響接下來沉積之矽和金屬層的矽化反應。因此,必須在形成用於連接主動電子元件之金屬矽化物接點或導體前使用所述之乾式蝕刻製程去除該原生氧化矽層585。上述之乾式蝕刻製程可用於去除原生氧化矽層585,以便暴露源極570A、汲極570B和閘極電極555的頂表面,如第5F圖所示。淺溝渠隔離區545A和545B中的氧化物同樣暴露於乾式蝕刻製程。為了在不同表面獲得均勻的去除速率,可對乾式蝕刻製程進行適當調整,例如反應氣體比例。Referring to Figure 5E, the native yttria layer 585 is typically formed on the exposed ruthenium surface by exposure to the atmosphere before and after the process. In order to improve the alloying reaction and conductivity of the formed metal halide, it is necessary to remove the native contact before forming the conductive metal telluride contacts on the gate electrode 555, the source metal 570A and the drain metal 570B. The yttrium oxide layer 585. The native yttria layer 585 can increase the electrical resistance of the semiconductor material and adversely affect the subsequent deposition of germanium and metallization. Therefore, the native ruthenium oxide layer 585 must be removed using the dry etch process described prior to forming the metal hydride contacts or conductors used to connect the active electronic components. The dry etch process described above can be used to remove the native yttria layer 585 to expose the top surface of source 570A, drain 570B, and gate electrode 555, as shown in FIG. 5F. The oxides in the shallow trench isolation regions 545A and 545B are also exposed to a dry etch process. In order to obtain a uniform removal rate on different surfaces, the dry etching process can be appropriately adjusted, such as a reaction gas ratio.
此後,如第5G圖所示,為了沉積金屬層590,使用物理氣相沉積(PVD)或濺射製程。隨後,為了在金屬層590與矽接觸的區域中形成金屬矽化物,使用傳統爐內退火來退火金屬和矽層。通常在獨立的處理系統中執行退火。因此,可在金屬590上沉積保護蓋層(未示出)。蓋層通常是氮化物材料,且可以包括由氮化鈦、氮化鎢、氮化鉭、氮化鉿、氮化矽、其衍生物、其合金、或其組合所構成的群組中選擇的一或多種材料。蓋層可藉由任何沉積製程加以沉積,較佳係PVD製程。Thereafter, as shown in FIG. 5G, in order to deposit the metal layer 590, a physical vapor deposition (PVD) or sputtering process is used. Subsequently, in order to form a metal telluride in the region where the metal layer 590 is in contact with the crucible, conventional furnace annealing is used to anneal the metal and germanium layers. Annealing is typically performed in a separate processing system. Thus, a protective cap layer (not shown) can be deposited over the metal 590. The cap layer is typically a nitride material and may comprise a group selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, tantalum nitride, tantalum nitride, derivatives thereof, alloys thereof, or combinations thereof. One or more materials. The cap layer can be deposited by any deposition process, preferably a PVD process.
退火通常包括在氮氣環境中將MOSFET結構500加熱至介於600℃與800℃之間的溫度持續約30分鐘。替代地,可使用將MOSFET結構500快速加熱到約1000℃持續約30秒的快速熱退火製程來形成金屬矽化物595。合適的導電金屬包括鈷、鈦、鎳、鎢、鉑、和具有低接觸電阻且可以在多晶矽和單晶矽上形成可靠金屬矽化物接點的任何其他金屬。Annealing typically involves heating the MOSFET structure 500 to a temperature between 600 ° C and 800 ° C for about 30 minutes in a nitrogen atmosphere. Alternatively, the metal telluride 595 can be formed using a rapid thermal annealing process that rapidly heats the MOSFET structure 500 to about 1000 ° C for about 30 seconds. Suitable conductive metals include cobalt, titanium, nickel, tungsten, platinum, and any other metal that has low contact resistance and can form a reliable metal halide junction on polycrystalline germanium and single crystal germanium.
可以透過使用不侵襲金屬矽化物595、間隙壁580或場氧化物545A、B而去除金屬的王水(HCl和HNO3 )的濕式蝕刻來去除金屬層590的未反應部分,由此在閘極電極555、源極570A和汲極570B上留下自準直(self-aligned)金屬矽化物595,如第5H圖所示。此後,可以在電極結構上沉積包括例如氧化矽、BPSG或PSG的絕緣罩層。可以透過在CVD室中的化學氣相沉積來沉積該絕緣罩層,其中來自饋入氣體之材料在低壓或常壓下凝結,例如如共同受讓的美國專利US 5,500249所描述的,這裏將其作為參考文獻。然後,為了形成光滑的平坦表面,在玻璃轉變溫度下退火MOSFET結構500。The unreacted portion of the metal layer 590 can be removed by wet etching using aqua regia (HCl and HNO 3 ) which does not attack the metal telluride 595, the spacer 580 or the field oxides 545A, B, thereby removing the metal layer 590. Self-aligned metal telluride 595 is left on pole electrode 555, source 570A, and drain 570B, as shown in FIG. 5H. Thereafter, an insulating cap layer including, for example, yttrium oxide, BPSG or PSG may be deposited on the electrode structure. The insulating cover layer can be deposited by chemical vapor deposition in a CVD chamber, wherein the material from the feed gas is condensed at a low pressure or a pressure, as described, for example, in the commonly assigned U.S. Patent No. 5,500,249. Use it as a reference. The MOSFET structure 500 is then annealed at a glass transition temperature in order to form a smooth, flat surface.
雖然已經描述了有關MOSFET元件的形成的上述製程順序,此處描述的乾式蝕刻製程亦可用於形成需要去除各種氧化物的其他半導體結構和元件。還可以在沉積包括例如鋁、銅、鈷、鎳、矽、鈦、鈀、鉿、硼、鎢、鉭、其合金、或其組合的不同金屬層的沉積之前使用乾式蝕刻製程。Although the above described process sequence for the formation of MOSFET elements has been described, the dry etch process described herein can also be used to form other semiconductor structures and components that require removal of various oxides. Dry etching processes can also be used prior to deposition of different metal layers including, for example, aluminum, copper, cobalt, nickel, niobium, titanium, palladium, tantalum, boron, tungsten, tantalum, alloys thereof, or combinations thereof.
在一實施例中,此處描述在實施例中的乾式蝕刻製程可以與水溶液蝕刻製程相結合。例如,對於具有至少兩種氧化物的氧化物結構,乾式蝕刻製程可能用於選擇性去除第一氧化物,其相對於第二氧化物完全地或部分地減少第一氧化物特徵。水溶液HF蝕刻製程可接著用於去除第二氧化物。In an embodiment, the dry etch process described herein in the embodiments can be combined with an aqueous etch process. For example, for an oxide structure having at least two oxides, a dry etch process may be used to selectively remove the first oxide, which completely or partially reduces the first oxide feature relative to the second oxide. The aqueous HF etching process can then be used to remove the second oxide.
為了提供前述描述的更好理解,給出下列非限制性實例。雖然此實例可能導向特定實施例,但不能認為實例在任何特定方面限制了本發明。In order to provide a better understanding of the foregoing description, the following non-limiting examples are given. While this example may be directed to a particular embodiment, the examples are not to be considered as limiting the invention in any particular respect.
將基材暴露於各種蝕刻製程,以去除原生氧化物層且在基材上形成鈍化表面。接著將基材在一時序期間暴露於外界條件,並且在鈍化表面上形成次原生氧化物層。在將基材暴露於外界條件的同時,依時序來監測次原生氧化物層的厚度,如第6圖所繪示。該各種蝕刻製程包括實驗A-E,如下表所概述。The substrate is exposed to various etching processes to remove the native oxide layer and form a passivated surface on the substrate. The substrate is then exposed to ambient conditions during a time sequence and a secondary native oxide layer is formed on the passivated surface. The thickness of the secondary native oxide layer is monitored in time series while exposing the substrate to ambient conditions, as depicted in FIG. The various etching processes included Experiments A-E as outlined in the following table.
在實驗A中,基材A暴露於HF濕式清潔溶液與製程。在實驗B與C中,基材B與C分別暴露於NH3 /NF3 莫耳比例為約5和約2之蝕刻氣體混合物,並且皆暴露於以約30瓦的RF功率來引燃的電漿。在實驗D與E中,基材D與E皆暴露於NH3 /NF3 莫耳比例為約20之蝕刻氣體混合物,但分別暴露於以約30瓦和15瓦的不同RF功率來引燃的電漿。In Experiment A, substrate A was exposed to an HF wet cleaning solution and process. In Experiments B and C, substrates B and C were exposed to an etching gas mixture having a NH 3 /NF 3 molar ratio of about 5 and about 2, respectively, and both exposed to electricity ignited at an RF power of about 30 watts. Pulp. In Experiments D and E, both substrates D and E were exposed to an etching gas mixture having a NH 3 /NF 3 molar ratio of about 20, but were respectively exposed to ignition at different RF powers of about 30 watts and 15 watts. Plasma.
對於實驗B-E,也將氬以約3500sccm流速隨著氨和三氟化氮導入製程腔室。製程腔室的內部壓力為約3Torr,並且基材溫度為約35℃。為了形成一含六氟矽酸銨的膜,將基材蝕刻長達120秒。For Experiment B-E, argon was also introduced into the process chamber with ammonia and nitrogen trifluoride at a flow rate of about 3500 sccm. The internal pressure of the process chamber was about 3 Torr and the substrate temperature was about 35 °C. To form a film containing ammonium hexafluoroantimonate, the substrate was etched for up to 120 seconds.
在隨後的退火製程期間,基材表面與噴頭間的間隔為約750mils。在腔室內以約1500sccm流速的氬進行載座淨化,以約500sccm流速的氬進行邊緣淨化。為了藉由昇華與/或分解將膜去除同時將基材表面予以鈍化,將蓋加熱到約120℃的溫度且將基材退火長達約60秒。約50的含原生氧化矽的材料從各基材表面去除。During the subsequent annealing process, the spacing between the substrate surface and the showerhead was about 750 mils. The chamber was purged with argon at a flow rate of about 1500 sccm in the chamber, and edge-purified with argon at a flow rate of about 500 sccm. To remove the film by sublimation and/or decomposition while passivating the surface of the substrate, the lid is heated to a temperature of about 120 ° C and the substrate is annealed for up to about 60 seconds. About 50 The raw cerium oxide-containing material is removed from the surface of each substrate.
一旦實驗A-E完成了蝕刻製程,將基材A-E退出製程腔室且將其放置在外界環境中,從而使基材在室溫(約22℃)下暴露於空氣中的氧和水。在約5小時的時序後,基材A、B和C各包含有大於約5的氧化物層,而基材D和E各包含有小於約5的氧化物層。在約10小時的時序後,基材A、B和C各包含有大於約7的氧化物層,而基材D和E各包含有小於約6的氧化物層。在約15小時、20小時和25小時的時序後,基材A、B和C各包含有大於約8的氧化物層,而基材D和E各包含有小於約6的氧化物層。此外,在約30小時的時序後,基材A、B和C各包含有約9或更大的氧化物層,而基材D和E各包含有小於約7的氧化物層。Once the experimental AE completed the etching process, the substrate AE was withdrawn from the process chamber and placed in an external environment, thereby exposing the substrate to oxygen and water in the air at room temperature (about 22 ° C). After about 5 hours of sequence, substrates A, B, and C each contain greater than about 5 Oxide layer, while substrates D and E each contain less than about 5 The oxide layer. After about 10 hours of time sequence, substrates A, B, and C each contain greater than about 7 Oxide layer, while substrates D and E each contain less than about 6 The oxide layer. Substrates A, B, and C each contain greater than about 8 after about 15 hours, 20 hours, and 25 hours of timing. Oxide layer, while substrates D and E each contain less than about 6 The oxide layer. In addition, after about 30 hours of sequence, substrates A, B, and C each contain about 9 Or a larger oxide layer, while substrates D and E each contain less than about 7 The oxide layer.
在實驗D與E期間形成的鈍化表面會於基材暴露於製程腔室外面之外界條件時在約5小時至約25小時之間的期間內限制在基材上進一步另一原生氧化物的形成到約6或更小的厚度。此外,在實驗D與E期間形成的鈍化表面會於基材暴露於製程腔室外面之外界條件時在約15小時至約30小時之間的期間內限制在基材上進一步另一原生氧化物的形成到約8或更小(較佳為約7或更小,且更佳為約6或更小)的厚度。The passivated surface formed during Experiments D and E limits further formation of another native oxide on the substrate during a period of between about 5 hours and about 25 hours when the substrate is exposed to the outer boundary conditions of the process chamber. To about 6 Or smaller thickness. In addition, the passivated surface formed during Experiments D and E limits further native oxide on the substrate during a period of between about 15 hours and about 30 hours when the substrate is exposed to the outer boundary conditions of the process chamber. Formation to about 8 Or smaller (preferably about 7 Or smaller, and more preferably about 6 Or smaller) thickness.
除非另外指出,否則在說明書和申請專利範圍中用來表示性質的量、反應條件等的所有數字應該理解為近似值。這些近似值是基於本發明欲獲得的期望性質和測量誤差,並且至少應該考慮報導的有效數字位元數並應用一般的四捨五入技術來解讀。另外,可以進一步最適化本文表示的任何數量,包括溫度、壓力、間隔、莫耳比例、流速等,以便獲得期望的蝕刻選擇性和性能。All numbers expressing quantities of properties, reaction conditions and the like in the specification and claims are to be understood as an approximation. These approximations are based on the desired properties and measurement errors to be obtained by the present invention, and at least the number of significant digits reported should be considered and interpreted using general rounding techniques. In addition, any of the quantities represented herein, including temperature, pressure, spacing, molar ratio, flow rate, etc., can be further optimized to achieve the desired etch selectivity and performance.
雖然前述說明指向於本發明的實施例,但在不偏離其基本範圍條件下可以設計出本發明的其他和額外實施例,因此其範圍係由申請專利範圍所確定。While the foregoing description is directed to embodiments of the present invention, other and additional embodiments of the present invention can be devised without departing from the basic scope thereof.
1...矽層1. . . Layer
2...淺溝渠2. . . Shallow ditch
3...源極3. . . Source
4...汲極4. . . Bungee
5...多晶矽5. . . Polycrystalline germanium
6...閘極氧化物層6. . . Gate oxide layer
7...熱氧化物層7. . . Thermal oxide layer
8...沉積的氧化物層8. . . Deposited oxide layer
9...間隙9. . . gap
10...基材10. . . Substrate
100...製程腔室100. . . Process chamber
110...基材110. . . Substrate
112...腔室主體112. . . Chamber body
113...通道113. . . aisle
125...真空泵125. . . Vacuum pump
127...節流閥127. . . Throttle valve
129...泵送通道129. . . Pumping channel
131...真空埠131. . . Vacuum
133...內襯133. . . Lining
135...孔洞135. . . Hole
140...遠端電漿產生器140. . . Remote plasma generator
160...狹縫閥開口160. . . Slit valve opening
200...蓋組件200. . . Cover assembly
210...蓋緣210. . . Cover edge
220...氣體輸送組件220. . . Gas delivery assembly
225...氣體分佈板225. . . Gas distribution plate
225A...孔洞225A. . . Hole
230...區隔元件230. . . Distinguishing element
240...電極240. . . electrode
250...頂板250. . . roof
270...加熱構件270. . . Heating member
300...支撐組件300. . . Support assembly
310...支撐構件310. . . Support member
314...軸314. . . axis
320...升降環320. . . Lifting ring
325...升降梢325. . . Lifting tip
330...升降機構330. . . Lifting mechanism
333...摺箱333. . . Folding box
340...電源340. . . power supply
400...基材400. . . Substrate
401...基材401. . . Substrate
402...阻障氧化物層402. . . Barrier oxide layer
403...氮化物層403. . . Nitride layer
404...光阻層404. . . Photoresist layer
405...溝渠圖案405. . . Ditch pattern
406...淺溝渠406. . . Shallow ditch
407...內襯氧化物層407. . . Lining oxide layer
408...氮化物內襯408. . . Nitride lining
409...溝渠氧化物409. . . Ditch oxide
500...MOSFET結構500. . . MOSFET structure
525...基材525. . . Substrate
545A...淺溝渠隔離區545A. . . Shallow trench isolation zone
545B...淺溝渠隔離區545B. . . Shallow trench isolation zone
550...薄閘極氧化物層550. . . Thin gate oxide layer
555...閘極電極555. . . Gate electrode
560...絕緣介電質層560. . . Insulating dielectric layer
570A...源極570A. . . Source
570B...汲極570B. . . Bungee
575...氮化矽層575. . . Tantalum nitride layer
580...間隙壁580. . . Clearance wall
585...原生氧化矽層585. . . Primary ruthenium oxide layer
590...金屬層590. . . Metal layer
595...金屬矽化物595. . . Metal telluride
本發明之前述特徵、詳細說明可以藉由參照實施例來詳細地瞭解,其中一些實施例係繪示在附圖中。然而,值得注意的是附圖僅示出本發明的典型實施例,並且因此不會限制本發明範圍,本發明允許其他等效的實施例。The foregoing features and detailed description of the invention may be It is to be understood, however, that the appended claims
第1圖示出基材的部分透視圖,其中該基材具有形成在其中的一淺溝渠隔離區,如本文的一實施例所述。Figure 1 shows a partial perspective view of a substrate having a shallow trench isolation region formed therein, as described in one embodiment herein.
第2圖示出一淺溝渠隔離區的部分截面圖,如本文的一實施例所述。Figure 2 shows a partial cross-sectional view of a shallow trench isolation region, as described in an embodiment herein.
第3圖示出根據本發明一實施例之製程腔室的截面圖。Figure 3 is a cross-sectional view showing a process chamber in accordance with an embodiment of the present invention.
第4A-4I圖示出根據本發明另一實施例之用於形成淺溝渠隔離區之製程順序的截面示意圖。4A-4I are schematic cross-sectional views showing a process sequence for forming a shallow trench isolation region in accordance with another embodiment of the present invention.
第5A-5H圖示出用於形成STI中隔離的電子元件之製程順序的截面示意圖,如本文的一實施例所述。5A-5H illustrate cross-sectional schematic views of a process sequence for forming isolated electronic components in an STI, as described in one embodiment herein.
第6圖顯示在各種鈍化基材表面上氧化物生長速率的一圖表,如本文的一些實施例所述。Figure 6 shows a graph of oxide growth rates on various passivated substrate surfaces, as described in some embodiments herein.
500...MOSFET結構500. . . MOSFET structure
525...基材525. . . Substrate
555...閘極電極555. . . Gate electrode
570A...源極570A. . . Source
570B...汲極570B. . . Bungee
580...間隙壁580. . . Clearance wall
595...金屬矽化物595. . . Metal telluride
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