Nothing Special   »   [go: up one dir, main page]

TWI420695B - 化合物半導體元件之封裝模組結構及其製造方法 - Google Patents

化合物半導體元件之封裝模組結構及其製造方法 Download PDF

Info

Publication number
TWI420695B
TWI420695B TW97140263A TW97140263A TWI420695B TW I420695 B TWI420695 B TW I420695B TW 97140263 A TW97140263 A TW 97140263A TW 97140263 A TW97140263 A TW 97140263A TW I420695 B TWI420695 B TW I420695B
Authority
TW
Taiwan
Prior art keywords
compound semiconductor
module structure
package module
semiconductor device
electrode
Prior art date
Application number
TW97140263A
Other languages
English (en)
Other versions
TW201017921A (en
Inventor
Wen Liang Tseng
Lung Hsin Chen
Chester Kuo
Original Assignee
Advanced Optoelectronic Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Optoelectronic Tech filed Critical Advanced Optoelectronic Tech
Priority to TW97140263A priority Critical patent/TWI420695B/zh
Priority to US12/580,497 priority patent/US20100096746A1/en
Publication of TW201017921A publication Critical patent/TW201017921A/zh
Application granted granted Critical
Publication of TWI420695B publication Critical patent/TWI420695B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

化合物半導體元件之封裝模組結構及其製造方法
本發明係關於一種化合物半導體元件之封裝模組結構及其製造方法，尤係關於一種光電半導體元件之薄型封裝模組結構及其製造方法。
由於光電元件中發光二極體(light emitting diode；LED)有體積小、發光效率高及壽命長等優點，因此被認為係次世代綠色節能照明的最佳光源。另外液晶顯示器的快速發展及全彩螢幕的流行趨勢，使白光系發光二極體除了應用於指示燈及大型顯示幕等用途外，更切入廣大之消費性電子產品，例如：手機及個人數位助理(PDA)。
圖1係習知表面黏著(SMD)元件之發光二極體元件之剖面示意圖。發光二極體晶粒12係藉由固晶膠11固定於絕緣層13c上N型導電銅箔13b之表面，並藉由金屬導線15與P型導電銅箔13a和N型導電銅箔13b電性相連，其中P型導電銅箔13a、N型導電銅箔13b及絕緣層13c構成具有電路之基板13。另外，透明膠材14覆蓋於基板13、金屬導線15及晶粒12上，可以保護整個發光二極體元件10不受環境及外力之破壞。
發光二極體元件10係使用一般印刷電路板作為基板13，因此其整體厚度因受限於基板13中絕緣層13c厚度而無法更薄。然消費性電子產品趨向於輕、薄、短、小之外型，因此其內部之各元件或外部殼體都需要小型化。另一方面，絕緣層13c多係散熱性較差之樹脂材料製成，因此不利於高功率發光化合物半導體元件作為傳導熱量之散熱途徑。因此若將複數個發光二極體元件10組成發光二極體模組，其將產生更嚴重之散熱問題。
綜上所述，市場上亟需要一種薄型化合物半導體元件之封裝模組結構，除了厚度要更薄而能節省所佔空間外，並且還要改善散熱不佳的問題，將更有利高功率元件之應用。
本發明係提供一種化合物半導體元件之封裝模組結構及其製造方法，該化合物半導體元件之封裝模組結構包含一散熱薄層，可有效進行熱逸散，因此可改善散熱不佳之問題。另外，化合物半導體元件之封裝模組結構由於使用薄型基板，其厚度可以更薄而能節省所佔空間。
本發明揭示一種化合物半導體元件之封裝模組結構，其包含一散熱薄層、一介電層、複數個化合物半導體晶粒、一將該半導體晶粒固接於該散熱薄層之手段以及一透明膠材。所述介電層包含複數個開口，形成於該散熱薄層上。複數個化合物半導體晶粒位在該介電層之複數個開口中之散熱薄層上，且化合物半導體晶粒係由該介電層分隔。透明膠材包覆該複 數個化合物半導體晶粒。
根據本發明之一實施例，化合物半導體元件之封裝模組結構另包含一電路板(例如軟性電路板)，該電路板包含第一電極及第二電極，分置於該化合物半導體晶粒之兩側之介電層上。將該半導體晶粒固接於該散熱薄層之手段係以固晶膠接合於該散熱薄層，且以金屬導線連接該第一電極及第二電極。本實施例中，化合物半導體元件之封裝模組結構之厚度介於0.4至0.8mm。
根據本發明之另一實施例，該散熱薄層為具有電路圖案之導電膜層，其包含第一電極及第二電極，分置於該化合物半導體晶粒之兩側。將該化合物半導體晶粒固接於該散熱薄層之手段係利用覆晶接合方式將該化合物半導體晶粒連接該導電膜層之第一電極及第二電極。利用複數個凸塊電性連接該化合物半導體晶粒與該導電膜層之第一電極及第二電極。本實施例中，化合物半導體元件之封裝模組結構之厚度介於0.15至0.3mm。
根據本發明第一實施例之化合物半導體元件之封裝模組結構之製造方法，其包含以下步驟：首先，提供一散熱薄層，且形成一介電層於該散熱薄層上。該介電層包含複數個開口。其次，將複數個化合物半導體晶粒固接於複數個開口中之散熱薄層上，且將一包含第一電極及第二電極之電路板覆蓋於該介電層上。第一電極及第二電極係分置於該化合物半導體晶粒兩側之介電層上。接著電性連接該複數個化合物半導體 晶粒與第一電極及第二電極，並將一透明膠材包覆該化合物半導體晶粒。一實施例中，該複數個化合物半導體晶粒與第一電極及第二電極可以焊線技術並藉由複數個金屬導線進行電性連接。
根據本發明第二實施例之化合物半導體元件之封裝模組結構之製造方法，其包含以下步驟：首先提供一散熱薄層，其中包含第一電極及第二電極，且形成一包含複數個開口之介電層於該散熱薄層上。接著將複數個化合物半導體晶粒固接於複數個開口中之散熱薄層上，且電性連接該第一電極及第二電極。之後將一透明膠材包覆該化合物半導體晶粒。一實施例中，將複數個化合物半導體晶粒固接於複數個開口之散熱薄層上係利用覆晶技術並藉由複數個凸塊使該化合物半導體晶粒與該第一電極及第二電極電性連接。
實際製作上，上述化合物半導體元件之封裝模組結構可先行形成於一暫用基板上，且於透明膠材包覆該化合物半導體晶粒後移除暫用基板。
10‧‧‧發光二極體元件
11‧‧‧介電材料層
12‧‧‧晶粒
13‧‧‧基板
13a‧‧‧P型導電銅箔
13b‧‧‧N型導電銅箔
13c‧‧‧絕緣層
14‧‧‧透明膠材
15‧‧‧金屬導線
20、40‧‧‧化合物半導體元件封裝模組結構
21‧‧‧電路板
22‧‧‧孔洞
23‧‧‧暫用基板
24‧‧‧散熱薄層
26‧‧‧介電層
27‧‧‧開口
28‧‧‧固晶膠
29‧‧‧晶粒
30‧‧‧金屬導線
31‧‧‧透明膠材
43‧‧‧暫用基板
44‧‧‧散熱薄層
46‧‧‧介電層
47‧‧‧開口
48‧‧‧凸塊
49‧‧‧晶粒
50‧‧‧透明膠材
70‧‧‧間隔槽
211‧‧‧N型電極
212‧‧‧P型電極
231‧‧‧第一表面
232‧‧‧第二表面
241‧‧‧第一表面
242‧‧‧第二表面
431‧‧‧第一表面
432‧‧‧第二表面
441‧‧‧N型電極
442‧‧‧P型電極
443‧‧‧第一表面
444‧‧‧第二表面
圖1係習知表面黏著(SMD)型式之發光二極體元件之剖面示意圖；圖2A~2H係本發明第一實施例之化合物半導體元件之封裝模組結構之製造方法之步驟示意圖；圖3A~3E係本發明第二實施例之化合物半導體元件之封裝模 組結構之製造方法之步驟示意圖。
圖2A~2H係本發明第一實施例之化合物半導體元件之封裝模組結構之製造方法之步驟示意圖。參照圖2A，其係一具孔洞22之電路板21之立體示意圖。一實施例中，該電路板21係一軟性電路板(例如FR-4)，其係先行準備以作為後續製作化合物半導體元件之封裝模組結構之構件。
如圖2B所示，一暫用基板23具有一第一表面231與一第二表面232，在圖2B中第一表面231係上表面，而第二表面232係下表面。暫用基板23可以由金屬材料、陶瓷材料或高分子材料所製成。暫用基板23之第一表面231上形成一散熱薄層24。散熱薄層24可以係金屬薄層，其材料可以係銀、鎳、銅、錫、鋁或前述金屬材料之合金，或者係銦錫氧化物(ITO)、銦鋅氧化物(IZO)、銦鎵氧化物(IGO)及銦鎢氧化物(IWO)等透明導電材料。
如圖2C所示，在該散熱薄層24上利用開膜、射出等步驟形成介電層26，且相鄰兩介電層26中形成開口27。開口27形成反射杯之結構。複數個開口27之位置分佈係一一對應於電路板21之孔洞22。
參照圖2D，藉由固晶膠28將化合物半導體晶粒29固定於開口27中之散熱薄層24上。之後，將電路板21覆蓋於介電層26上，其中電路板21之孔洞22對應於開口27，如圖2E所示。電路板21之電路設計將開口27兩側分別設為N型電極211及P型電 極212。一實施例中，晶粒29可為發光二極體，雷射二極體，或係光伏打電池(photocell)。
參照圖2F，利用銲線或係稱為打線接合(wire-bonding)技術並以金屬導線30完成晶粒29、N型電極211及P型電極212間之電性連接。
參照圖2G，覆蓋一透明膠材31於晶粒29、N型電極211、P型電極212及金屬導線30上。透明膠材31可為環氧樹脂(epoxy)或矽膠(silicone；又稱矽氧烷)等。該透明膠材31可混入螢光粉等光轉換材料，藉此可以被激發而產生二次光線，並和晶粒29產生之一次光線混合而形成白光或係其他種多波長之電磁輻射。混入的螢光體的材質可為釔鋁石榴石(YAG)，鋱鋁石榴石(TAG)，矽酸鹽族係(silicate)，氮化物為主(nitride-based)等不同的螢光體。透明膠材31可以藉由轉移成型(transfer-molding)或係注入成型(inject-molding)等方式形成。
當該透明膠材31硬化後，可以藉由彎折、分離、蝕刻、雷射切割或研磨將暫用基板23移除，以致散熱薄層24之第一表面241外露，至此化合物半導體元件之封裝模組結構20便已完成，如圖2H所示。又散熱薄層24之第一表面241係相對於第二表面242，該第二表面242仍被透明膠材31所覆蓋。
由於化合物半導體元件20兩端之N型電極211及P型電極212露出透明膠材31外，因此可以作為電性連接之外部接點。另一 方面，晶粒29產生之熱量直接透過很薄且導熱佳之散熱薄層24，因此可大幅增加封裝模組結構20之散熱效率。本發明化合物半導體元件20之厚度可以降至0.3mm~1.0mm，而形成超薄結構。
圖3A~3H係本發明第二實施例之化合物半導體元件之封裝模組結構之製造方法之步驟示意圖，其中主要係利用覆晶技術。
如圖3A所示，一暫用基板43具有一第一表面431與一第二表面432，在圖3A中第一表面431係上表面，而第二表面432係下表面。暫用基板43可以由金屬材料、陶瓷材料或高分子材料所製成，其第一表面431上有以印刷(printing)、網印(screening)、電鑄(electroform)、化鍍(無電解電鍍)或濺鍍(sputter)形成一具圖案之散熱薄層44。本實施例中，該散熱薄層44係一包含N型電極441和P型電極442之導電膜層，且分置於隔離槽70之兩側，形成封裝模組結構所需電路。導電膜層之材料可以係銀、鎳、銅、錫、鋁或前述金屬材料之合金，或者係銦錫氧化物(ITO)、銦鋅氧化物(IZO)、銦鎵氧化物(IGO)及銦鎢氧化物(IWO)等透明導電材料。
如圖3B所示，在該散熱薄層44上利用開膜、射出等步驟形成介電層46，其中相鄰之介電層46間形成複數個開口47。複數個開口47之位置分佈係對應於散熱薄層44之隔離槽70。
參照圖3C，晶粒49係覆晶固定於散熱薄層44，其中藉由複數 個凸塊48分別和N型電極441及P型電極442電性相連。
參照圖3D，形成透明膠材50於開口47中，而覆蓋晶粒49、N型電極441、P型電極442上。透明膠材50可為環氧樹脂或矽膠等，且可以藉由轉移成型或係注入成型等方式覆蓋於晶粒49上。
當該透明膠材50硬化後，可以藉由彎折、分離、蝕刻、雷射切割或研磨將暫用基板43移除，以致散熱薄層44之第一表面443外露，至此化合物半導體元件之封裝模組結構40便已完成，如圖3E所示。又散熱薄層44之第一表面443係相對於第二表面444，該第二表面444仍被透明膠材50所覆蓋。
由於化合物半導體元件40之N型電極441及P型電極442外露，因此可以作為電性連接之外部接點。另一方面，晶粒49產生之熱量直接透過很薄且導熱佳之散熱薄層44，因此可增加整體封裝模組結構之散熱效率。
上述實施例顯示之製程先後順序並無限制，惟需符合模組製程由高溫至低溫。
大體而言，而第二實施例採用覆晶技術，相較於第一實施例可進一步降低封裝模組結構40之厚度至0.1~0.6mm。本發明之封裝模組結構20、40可視需要為條狀之光條(light bar)或片狀之光板結構(light plate)，提供多樣化之應用。
相較於習知技術，除了提供薄型化之應用外，本發明之化合物半導體封裝模組結構20、40之整個下表面均為散熱薄層， 可有效逸散化合物半導體元件所發出之熱，增加散熱速率，進而增加化合物半導體之亮度、熱穩定度及使用壽命。另外，實施例中FPC之應用提供可撓特性而可克服表面彎曲之後端模組使用。
本發明之技術內容及技術特點已揭示如上，然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此，本發明之保護範圍應不限於實施例所揭示者，而應包括各種不背離本發明之替換及修飾，並為以下之申請專利範圍所涵蓋。
20‧‧‧化合物半導體元件之封裝模組結構
24‧‧‧散熱薄層
26‧‧‧介電層
28‧‧‧固晶膠
29‧‧‧化合物半導體元件晶粒
30‧‧‧金屬導線
31‧‧‧透明膠材
211‧‧‧N型電極
212‧‧‧P型電極
241‧‧‧第一表面
242‧‧‧第二表面

Claims (10)

  1. 一種化合物半導體元件之封裝模組結構之製造方法，包含以下步驟：提供一散熱薄層；通過開模或射出成型的方法形成一介電層於該散熱薄層上，該介電層包含複數個開口；將複數個化合物半導體晶粒固接於複數個開口中之散熱薄層上；提供一電路板，該電路板具有孔洞，並將一該電路板覆蓋於該介電層上，且使該電路板的孔洞與介電層上的開口一一對應，該電路板包含第一電極及第二電極，該第一電極及第二電極分置於該化合物半導體晶粒兩側之介電層上；電性連接該複數個化合物半導體晶粒與第一電極及第二電極；以及將一透明膠材包覆該化合物半導體晶粒。
  2. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中該散熱薄層係先行形成於一暫用基板上，且該暫用基板於透明膠材包覆該化合物半導體晶粒後移除。
  3. 根據請求項2之化合物半導體元件之封裝模組結構之製造方法，其中該暫用基板係藉由彎折、分離、蝕刻、雷射切割或研磨之方式而移除。
  4. 根據請求項2之化合物半導體元件之封裝模組結構之製造方 法，其中暫用基板係由金屬材料、陶瓷材料或高分子材料所製成。
  5. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中該散熱薄層係不具電路圖案之金屬薄層。
  6. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中該散熱薄層之材料係銀、鎳、銅、錫、鋁或前述金屬之合金。
  7. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中該複數個化合物半導體晶粒係以固晶膠接合於該散熱薄層。
  8. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中電性連接該複數個化合物半導體晶粒與第一電極及第二電極係以焊線技術並藉由複數個金屬導線進行電性連接。
  9. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中該化合物半導體晶粒可為發光二極體晶粒、雷射二極體或係光伏打電池。
  10. 根據請求項1之化合物半導體元件之封裝模組結構之製造方法，其中該透明膠材可為環氧樹脂或係矽氧烷。
TW97140263A 2008-10-21 2008-10-21 化合物半導體元件之封裝模組結構及其製造方法 TWI420695B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW97140263A TWI420695B (zh) 2008-10-21 2008-10-21 化合物半導體元件之封裝模組結構及其製造方法
US12/580,497 US20100096746A1 (en) 2008-10-21 2009-10-16 Package module structure of compound semiconductor devices and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97140263A TWI420695B (zh) 2008-10-21 2008-10-21 化合物半導體元件之封裝模組結構及其製造方法

Publications (2)

Publication Number Publication Date
TW201017921A TW201017921A (en) 2010-05-01
TWI420695B true TWI420695B (zh) 2013-12-21

Family

ID=42107992

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97140263A TWI420695B (zh) 2008-10-21 2008-10-21 化合物半導體元件之封裝模組結構及其製造方法

Country Status (2)

Country Link
US (1) US20100096746A1 (zh)
TW (1) TWI420695B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103190204B (zh) 2010-11-03 2016-11-16 3M创新有限公司 具有无引线接合管芯的柔性led器件
KR20130141559A (ko) 2010-11-03 2013-12-26 쓰리엠 이노베이티브 프로퍼티즈 컴파니 열 관리를 위한 가요성 ｌｅｄ 디바이스 및 제조 방법
US9698563B2 (en) 2010-11-03 2017-07-04 3M Innovative Properties Company Flexible LED device and method of making
JP5932835B2 (ja) * 2011-01-17 2016-06-08 コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． 低コストなカプセル化された発光装置
WO2013118076A1 (en) * 2012-02-10 2013-08-15 Koninklijke Philips N.V. Low cost encapsulated light-emitting device
DE102012002605B9 (de) 2012-02-13 2017-04-13 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils und optoelektronisches Halbleiterbauteil
TWI458113B (zh) 2012-05-04 2014-10-21 Taiwan Ic Packaging Corp Proximity sensor and its manufacturing method
US8889439B2 (en) * 2012-08-24 2014-11-18 Tsmc Solid State Lighting Ltd. Method and apparatus for packaging phosphor-coated LEDs
CH709337B1 (fr) * 2014-03-04 2016-12-30 Robert Alderton Unité d'éclairage LED et procédé de fabrication d'une telle unité.
US20160111581A1 (en) * 2014-10-16 2016-04-21 Semiconductor Components Industries, Llc Packaged semiconductor devices and related methods
JP6432343B2 (ja) * 2014-12-26 2018-12-05 日亜化学工業株式会社 発光装置の製造方法
CN106981483A (zh) * 2017-05-12 2017-07-25 中山市立体光电科技有限公司 一种线性led光源的封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200541026A (en) * 2004-06-03 2005-12-16 Univ Nat Central Light emitting diode package structure and manufacturing process thereof
CN1832212A (zh) * 2005-03-08 2006-09-13 安捷伦科技有限公司 具有增强热耗散的led安装
CN2916930Y (zh) * 2006-06-23 2007-06-27 甘翠 一种发光二极管光源
WO2007086668A1 (en) * 2006-01-26 2007-08-02 Lg Innotek Co., Ltd Package of light emitting diode and method for manufacturing the same
TW200820462A (en) * 2006-10-24 2008-05-01 Chipmos Technologies Inc Light emitting chip package and manufacturing thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387412B1 (en) * 2001-04-12 2009-03-11 Matsushita Electric Works, Ltd. Light source device using led, and method of producing same
KR100419611B1 (ko) * 2001-05-24 2004-02-25 삼성전기주식회사 발광다이오드 및 이를 이용한 발광장치와 그 제조방법
JP4045781B2 (ja) * 2001-08-28 2008-02-13 松下電工株式会社 発光装置
US6936855B1 (en) * 2002-01-16 2005-08-30 Shane Harrah Bendable high flux LED array
TWI261936B (en) * 2005-01-25 2006-09-11 Lustrous Technology Ltd LED package structure and mass production method of making the same
TWI325644B (en) * 2007-01-03 2010-06-01 Chipmos Technologies Inc Chip package and manufacturing thereof
KR100887475B1 (ko) * 2007-02-26 2009-03-10 주식회사 네패스 반도체 패키지 및 그 제조방법
TWI344708B (en) * 2007-04-30 2011-07-01 Jin Chyuan Biar Package structure of lighting element and lighting device thereof
TWI348229B (en) * 2007-07-19 2011-09-01 Advanced Optoelectronic Tech Packaging structure of chemical compound semiconductor device and fabricating method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200541026A (en) * 2004-06-03 2005-12-16 Univ Nat Central Light emitting diode package structure and manufacturing process thereof
CN1832212A (zh) * 2005-03-08 2006-09-13 安捷伦科技有限公司 具有增强热耗散的led安装
WO2007086668A1 (en) * 2006-01-26 2007-08-02 Lg Innotek Co., Ltd Package of light emitting diode and method for manufacturing the same
CN2916930Y (zh) * 2006-06-23 2007-06-27 甘翠 一种发光二极管光源
TW200820462A (en) * 2006-10-24 2008-05-01 Chipmos Technologies Inc Light emitting chip package and manufacturing thereof

Also Published As

Publication number Publication date
US20100096746A1 (en) 2010-04-22
TW201017921A (en) 2010-05-01

Similar Documents

Publication Publication Date Title
TWI420695B (zh) 化合物半導體元件之封裝模組結構及其製造方法
US20120002420A1 (en) LED module, LED package, and wiring substrate and method of making same
US8610146B2 (en) Light emitting diode package and method of manufacturing the same
EP2418702B1 (en) Light emitting device and lighting system having the same
EP2093811B1 (en) Package structure of compound semiconductor device
US20090022198A1 (en) Package structure of compound semiconductor device and fabricating method thereof
JP4910220B1 (ja) Ｌｅｄモジュール装置及びその製造方法
CN101630668B (zh) 化合物半导体元件及光电元件的封装结构及其制造方法
KR100977260B1 (ko) 고출력 엘이디 패키지 및 그 제조방법
KR100989579B1 (ko) 칩온보드형 발광 다이오드 패키지 및 그것의 제조 방법
CN101728370B (zh) 化合物半导体元件的封装模块结构及其制造方法
CN101546737B (zh) 化合物半导体元件的封装结构及其制造方法
JP2004172636A (ja) 発光ダイオード及び製造方法
TW201318235A (zh) 加強散熱的光學元件封裝
TWI573299B (zh) 化合物半導體元件之封裝模組結構及其製造方法
KR100985917B1 (ko) 대전력 광원 램프를 위한 효과적인 열방출 구조의 리드프레임, 전자 소자 및 그 제조 방법
TWI362122B (en) Light-emitting diode package structure and method for manufacturing the same
KR101456921B1 (ko) 세라믹 ｐｃｂ를 이용한 ｌｅｄ 광원모듈 및 그 제조방법
KR101146659B1 (ko) 광 패키지 및 그 제조 방법
JP2013135077A (ja) 半導体パッケージ用基板、半導体パッケージ、およびそれらの製造方法
KR101856217B1 (ko) 필름 타입의 광소자 패키지 및 그 제조 방법
TWI542031B (zh) 光學封裝及其製造方法
KR20110122496A (ko) 광 패키지 및 그 제조 방법
KR20120063702A (ko) 광패키지 및 그 제조방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees