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TWI407564B - 具有溝槽底部多晶矽結構之功率半導體及其製造方法 - Google Patents

具有溝槽底部多晶矽結構之功率半導體及其製造方法 Download PDF

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TWI407564B
TWI407564B TW099118429A TW99118429A TWI407564B TW I407564 B TWI407564 B TW I407564B TW 099118429 A TW099118429 A TW 099118429A TW 99118429 A TW99118429 A TW 99118429A TW I407564 B TWI407564 B TW I407564B
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heavily doped
doped polysilicon
power semiconductor
polysilicon structure
trench
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TW201145508A (en
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Kao Way Tu
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Great Power Semiconductor Corp
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Description

具有溝槽底部多晶矽結構之功率半導體及其製造方法
本發明係關於一種功率半導體及其製作方法，尤其是一種在溝槽底部具有重摻雜多晶矽結構之功率半導體及其製作方法。
相較於傳統之平面式功率半導體，其導通電流是沿著平行基材表面的走向流動，溝渠式功率半導體則是將閘極設置於溝槽內，以改變閘極通道的位置，使得導通電流沿著垂直於基材的方向流動。因而可以縮小元件尺寸，提高元件之積集度(integration)。常見的功率半導體包括金氧半導體場效應電晶體(MOSFET)、絕緣閘二極電晶體(IGBT)等。
功率半導體在運作過程中主要的能量損耗，包括來自於導通電阻之導通損失，以及來自於閘極電荷之切換損失。伴隨著操作頻率的提高，切換損失的重要性也更形增加。就功率半導體之結構特徵來看，透過降低其輸入電容(Ciss)與反饋電容(Crss)等，有助於改善切換速度，降低切換損失。不過，為了改善其輸入電容(Ciss)與反饋電容(Crss)，往往會增加製程之複雜度，而造成製作成本的提高。
爰是，尋找一個簡單的製作方法，可直接搭配既有的功率半導體製程，以降低功率半導體之輸入電容與反饋電容，是本技術領域一個重要的課題。
本發明之主要目的在於降低功率半導體之輸入電容與反饋電容，以減少高頻應用下之切換損失。
本發明提供一種功率半導體。此功率半導體包括一第一導電型之基材、一溝槽、一重摻雜多晶矽結構、一閘極多晶矽結構與一閘極介電層。其中，溝槽係形成於基材內。重摻雜多晶矽結構係位於溝槽之一下部份，並且，重摻雜多晶矽結構之至少一側邊係直接接觸基材。閘極多晶矽結構係位於溝槽之一上部份。閘極介電層係位於閘極多晶矽結構與重摻雜多晶矽結構之間。重摻雜多晶矽結構內之摻雜係透過重摻雜多晶矽結構之側邊向外擴散以形成一重摻雜區。
依據此功率半導體，本發明並提供一種功率半導體之製造方法。首先，提供一第一導電型之基材。隨後，形成一溝槽於基材內。然後，形成一重摻雜多晶矽結構於溝槽之一下部份內。此重摻雜多晶矽結構之至少一側邊係直接接觸基材。接下來，形成一閘極介電層至少覆蓋重摻雜多晶矽結構之一上表面。然後，形成一閘極多晶矽結構於溝槽之一上部份內。在形成重摻雜多晶矽結構之後，更包括施以一熱擴散製程，使重摻雜多晶矽結構內之摻雜向外擴散以形成一重摻雜區至少環繞重摻雜多晶矽結構之側邊。
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。
第1A至1G圖顯示本發明之溝槽式功率半導體之製造方法之第一實施例。如第1A圖所示，首先，提供一N型之基板100，隨後，形成一N型磊晶層110於基板100上，以構成一基材。然候，形成一溝槽120於磊晶層110內。
接下來，如第1B圖所示，全面沉積一具有重摻雜之多晶矽層(如圖中虛線部分所示)，然後再以蝕刻方式去除不必要的多晶矽材料，留下位於溝槽120之下部分之一重摻雜多晶矽結構142。基本上，磊晶層110(單晶結構)與多晶矽層(多晶結構)的蝕刻速率存在明顯的差異，透過適當調整其摻雜濃度，甚至可以使二者的蝕刻速率的差異達到十倍以上。因此，即使磊晶層110也會曝露在此蝕刻環境中，仍然可以利用前述蝕刻特性，達到選擇性蝕刻多晶矽層的目的。
隨後，如第1C圖，形成一底部介電層132覆蓋重摻雜多晶矽結構142之上表面。然後，如第1D圖所示，在溝槽120的裸露側壁上形成一側壁介電層134。前述底部介電層132與側壁介電層134即構成此溝槽式功率半導體結構之閘極介電層。接下來，形成一導電結構，例如一閘極多晶矽結構144，於溝槽120之上部份內。此閘極多晶矽結構144與重摻雜多晶矽結構142係透過底部介電層132分隔開來。
本實施例將閘極介電層之製作步驟區分為兩個部份，先形成厚度較厚的底部介電層132於重摻雜多晶矽結構142的上表面，然後再形成厚度較薄的側壁介電層134於溝槽120的側壁。此厚度較厚的底部介電層132有助於降低閘汲極間之電容值(Vgd)。
接下來，如第1E圖所示，以離子植入方式植入P型摻雜於磊晶層110內，然後再施以一熱擴散(drive-in)步驟，使植入的P型摻雜擴散，以形成P型本體150於相鄰二個溝槽120之間。值得注意的是，此熱擴散步驟同時會使重摻雜多晶矽結構142內的摻雜向外擴散，而在重摻雜多晶矽結構142的周圍形成一重摻雜區160。在本實施例中，重摻雜多晶矽結構142具有高濃度之N型摻雜，因而在周圍形成一N型重摻雜區160。此N型重摻雜區160的存在可以防止P型本體150的範圍擴散至溝槽120的底部，因而可以確保電晶體的正常運作。
接下來，如第1F圖所示，利用一源極光罩(未圖示)形成一光阻圖案175於P型本體150上方，以定義源極的位置。隨後，以離子植入方式植入N型摻雜於P型本體150內，以形成N型源極摻雜區170於溝槽120的側邊。然後，如第1G圖所示，形成一層間介電層180，例如硼磷矽玻璃(BPSG)層或磷矽玻璃(PSG)層，覆蓋閘極多晶矽結構144，同時在P型本體150上方定義出接觸窗182的位置。然後，在接觸窗182之底部植入P型摻雜，以形成一P型重摻雜區185。最後，沉積一源極金屬層190於層間介電層180上，並且填入接觸窗182內，以電性連接源極摻雜區170。
如前述，本實施例透過重摻雜多晶矽結構142的製作，可以有效調整P型本體150的輪廓，因而可採用深度較小之溝槽120，而不需顧慮P型本體會覆蓋溝槽120底部而導致元件失效。此深度較小的溝槽120有助於降低輸入電容Ciss，同時，覆蓋於閘極多晶矽結構144底部之底部介電層132有助於降低反饋電容Crss，因此，本實施例可以有效提升切換速率，降低切換損失。
第2圖顯示本發明溝槽式功率半導體之製造方法之第二實施例。不同於本發明之第一實施例，本實施例在利用硬質罩幕層125形成溝槽120之步驟後，並不移除此硬質罩幕層125，而是直接進行多晶矽層之沉積與蝕刻步驟。此覆蓋於磊晶層110上表面之硬質罩幕層125，有助於防止磊晶層110在蝕刻去除多晶矽材料的步驟中被同時蝕刻去除。
第3A與3B圖顯示本發明溝槽式功率半導體之製造方法之第三實施例。如第1G圖所示，在本發明之第一實施例中，重摻雜多晶矽結構142的下表面是直接與磊晶層110相接。相較之下，如第3A圖所示，本實施例在形成重摻雜多晶矽結構142前，先形成一第一介電層236於溝槽120的底部，然後再依序形成重摻雜多晶矽結構142與底部介電層132於溝槽120內。本實施例之後續製程與本發明之第一實施例相類似，在此不予贅述。請參照第3B圖所示，本實施例所形成之重摻雜區260僅環繞重摻雜多晶矽結構142之側邊，並未延伸包覆溝槽120的底部。雖然如此，此重摻雜區260一樣具有防止P型本體150延伸覆蓋溝槽120底部的效果。
前述各個實施例係利用傳統之溝槽式場效電晶體結構說明本發明之技術特徵。不過，本發明並不限於此。如第4A至4C圖所示，本發明之第四實施例係以一高壓溝槽式功率半導體(超接面(super junction)結構)說明本發明之技術特徵。
如第4A圖所示，首先，在N型磊晶層310中形成一深溝槽320。隨後，如第4B圖所示，在此深溝槽320內由下而上依序形成一第一介電層3411、一第一重摻雜多晶矽層3421、一第二介電層3412、一第二重摻雜多晶矽層3422等，而構成一介電層3411,3412,…3416與重摻雜多晶矽層3421,3422,...3426交疊的層狀結構。圖中係以六層重摻雜多晶矽層為例，不過，本發明並不限於此。
隨後，如第4B圖所示，在位於最上方的重摻雜多晶矽層3426之上表面形成一閘極介電層330。此閘極介電層330同時覆蓋深溝槽320裸露於外之側壁。接下來，如第4C圖所示，形成一T型閘極多晶矽結構344於深溝槽320內。此T型閘極多晶矽結構344之垂直部分係填入深溝槽320之上部份，其水平部分則是位於磊晶層310上。
接下來，利用T型閘極多晶矽結構344為遮罩，以離子植入方式植入P型摻雜於磊晶層310內，並施以一熱擴散(drive-in)步驟，以形成P型本體350於相鄰二個閘極多晶矽結構344之間。此熱擴散步驟同時會使各個重摻雜多晶矽層3421,3422,…3426內的摻雜向外擴散，而形成多個重摻雜子區(sub-region)3601,3602,…3606，分別環繞相對應之重摻雜多晶矽層3421,3422,…3426。並且，各個重摻雜子區3601,3602,…3606係互相連接。至於本實施例之源極摻雜區與接觸窗之製作方式，與本發明第一實施例並無不同，在此不予贅述。
值得注意的是，在本實施例中，重摻雜多晶矽層3421,3422,…3426具有高濃度之P型摻雜，因而在周圍形成P型重摻雜子區3601,3602,…3606。在本實施例中，這些P型重摻雜子區3601,3602,…3606係互相連接，而構成一完整的P型重摻雜區360。不過，本發明並不限於此，這些P型重摻雜子區3601,3602,…3606亦可以互相分離，只要這些P型重摻雜子區3601,3602,…3606的電位可以受到閘極多晶矽結構344之電位的影響即可。此外，此P型重摻雜區360與P型本體350係保持一預設距離。透過此P型井區與P型本體350間所產生之空乏區，可以有效提升電晶體元件的耐壓。
第5A至5C圖顯示本發明之功率半導體之製造方法之第五實施例。本實施例亦是以一高壓功率半導體結構為例。第5A圖之製作步驟係承接第4B圖之步驟。如圖中所示，在形成閘極介電層330後，形成閘極多晶矽結構445於磊晶層310之上表面。此閘極多晶矽結構445可利用典型之多晶矽微影蝕刻技術製作。隨後，直接利用此閘極多晶矽結構445為遮罩，以離子植入方式植入P型摻雜於磊晶層310內，以形成P型本體450環繞溝槽320之上部份的周圍。然後，依然是利用閘極多晶矽結構445為遮罩，不過，改為植入N型摻雜於磊晶層310內，以形成N型源極摻雜區470與P型本體450內。
接下來，如第5B圖所示，形成一層間介電層480覆蓋閘極多晶矽結構445，同時在P型本體450之上方定義出接觸窗482的位置。如圖中所示，此接觸窗482係大致對準溝槽320，並且，接觸窗的寬度係大於溝槽320之寬度。然後，在溝槽320之上部分內填入一多晶矽結構444。接下來，如第5C圖所示，透過接觸窗482向下蝕刻磊晶層310，使位於N型源極摻雜區470下方之P型本體450裸露出來。隨後，植入P型摻雜於接觸窗482的底部，以形成一P型重摻雜區485。最後，沉積一源極金屬層490於層間介電層480上，並且透過接觸窗485電性連接源極摻雜區470與多晶矽結構444。
在第四實施例中，閘極多晶矽結構344係位於溝槽320內，並且，閘極多晶矽結構344係對準由多個重摻雜多晶矽層3421,3422,…3426所構成之重摻雜多晶矽結構。相較之下，本實施例之閘極多晶矽結構445則是形成於磊晶層310之上表面，並且，本實施例之重摻雜多晶矽結構係對準P型本體450，形成於重摻雜多晶矽結構周圍的P型井區460係連接P型本體450。本實施例係透過在相鄰二個P型井區460間所產生之空乏區，以提升電晶體元件的耐壓。
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。另外本發明的任一實施例或申請專利範圍不須達成本發明所揭露之全部目的或優點或特點。此外，摘要部分和標題僅是用來輔助專利文件搜尋之用，並非用來限制本發明之權利範圍。
100‧‧‧基板
110‧‧‧磊晶層
120‧‧‧溝槽
142‧‧‧重摻雜多晶矽結構
132‧‧‧底部介電層
134‧‧‧側壁介電層
144‧‧‧閘極多晶矽結構
150‧‧‧本體
160‧‧‧重摻雜區
175‧‧‧光阻圖案
170‧‧‧源極摻雜區
180‧‧‧層間介電層
182‧‧‧接觸窗
185‧‧‧重摻雜區
190‧‧‧源極金屬層
125‧‧‧硬質罩幕層
236‧‧‧第一介電層
260‧‧‧重摻雜區
310‧‧‧磊晶層
320‧‧‧深溝槽
3411,3412,3413,3414,3415,3416‧‧‧介電層
3421,3422,3423,3424,3425,3426‧‧‧重摻雜多晶矽層
330‧‧‧閘極介電層
344‧‧‧閘極多晶矽結構
350‧‧‧本體
3601,3602,3603,3604,3605,3606‧‧‧重摻雜子區
360‧‧‧重摻雜區
445‧‧‧閘極多晶矽結構
444‧‧‧多晶矽結構
450‧‧‧本體
470‧‧‧源極摻雜區
480‧‧‧層間介電層
482‧‧‧接觸窗
485‧‧‧重摻雜區
第1A至1G圖顯示本發明之溝槽式功率半導體之製造方法之第一實施例。
第2圖顯示本發明溝槽式功率半導體之製造方法之第二實施例。
第3A與3B圖顯示本發明溝槽式功率半導體之製造方法之第三實施例。
第4A至4C圖顯示本發明之功率半導體之製造方法之第四實施例。
第5A與5C圖顯示本發明之功率半導體之製造方法之第五實施例。
100．．．基板
110．．．磊晶層
142．．．重摻雜多晶矽結構
132．．．底部介電層
134．．．側壁介電層
144．．．閘極多晶矽結構
150．．．本體
160．．．重摻雜區
170．．．源極摻雜區
180．．．層間介電層
182．．．接觸窗
185．．．重摻雜區
190．．．源極金屬層

Claims (17)

  1. 一種功率半導體，包括：一第一導電型之基材；一溝槽，形成於該基材內；一重摻雜多晶矽結構，位於該溝槽之一下部份，並且，該重摻雜多晶矽結構之至少一側邊係直接接觸該基材；一導電結構，位於該溝槽之一上部份；一閘極介電層，位於該導電結構與該重摻雜多晶矽結構之間；以及一第二導電型之本體，位於該基材內；其中，該重摻雜多晶矽結構內之摻雜係至少透過該重摻雜多晶矽結構之該側邊向外擴散以形成一重摻雜區。
  2. 如申請專利範圍第1項之功率半導體，更包括一介電層，位於該溝槽之一底面，該重摻雜多晶矽結構係位於該介電層上方。
  3. 如申請專利範圍第1項之功率半導體，其中，該重摻雜多晶矽結構係該為第一導電型。
  4. 如申請專利範圍第1項之功率半導體，其中，該重摻雜多晶矽結構係該為第二導電型。
  5. 如申請專利範圍第4項之功率半導體，其中，該重摻雜區係連接該本體。
  6. 如申請專利範圍第1項之功率半導體，其中，該重摻雜多晶矽結構係由複數個重摻雜多晶矽層堆疊而成，並且，該些重摻雜多晶矽層係透過至少一介電層區分隔開來。
  7. 如申請專利範圍第6項之功率半導體，其中，該重摻雜區係由多個重摻雜子區所構成，各該重摻雜子區分別對應於該些重摻雜多晶矽層，並且，至少部分該些重摻雜子區係互相連接。
  8. 如申請專利範圍第1項之功率半導體，其中，該導電結構係一閘極多晶矽結構。
  9. 如申請專利範圍第1項之功率半導體，其中，該導電結構係電性連接至一源極。
  10. 一種功率半導體之製造方法，包括：提供一第一導電型之基材；形成一溝槽於該基材內；形成一重摻雜多晶矽結構於該溝槽之一下部份內，該重摻雜多晶矽結構之至少一側邊係直接接觸該基材；形成一閘極介電層至少覆蓋該重摻雜多晶矽結構之一上表面；形成一導電結構於該溝槽之一上部份；以及施以一熱擴散製程，使該重摻雜多晶矽結構之摻雜向外擴散以形成一重摻雜區至少環繞該重摻雜多晶矽結構之該側邊。
  11. 如申請專利範圍第10項之功率半導體之製造方法，在形成該重摻雜多晶矽結構之步驟前，更包括形成一介電層於該溝槽之一底面。
  12. 如申請專利範圍第10項之功率半導體之製造方法，其中，該熱擴散製程同時用以形成一第二導電型之本體。
  13. 如申請專利範圍第10項之功率半導體之製造方法，其中，該重摻雜多晶矽結構係為該第一導電型。
  14. 如申請專利範圍第10項之功率半導體之製造方法，其中，該重摻雜多晶矽結構係為一第二導電型。
  15. 如申請專利範圍第14項之功率半導體之製造方法，其中，形成該重摻雜多晶矽結構之步驟包括：形成一第一重摻雜多晶矽層於該溝槽內；形成一第一介電層覆蓋該第一重摻雜多晶矽層；以及形成一第二重摻雜多晶矽層於該第一介電層上方。
  16. 如申請專利範圍第10項之功率半導體之製造方法，其中，該導電結構係一閘極多晶矽結構。
  17. 如申請專利範圍第10項之功率半導體之製造方法，更包括，沉積一源極金屬層電性連接該導電結構。
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US20080150020A1 (en) * 2003-05-20 2008-06-26 Ashok Challa Trenched Shield Gate Power Semiconductor Devices and Methods of Manufacture
US20090189218A1 (en) * 2007-12-14 2009-07-30 James Pan Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings

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