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TWI496254B - 嵌埋半導體元件之封裝結構及其製法 - Google Patents

嵌埋半導體元件之封裝結構及其製法 Download PDF

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TWI496254B
TWI496254B TW099137412A TW99137412A TWI496254B TW I496254 B TWI496254 B TW I496254B TW 099137412 A TW099137412 A TW 099137412A TW 99137412 A TW99137412 A TW 99137412A TW I496254 B TWI496254 B TW I496254B
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layer
insulating protective
protective layer
wafer
disposed
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TW099137412A
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TW201220446A (en
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Shih Ping Hsu
I Ta Tsai
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Unimicron Technology Corp
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Priority to TW099137412A priority Critical patent/TWI496254B/zh
Priority to US13/160,911 priority patent/US20120104598A1/en
Publication of TW201220446A publication Critical patent/TW201220446A/zh
Priority to US13/865,220 priority patent/US8580608B2/en
Priority to US14/046,000 priority patent/US9024422B2/en
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Publication of TWI496254B publication Critical patent/TWI496254B/zh

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
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Description

嵌埋半導體元件之封裝結構及其製法
　　本發明係有關一種封裝結構及其製法，尤指一種嵌埋半導體元件之封裝結構及其製法。
　　隨著電子產業的蓬勃發展，電子產品亦朝著輕、薄、短、小、高積集度、多功能化方向發展。而為滿足封裝結構高積集度(Integration)以及微型化(Miniaturization)的封裝需求，封裝基版除了導入球柵陣列(BGA)的設計，封裝形式逐漸由打線式(Wire Bonding)封裝或覆晶式(Flip Chip, FC)封裝進展到直接在一封裝基板(packaging substrate) 中嵌埋並電性整合一例如具有積體電路之半導體晶片，此種封裝件能縮減整體半導體裝置之體積並提昇電性功能。
　　另一方面，單一晶片之封裝形式逐漸演進到3D封裝和模組化封裝形態，以達到多種晶片之系統化封裝(System in package, SIP) ，遂成為一種封裝的趨勢。
　　請參閱第1A圖，係為習知以覆晶方式之無核心板（coreless）封裝結構的剖視示意圖。如第1A圖所示，習知封裝結構係包括：基板10、防焊層12、晶片14、以及底膠16。
　　所述之基板10具有相對之第一表面10a與第二表面10b，該基板10係由至少一介電層100、設於該介電層100上之線路層101、與複數設於該介電層100中並電性連接該線路層101之導電盲孔102所構成，且該線路層101於該第一表面10a上具有複數外露之第一電性接觸墊103，而於該第二表面10b上則具有複數外露之第二電性接觸墊104。
　　所述之防焊層12設於該基板10之第一及第二表面10a,10b上，且該防焊層12具有複數開孔120，以令各該第一及第二電性接觸墊103,104對應外露於各該開孔120中，且外露之第二電性接觸墊104俾供外接其他電子裝置。
　　所述之晶片14以覆晶方式設於該基板10之第一表面10a上之防焊層12上，該晶片14具有作用面14a及非作用面14b，於該作用面14a上具有複數電極墊140，以令各該電極墊140藉由焊錫凸塊15對應電性連接外露之各該第一電性接觸墊103。
　　所述之底膠16設於該基板10之第一表面10a上之防焊層12與該晶片14之作用面14a之間，以包覆該焊錫凸塊15。
　　惟，習知如第1A圖之封裝結構係僅於該基板10之其中一表面（第一表面10a）上接置晶片14，並於該基板10之其中一表面（第一表面10a）及晶片14上形成底膠16，使該基板10的兩表面成為不對稱之結構，致使該基板10之外圍會因應力不均而變形，導致整體結構發生翹曲（warpage）現象，因而影響電性連接之品質，進而造成整體封裝結構的可靠度不佳，且產品良率下降等問題。
　　再者，如第1A圖之封裝結構因缺乏硬質之核心板體作支撐，導致強度不足，因而整體結構容易發生翹曲現象，進而影響電性連接之品質，且不利於形成該底膠16之製程
　　請再參閱第1B圖，係為另一態樣之習知嵌埋有半導體元件之封裝結構的剖視示意圖。如第1B圖所示，習知封裝結構係包括：一具有相對第一及第二表面19a,19b及貫穿該第一及第二表面19a,19b之開口190之核心板19、設於該開口190中之晶片11、設於該核心板19之第一及第二表面19a,19b與晶片11上之增層結構17、以及設於該增層結構17上之防焊層18。
　　所述之晶片11具有作用面11a及非作用面11b，於該作用面11a上具有複數電極墊110，且藉由黏著材191填充於該開口190，以固定該晶片11於該開口190中。
　　所述之增層結構17具有至少一介電層170、設於該介電層170上之線路層171、及複數設於該介電層170中並電性連接該電極墊110與線路層171之導電盲孔172。
　　所述之防焊層18具有複數開孔180，以令該線路層171之部分表面外露於各該開孔180中，俾供作為電性接觸墊以外接其他電子裝置。
　　習知如第1B圖之封裝結構需於該核心板19上以雷射方式或銑刀製作出貫穿之開口190，但該核心板19之厚度若大於0.3㎜，則無法使用雷射開孔之方式。另外，利用銑刀之方式雖無厚度之限制，但卻存在有製程速度慢及精度不佳等問題。
　　因此，如何提出一種封裝結構，以避免習知封裝結構之種種問題，實以成爲目前業界亟待克服之課題。
　　鑑於上述習知技術之種種缺失，本發明之主要目的係提供一種能避免發生翹曲之嵌埋半導體元件之封裝結構及其製法。
　　為達上述目的及其他目的，本發明揭露一種嵌埋半導體元件之封裝結構，係包括：晶片，係具有相對之作用面與非作用面，該作用面上具有複數電極墊；第一絕緣保護層，係具有對應設置該晶片之置晶區，以令該晶片之作用面設於該第一絕緣保護層之置晶區上；連接柱，係設於該第一絕緣保護層中且對應各該電極墊之位置，並透過焊錫凸塊以電性連接該晶片之電極墊，使該連接柱及焊錫凸塊形成複數接點；封膠層，係設於該第一絕緣保護層與晶片同側之表面上，並包覆該晶片，且填入各該接點周圍之空隙中；以及增層結構，係設於該第一絕緣保護層另一側之表面及各該連接柱上。
　　本發明復提供一種嵌埋半導體元件之封裝結構之製法，係包括：提供一具有相對兩表面之承載板，該承載板具有核心層、設於該核心層之相對兩表面上之第一金屬層、設於各該第一金屬層上之剝離層、及設於各該剝離層上之第二金屬層；施以圖案化製程，俾於該第二金屬層上形成複數連接柱，且外露部分之第二金屬層表面；於該第二金屬層外露之表面上形成第一絕緣保護層，且令各該連接柱外露於該第一絕緣保護層；於該些連接柱上接置至少一晶片，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且各該電極墊藉由焊錫凸塊以覆晶方式電性連接各該連接柱；於該第一絕緣保護層及晶片上形成封膠層；移除該承載板；以及於該第一絕緣保護層及該些連接柱上形成增層結構。
　　前述之製法中，當形成該第一絕緣保護層時，於該第一絕緣保護層上形成複數第一開孔，以令各該連接柱對應外露於各該第一開孔中。
　　前述之封裝結構及其製法中，該晶片係為主動元件或被動元件。
　　前述之封裝結構及其製法中，該連接柱之高度係齊平、高於或低於該第一絕緣保護層之頂面高度。
　　前述之封裝結構及其製法中，該增層結構係包括至少一介電層、設於該介電層上之線路層、及複數設於該介電層中並電性連接該線路層之導電盲孔，且部分之線路層係設於該第一絕緣保護層及該些連接柱上，以電性連接該些連接柱。
　　又依上所述，復包括於該增層結構上形成第二絕緣保護層，且令部份之線路層外露於該第二絕緣保護層，俾供作為電性接觸墊。另包括於各該電性接觸墊上形成銲錫球。
　　由上可知，本發明之嵌埋半導體元件之封裝結構及其製法，藉由先將晶片嵌埋於封膠層，於後續之形成增層結構製程中，可藉由該封膠層之抗彎曲性，以避免該增層結構產生翹曲。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　請參閱第2A至2F圖，係為本發明所揭露之一種嵌埋半導體元件之封裝結構之製法。
　　如第2A圖所示，提供一具有相對兩表面之承載板2a，該承載板2a係為整版面，且具有核心層20、設於該核心層20之相對兩表面20a上之第一金屬層21、設於各該第一金屬層21上之剝離層22、及設於各該剝離層22上之第二金屬層23。
　　所述之核心層20可為例如BT（Bismaleimide Triazine）之有機聚合材料，亦可為兩相對表面全面結合有例如為預浸材（prepreg）之介電材之銅箔基板（CCL）(未表示於圖式中)。
　　如第2B圖所示，施以圖案化製程，俾於該第二金屬層23上形成複數連接柱24，且外露部分之第二金屬層23上表面23a。又形成該連接柱24之材質係為導電材，例如：銅。
　　如第2C圖所示，於該第二金屬層23外露之表面23a上形成第一絕緣保護層25，且令各該連接柱24外露於該第一絕緣保護層25。又該連接柱24齊平於該第一絕緣保護層25之頂面高度。
　　再者，亦可如第2C’圖所示，各該連接柱24’高於該第一絕緣保護層25之頂面高度。或如第2C”圖所示，於該第一絕緣保護層25”上形成複數第一開孔250，以令各該連接柱24”對應外露於各該第一開孔250中，使各該連接柱24”低於該第一絕緣保護層25之頂面高度。
　　如第2D圖所示，係以第2C圖所示之結構作接續製程。於該些連接柱24上接置至少一晶片26,26’，該晶片26,26’具有相對之作用面26a與非作用面26b，該作用面26a上具有複數電極墊260，且各該電極墊260藉由焊錫凸塊27以覆晶方式電性連接各該連接柱24。該晶片26,26’可為主動元件（如圖中左側之晶片26’）或整合式被動元件（Integrated Passive Device, IPD，如圖中右側之晶片26）。
　　接著，於該第一絕緣保護層25及晶片26,26’上形成封膠層28，且填入該些焊錫凸塊27之間的空隙中。其中，形成該封膠層28之材料係可為介電材或封裝膠材。
　　如第2E圖所示，移除該承載板2a，以露出該第一絕緣保護層25及該些連接柱24。其中，係藉由該剝離層22先移除該核心層20及第一金屬層21，以露出該第二金屬層23；再蝕刻移除該第一絕緣保護層25上之第二金屬層23。亦可保留該第一絕緣保護層25上之第二金屬層23，以供後續製程製作線路之用。
　　本發明係於該承載板2a之相對兩表面上接置晶片26,26’，並於該承載板2a之相對兩表面及晶片26,26’上形成封膠層28，使該承載板2a的兩表面上成為對稱結構，故該承載板2a之外圍不會因應力不均而變形，因而有效避免整體結構發生翹曲（warpage）現象。
　　如第2F圖所示，於該第一絕緣保護層25及該些連接柱24上形成增層結構29。該增層結構29係包括至少一介電層290、設於該介電層290上之線路層291、及複數設於該介電層290中並電性連接該線路層291之導電盲孔292，且該線路層291係具有設於該第一絕緣保護層25及該些連接柱24上之連接墊2910，以電性連接該些連接柱24與導電盲孔292。接著，於該增層結構29上形成第二絕緣保護層30，且該第二絕緣保護層30中形成複數第二開孔300，以令部份之線路層291外露於該第二開孔300，俾作為電性接觸墊293，以形成銲錫球31。最後，進行切單製程。
　　再者，該第一絕緣保護層25及該些連接柱24上之線路層291係可利用該第二金屬層23供作導電層，以圖案化電鍍法(Patterning plating)製作該線路層291。若欲製作更細間距之線路，則於該第一絕緣保護層25及該些連接柱24上製作線路層291前，可先蝕刻移除該第二金屬層23，以重新形成導電層之半加成法(Semi-additive plating, SAP) 製作該線路層291。
　　又，於其他實施例中，若以第2C’或2C”圖所示之結構作接續製程，將可形成如第2F’或2F”圖所示之結構。
　　另外，該第一絕緣保護層25與第二絕緣保護層30可為防焊層。
　　本發明藉由該封膠層28之抗彎曲性，以避免該增層結構29產生翹曲，故該晶片26,26’之電極墊260與該連接墊2910之對位不會產生走位，因而可維持電性連接之品質，有效提升整體封裝結構的可靠度及產品良率。
　　本發明復提供一種嵌埋半導體元件之封裝結構，係包括：晶片26,26’，係具有相對之作用面26a與非作用面26b，該作用面26a上具有複數電極墊260；第一絕緣保護層25,25”，係具有對應設置該晶片26,26’之置晶區A，以令該晶片26,26’之作用面26a設於該第一絕緣保護層25之置晶區A上；連接柱24,24’,24”，係設於該第一絕緣保護層25,25”中且對應各該電極墊260之位置，並透過焊錫凸塊27以電性連接該電極墊260，使該連接柱24,24’,24”及焊錫凸塊27形成複數接點；封膠層28，係設於該第一絕緣保護層25與晶片26,26’同側之表面上，並包覆該晶片26,26’，且填入各該接點周圍之空隙中；以及增層結構29，　　係設於該第一絕緣保護層25另一側之表面及各該連接柱24,24’,24”上。
　　所述之晶片26,26’係為主動元件或被動元件。
　　所述之連接柱24,24’,24”之高度係齊平、高於或低於該第一絕緣保護層25,25”之端面位置。
　　所述之增層結構29係包括至少一介電層290、設於該介電層290上之線路層291、及複數設於該介電層290中並電性連接該線路層291之導電盲孔292，且部分之線路層291（連接墊2910）係設於該第一絕緣保護層25及該些連接柱24,24’,24”上，以電性連接該些連接柱24,24’,24”。
　　所述之封裝結構復包括第二絕緣保護層30，係設於該增層結構29上，且該第二絕緣保護層30中形成複數第二開孔300，以令部份之線路層291外露於該些第二開孔300，俾供作為電性接觸墊293，以設置銲錫球31。
　　綜上所述，本發明之嵌埋半導體元件之封裝結構及其製法，係於該承載板之相對兩側上接置晶片及形成封膠層，使該承載板之兩側上成為對稱結構，以避免整體結構發生翹曲現象。
　　再者，本發明藉由該封膠層之抗彎曲性，可避免該增層結構產生翹曲，故該晶片之電極墊與該線路層之間可維持電性連接之品質，以提升整體封裝結構的可靠度及產品良率。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．基板
10a,19a．．．第一表面
10b,19b．．．第二表面
100,170,290．．．介電層
101,171,291．．．線路層
102,172,292．．．導電盲孔
103．．．第一電性接觸墊
104．．．第二電性接觸墊
11,14,26,26’．．．晶片
11a,14a,26a．．．作用面
11b,14b,26b．．．非作用面
110,140,260．．．電極墊
12,18．．．防焊層
120,180．．．開孔
15,27．．．焊錫凸塊
16．．．底膠
17,29．．．增層結構
19．．．核心板
190．．．開口
191．．．黏著材
2a．．．承載板
20．．．核心層
20a,23a．．．表面
21．．．第一金屬層
22．．．剝離層
23．．．第二金屬層
24,24’,24”連接柱
25,25”．．．第一絕緣保護層
250．．．第一開孔
28．．．封膠層
2910．．．連接墊
293．．．電性接觸墊
30．．．第二絕緣保護層
300．．．第二開孔
31．．．銲錫球
A．．．置晶區
　　第1A圖係為習知半導體覆晶封裝結構之剖視示意圖；
　　第1B圖係為習知嵌埋半導體元件之封裝結構之剖視示意圖；以及
　　第2A至2F圖係為本發明嵌埋半導體元件之封裝結構之製法剖視示意圖；其中，第2C’及2C”圖係分別為第2C圖之不同實施例，第2F’及2F”圖係分別為第2F圖之不同實施例。
24．．．連接柱
25．．．第一絕緣保護層
26 26’．．．晶片
26a．．．作用面
26b．．．非作用面
260．．．電極墊
27．．．焊錫凸塊
28．．．封膠層
29．．．增層結構
290．．．介電層
291．．．線路層
2910．．．連接墊
292．．．導電盲孔
293．．．電性接觸墊
30．．．第二絕緣保護層
300．．．第二開孔
31．．．銲錫球
A．．．置晶區

Claims (10)

  1. 一種嵌埋半導體元件之封裝結構，係包括：晶片，係具有相對之作用面與非作用面，該作用面上具有複數電極墊；第一絕緣保護層，係具有對應設置該晶片之置晶區，以令該晶片之作用面設於該第一絕緣保護層之置晶區上；連接柱，係設於該第一絕緣保護層中且對應各該電極墊之位置，並透過焊錫凸塊以電性連接該晶片之電極墊，使該連接柱及焊錫凸塊形成複數接點，其中，該連接柱之下端部係齊平於該第一絕緣保護層之下表面；封膠層，係設於該第一絕緣保護層與晶片同側之表面上，並包覆該晶片，且填入各該接點周圍之空隙中；以及增層結構，係設於該第一絕緣保護層另一側之表面及各該連接柱上。
  2. 如申請專利範圍第1項所述之嵌埋半導體元件之封裝結構，其中，該晶片係為主動元件或被動元件。
  3. 如申請專利範圍第1項所述之嵌埋半導體元件之封裝結構，其中，該連接柱之高度係齊平、高於或低於該第一絕緣保護層之頂面高度。
  4. 如申請專利範圍第1項所述之嵌埋半導體元件之封裝結構，其中，該增層結構係包括至少一介電層、設於該介電層上之線路層、及複數設於該介電層中並電性連接該線路層之導電盲孔，且部分之線路層係設於該第一絕緣保護層及該些連接柱上，以電性連接該些連接柱。
  5. 如申請專利範圍第4項所述之嵌埋半導體元件之封裝結構，復包括第二絕緣保護層，係設於該增層結構上，且該 第二絕緣保護層中形成複數第二開孔，以令部份之線路層外露於該些第二開孔，俾供作為電性接觸墊。
  6. 如申請專利範圍第5項所述之嵌埋半導體元件之封裝結構，復包括銲錫球，係設於各該第二開孔中之電性接觸墊上。
  7. 一種嵌埋半導體元件之封裝結構之製法，係包括：提供一具有相對兩表面之承載板，該承載板具有核心層、設於該核心層之相對兩表面上之第一金屬層、設於各該第一金屬層上之剝離層、及設於各該剝離層上之第二金屬層；施以圖案化製程，俾於該第二金屬層上形成複數連接柱，且外露部分之第二金屬層表面；於該第二金屬層外露之表面上形成第一絕緣保護層，且令各該連接柱外露於該第一絕緣保護層；於該些連接柱上接置至少一晶片，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且各該電極墊藉由焊錫凸塊以覆晶方式電性連接各該連接柱；於該第一絕緣保護層及晶片上形成封膠層，且令該承載板之相對兩表面上之連接柱、第一絕緣保護層、晶片及封膠層呈對稱結構；藉由該剝離層移除該承載板之核心層及第一金屬層；以及於該第一絕緣保護層及該些連接柱上形成增層結構。
  8. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法，其中，該連接柱齊平、高於或低於該第一絕緣保護層之頂面高度。
  9. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法，其中，該晶片係為主動元件或被動元件。
  10. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法，其中，該增層結構係包括至少一介電層、設於該介電層上之線路層、及複數設於該介電層中並電性連接該線路層之導電盲孔，且部分之線路層係設於該第一絕緣保護層及該些連接柱上，以電性連接該些連接柱。
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