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TWI488279B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI488279B
TWI488279B TW100130452A TW100130452A TWI488279B TW I488279 B TWI488279 B TW I488279B TW 100130452 A TW100130452 A TW 100130452A TW 100130452 A TW100130452 A TW 100130452A TW I488279 B TWI488279 B TW I488279B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
passive component
layer
metal
protective layer
Prior art date
Application number
TW100130452A
Other languages
English (en)
Other versions
TW201230282A (en
Inventor
Kuei Ti Chan
Tzu Hung Lin
Ching Liou Huang
Original Assignee
Mediatek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Inc filed Critical Mediatek Inc
Publication of TW201230282A publication Critical patent/TW201230282A/zh
Application granted granted Critical
Publication of TWI488279B publication Critical patent/TWI488279B/zh

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
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Description

半導體封裝
本發明係有關於一種半導體封裝，特別係有關於一種半導體封裝的被動元件。
對習知的覆晶封裝(flip chip package)而言，電感的要求為低電阻，使其可以達到高品質因數(Q factor)。電感的品質因數係定義為其處於某一特定頻率時，其的電感電抗和電阻之間的比例，且電感的品質因數係用來衡量電感的效能。電感的品質因數愈高，愈接近無損耗的理想電感。
習知覆晶封裝的製程通常使用位於晶片的內連線結構之額外金屬層來改善電感的品質因數。然而，上述額外金屬層會增加製程成本，且會對產率對有不良的影響。
因此，在此技術領域中，有需要一種高品質因數的電感，以滿足上述需求且克服習知技術的缺點。
有鑑於此，本發明一實施例係提供一種半導體封裝，上述半導體封裝包括一基板；一第一保護層，設置於上述基板上；一第二保護層，設置於上述第一保護層上；一凸塊下金屬層，設置於上述第一保護層與上述第二保護層上；一被動元件，設置於上述凸塊下金屬層上；一額外凸塊下金屬層，設置於上述基板上，上述額外凸塊下金屬層與上述凸塊下金屬層隔絕；一導電凸塊，設置於上述額外 凸塊下金屬層上；以及一導電柱狀物，位於上述額外凸塊下金屬層和上述導電凸塊之間，其中上述導電柱狀物和上述被動元件位於相同的層。
本發明另一實施例係提供一種半導體封裝，上述半導體封裝包括一第一保護層，設置於一基板上；一第二保護層，設置於上述第一保護層上；一凸塊下金屬層，設置於上述第一保護層與上述第二保護層上；一被動元件，設置於上述凸塊下金屬層上；一焊料，覆蓋上述被動元件；一額外凸塊下金屬層，設置於上述基板上，上述額外凸塊下金屬層與上述凸塊下金屬層隔絕；一導電凸塊，設置於上述額外凸塊下金屬層上；以及一導電柱狀物，位於上述額外凸塊下金屬層和上述導電凸塊之間，其中上述導電柱狀物和上述被動元件位於相同的層。
本發明實施例之半導體封裝可降低製程成本，且上述被動元件具有低電阻和高品質因數。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。
第1至9圖為本發明實施例之半導體封裝500的製 程剖面圖。本發明實施例之半導體封裝500為一覆晶封裝(flip chip package)。本發明實施例之半導體封裝500可包括與一凸塊結構的一導電柱狀物(conductive pillar)整合的一被動元件(passive device)，而導電柱狀物係設置於一金屬墊和一導電凸塊之間，以使上述被動元件的厚度遠大於習知的設置於內連線結構中且沒有額外金屬層的被動元件的厚度。如果上述被動元件為一電感，則可具有低電阻和高品質因數(quality factor(Q factor))。
請參考第1圖，提供一半導體晶片300。在本發明一實施例中，半導體晶片300可包括一基板200，其具有一半導體元件202設置於其上。一內連線結構220，設置於基板200和半導體元件202上。在本發明一實施例中，內連線結構220可提供半導體元件202的電性傳輸路徑。在本發明一實施例中，設置於基板200上的內連線結構220可包括複數個金屬層、與金屬層交錯堆疊的複數個介電層，和穿過介電層的複數個介層孔插塞204、210、218。舉例來說，內連線結構220的金屬層可包括金屬層208、214和金屬墊224a、224b。另外，金屬墊224a、224b係屬於內連線結構220的金屬層中的最頂層金屬層(uppermost metal layer)。在本實施例中，金屬墊224a係用於傳輸半導體晶片300的輸入/輸出(I/O)訊號、接地(ground)訊號或電源(power)訊號，而金屬墊224b用於傳輸電源訊號至後續形成於其上的被動元件。舉例來說，內連線結構220的介電層可包括介電層206、212、216和保護層(passivation layer)222。另外，保護層222係屬於內連線結構220的介 電層中的最頂層介電層(uppermost dielectric layer)。
接著，請再參考第1圖，於半導體晶片300上進行一凸塊製程(bump process)。利用一沉積方式，順應性形成一保護層226，覆蓋金屬墊224a、224b。在本發明一實施例中，保護層226可包括氧化物、氮化物或氮氧化物。接著，圖案化保護層226，以分別於金屬墊224a、224b上形成開口227a、227b，以使部分金屬墊224a、224b分別從開口227a、227b暴露出來。
接著，請再參考第1圖，可利用一塗佈方式，全面性形成一保護層228。在本發明一實施例中，保護層228可包括聚醯亞胺(polyimide)，當半導體晶片300遭受不同種類的環境壓力時，保護層228可提供可靠的絕緣。
接著，請參考第2圖，利用包括微影和顯影製程的一圖案化製程，移除部分保護層228，以分別於開口227a、227b上形成開口230a、230b。因此，部分金屬墊224a、224b分別從開口230a、230b暴露出來。
接著，請參考第3圖，對第2圖所示的保護層228的進行一硬化(curing)製程，以固化保護層228。進行硬化製程之後，保護層228的高度會下降，會因為保護層228的收縮以形成一硬化保護層228a。
接著，請參考第4圖，可利用例如濺鍍或電鍍法的一沉積方式，於硬化保護層228a上形成一凸塊下金屬層(under bump metallurgy(UBM)layer)232。同時，凸塊下金屬層232形成開口230a、230b的側壁以及底面。並且，凸塊下金屬層232係延伸至硬化保護層228a的一頂面上 方。在本發明一實施例中，凸塊下金屬層232由一鈦層和位於鈦層上的一銅層構成。
第5至8圖係顯示位於凸塊下金屬層232上的一被動元件和一導電柱狀物的形成方式。接著，請參考第5圖，於凸塊下金屬層232上全面性堆疊一乾膜光阻234。在本發明其他實施例中，也可使用液態光阻來代替乾膜光阻234。接著，利用包括曝光和顯影步驟的微影製程圖案化乾膜光阻234，以於金屬墊224a、224b的上方分別形成開口236a、236b，以確定出後續被動元件和導電柱狀物的形成位置。在本發明一實施例中，乾膜光阻234的厚度可介於20μm至40μm之間。
接著，請參考第6圖，可利用一電鍍方式，分別於開口236a、236b的底面上形成導電緩衝層237a、237b。在本發明一實施例中，導電緩衝層237a、237b可做為形成於其上的被動元件和導電柱狀物的一種晶層(seed layer)、一黏著層和一阻障層。在本發明一實施例中，導電緩衝層237a、237b可包括鎳。然後，分別於導電緩衝層237a、237b上形成一導電柱狀物238a和一被動元件238b，並填充開口236a、236b。在本發明一實施例中，導電柱狀物238a可用做為後續導電凸塊的焊點(solder joint)形成於其上，而導電凸塊係用於傳輸半導體晶片300的輸入/輸出(I/O)訊號、接地(ground)訊號或電源(power)訊號。因此，導電柱狀物238a可幫助增加凸塊結構的機械強度。在本發明一實施例中，導電柱狀物238a可由銅形成，以防止在後續回焊製程(solder re-flow process)中變形。例如一電感、一變 壓器、一繞線或一天線等的半導體封裝之一被動元件238b可與導電柱狀物238a形成於同一層。在本發明一實施例中，被動元件238b可為厚度厚(由乾膜光阻234定義)和強壯的結構，特別是用於形成一電感時。
接著，請參考第7圖，可利用例如使用適當蝕刻劑的濕蝕刻製程之一剝除製程(stripping process)，移除乾膜光阻234。進行剝除製程之後，未被導電柱狀物238a和被動元件238b覆蓋的凸塊下金屬層232係暴露出來。
接著，請參考第8圖，進行一非等向性蝕刻製程(anisotropic etching process)，以移除未被導電柱狀物238a和被動元件238b覆蓋的凸塊下金屬層232，因此形成分別位於導電柱狀物238a和被動元件238b下方的凸塊下金屬層圖案232a、232b。在進行如第8圖所示的製程之後，係完成本發明實施例之半導體封裝的被動元件238b，其中凸塊下金屬層圖案232b與被動元件238b完全重疊。注意金屬墊224b僅用於傳輸電源訊號至形成於其上的被動元件238b，因此金屬墊224b係與被動元件238b部分重疊但並非完全重疊。
接著，請參考第9圖，可利用一電鍍方式，於導電柱狀物238a上形成一導電緩衝層240。在本發明一實施例中，導電緩衝層240為選擇性的元件，其可做為形成於其上的導電凸塊的一種晶層(seed layer)、一黏著層和一阻障層。在本發明一實施例中，導電緩衝層240可包括鎳。
可利用搭配圖案化光阻層的電鍍製程或一網版印刷製程，於導電緩衝層240上形成一焊料。接著，移除上述 圖案化光阻層，且進行一回焊製程，以於導電柱狀物238a上形成導電凸塊242。在本發明一實施例中，導電凸塊242係用於傳輸半導體晶片300的輸入/輸出(I/O)訊號、接地(ground)訊號或電源(power)訊號。在本發明一實施例中，導電柱狀物238a、導電凸塊242和兩者之間的導電緩衝層240(選擇性元件)係共同構成一凸塊結構250。在本發明其他實施例中，可於被動元件238b上額外形成一導電緩衝層或一焊料，其中導電凸塊242和焊料可位於同一層。經過上述製程之後，係完成本發明實施例之半導體封裝500。
另外，半導體封裝500可與如第9圖所示的一印刷電路板248接合。在本發明一實施例中，一底部填充材料(underfill material)244可選擇性填滿之半導體封裝500和印刷電路板248之間的空間。注意半導體封裝500的導電凸塊242接合至印刷電路板248的一金屬墊246，而印刷電路板248係設置於半導體封裝500的導電凸塊242和被動元件的上方。
本發明實施例之半導體封裝500係提供一被動元件238b，其與凸塊結構250設置在相同層別(level)，上述凸塊結構250係介於半導體封裝500的金屬墊224b和印刷電路板248的金屬墊246之間。如第9圖所示，例如為電感的被動元件238b具有兩個末端，其中每一個末端可連接至半導體封裝500的導電墊224b或印刷電路板248的導電墊246。在本發明一實施例中，被動元件238b的兩個末端可分別連接至設置於半導體封裝500的內連線結構220頂面的兩個不同的金屬墊(如第10圖所示之實施例中，被動元 件238b1的兩個末端係分別連接至兩個不同的金屬墊224b1和224b2)。在本發明另一實施例中，被動元件238b的其中一個末端可連接至設置於半導體封裝500的內連線結構220頂面的金屬墊224b，而被動元件238b的另一個末端可連接至設置於被動元件238b上方之印刷電路板248的金屬墊(圖未顯示)。在本發明又另一實施例中，被動元件238b的兩個末端可分別連接至設置於被動元件238b上方之印刷電路板248的兩個不同的金屬墊(圖未顯示)。
第10圖為本發明實施例之半導體封裝的被動元件238b1的透視圖。如第10圖所示之一實施例中，舉例來說，如果被動元件238b1為一電感，被動元件238b1的兩個末端可分別連接至設置於例如半導體封裝500的內連線結構220頂面的兩個不同的金屬墊224b1和224b2。如果被動元件238b1例如為一電感，其具有設置在相同層(level)的複數匝(turn)，則被動元件238b1可包括一連接片段224b3，該被動元件238b1的連接片段224b3與238b1的一部分238c相互交叉，但並未與部分238c直接接觸。在本發明一實施例中，連接片段224b3可由最頂層金屬層(與內連線結構220的金屬層的金屬墊224b1和224b2相同層)形成，以避免短路。
第1表係顯示習知晶片上電感(on-chip inductor)與本發明實施例之電感(之後簡稱為封裝電感(package inductor))的電性比較結果。習知的晶片上電感係設計位於一半導體 封裝的一內連線結構的一金屬墊(最頂層金屬層)之層。而本發明實施例之封裝電感係設計位於一半導體封裝的一金屬墊和一導電凸塊之間的層。本發明實施例之封裝電感的厚度(約為30μm)會遠大於習知的晶片上電感的厚度(約為2.8μm)。因為本發明實施例之封裝電感(被動元件)的電阻值下降，所以本發明實施例之封裝電感的品質因數(Q factor)(Q=ωL/R，其中L為電感值，R為電阻值，而ω為角速度(弧度/秒))為增加。如第1表所示，當習知晶片上電感和本發明實施例之封裝電感做為振盪頻率為4GHz、6.6GHz以及8GHz的電壓控制振盪器時，相較於習知晶片上電感，本發明實施例之封裝電感的品質因數(>40)性能表現係大為提升。
本發明實施例之半導體封裝500的被動元件係具有以下優點。本發明實施例之被動元件與凸塊結構之導電柱狀物位於相同的層因而不需額外的金屬層，上述導電柱狀物係設置於一金屬墊和一導電凸塊之間。因此，可降低製程成本。本發明實施例之被動元件的厚度係遠厚於設置於內連線結構中的習知被動元件。如果本發明實施例之被動元件為一電感，則上述被動元件係具有低電阻和高品質因數(Q factor)。另外，本發明實施例之被動元件可由銅形成，以防止其在後續回焊製程(re-flow process)期間變形。此外，因為本發明實施例之被動元件不會被內連線結構的金屬層和介電孔插塞的配置所限制，所以本發明實施例之被動元件的所在層別可具有較寬鬆的設計規則(design rule)。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
200‧‧‧基板
202‧‧‧半導體元件
204、210、218‧‧‧介層孔插塞
206、212、216‧‧‧介電層
208、214‧‧‧金屬層
220‧‧‧內連線結構
222、226、228‧‧‧保護層
224a、224b、224b1、224b2、246‧‧‧金屬墊
224b3‧‧‧連接片段
227a、227b、230a、230b、236a、236b‧‧‧開口
228a‧‧‧硬化保護層
232‧‧‧凸塊下金屬層
232a、232b‧‧‧凸塊下金屬層圖案
234‧‧‧乾膜光阻
237a、237b、240‧‧‧導電緩衝層
238c‧‧‧部分
238a‧‧‧導電柱狀物
238b、238b1‧‧‧被動元件
242‧‧‧導電凸塊
244‧‧‧底部填充材料
248‧‧‧印刷電路板
250‧‧‧凸塊結構
300‧‧‧半導體晶片
500‧‧‧半導體封裝
第1至9圖為本發明實施例之半導體封裝的製程剖面圖。
第10圖為本發明實施例之半導體封裝的被動元件的透視圖。
200‧‧‧基板
202‧‧‧半導體元件
204、210、218‧‧‧介層孔插塞
206、212、216‧‧‧介電層
208、214‧‧‧金屬層
220‧‧‧內連線結構
222、226‧‧‧保護層
224a、224b、246‧‧‧金屬墊
228a‧‧‧硬化保護層
232a、232b‧‧‧凸塊下金屬層圖案
237a、237b、240‧‧‧導電緩衝層
238a‧‧‧導電柱狀物
238b‧‧‧被動元件
242‧‧‧導電凸塊
244‧‧‧底部填充材料
248‧‧‧印刷電路板
250‧‧‧凸塊結構
300‧‧‧半導體晶片
500‧‧‧半導體封裝

Claims (23)

  1. 一種半導體封裝，包括：一基板；一第一保護層，設置於該基板上；一第二保護層，設置於該第一保護層上；一凸塊下金屬層，設置於該第一保護層與該第二保護層上；一被動元件，設置於該凸塊下金屬層上；一額外凸塊下金屬層，設置於該第一保護層上，該額外凸塊下金屬層與該凸塊下金屬層隔絕；一導電凸塊，設置於該額外凸塊下金屬層上；以及一導電柱狀物，位於該額外凸塊下金屬層和該導電凸塊之間，其中該導電柱狀物和該被動元件位於相同的層。
  2. 如申請專利範圍第1項所述之半導體封裝，其中該被動元件包括一電感、一繞線或一天線。
  3. 如申請專利範圍第1項所述之半導體封裝，更包括一內連線結構，位於該基板和該第一保護層之間，其中該內連線結構包括複數個金屬層和複數個介電層。
  4. 如申請專利範圍第3項所述之半導體封裝，其中該內連線結構包括一金屬墊，由該內連線結構的該些金屬層的一最頂層金屬層形成。
  5. 如申請專利範圍第4項所述之半導體封裝，其中該金屬墊從該第一保護層的一第一開口暴露出來。
  6. 如申請專利範圍第4項所述之半導體封裝，其中該凸塊下金屬層覆蓋從該第一開口暴露出來的該金屬墊，且 延伸至該第一保護層上方。
  7. 如申請專利範圍第4項所述之半導體封裝，其中該第二保護層由該內連線結構的該些介電層的一最頂層介電層形成。
  8. 如申請專利範圍第1項所述之半導體封裝，更包括一焊料，覆蓋該被動元件。
  9. 如申請專利範圍第4項所述之半導體封裝，其中該被動元件具有兩末端，分別連接至該金屬墊和設置於該內連線結構的一頂部的一額外金屬墊。
  10. 如申請專利範圍第4項所述之半導體封裝，其中該被動元件具有兩末端，分別連接至該金屬墊和設置於該被動元件上方的一印刷電路板的一金屬墊。
  11. 如申請專利範圍第4項所述之半導體封裝，其中該被動元件具有兩末端，分別連接至設置於該被動元件上方的一印刷電路板的不同金屬墊。
  12. 如申請專利範圍第1項所述之半導體封裝，其中該被動元件的材料為銅。
  13. 如申請專利範圍第8項所述之半導體封裝，其中該導電凸塊和該焊料位於相同的層。
  14. 如申請專利範圍第6項所述之半導體封裝，更包括一第三保護層，位於該第一保護層和該凸塊下金屬層之間，其中該第三保護層包括一第二開口，暴露出部分從該第一開口暴露出來的該金屬墊。
  15. 如申請專利範圍第14項所述之半導體封裝，其中該第一保護層和該第二保護層包括氧化物、氮化物、氮氧 化物，且該第三保護層包括聚醯亞胺。
  16. 如申請專利範圍第1項所述之半導體封裝，其中該凸塊下金屬層與該被動元件完全重疊。
  17. 如申請專利範圍第3項所述之半導體封裝，其中該被動元件包括一連接片段，跨越該被動元件的一部分。
  18. 如申請專利範圍第17項所述之半導體封裝，其中該連接片段由該內連線結構的該些金屬層的一最頂層金屬層形成。
  19. 一種半導體封裝，包括：一第一保護層，設置於一基板上；一第二保護層，設置於該第一保護層上；一凸塊下金屬層，設置於該第一保護層與該第二保護層上；一被動元件，設置於該凸塊下金屬層上；一額外凸塊下金屬層，設置於該基板上，該額外凸塊下金屬層與該凸塊下金屬層隔絕；一導電凸塊，設置於該額外凸塊下金屬層上；以及一導電柱狀物，位於該額外凸塊下金屬層和該導電凸塊之間，其中該導電柱狀物和該被動元件位於相同的層；以及一焊料，覆蓋該被動元件。
  20. 如申請專利範圍第19項所述之半導體封裝，其中該被動元件具有兩末端，分別連接至位於該凸塊下金屬層和該基板之間的不同金屬墊。
  21. 如申請專利範圍第19項所述之半導體封裝，其中該被動元件具有兩末端，分別連接至位於該凸塊下金屬層 和該基板之間的一金屬墊和設置於該被動元件上方的一印刷電路板的一金屬墊。
  22. 如申請專利範圍第19項所述之半導體封裝，其中該被動元件具有兩末端，分別連接至設置於該被動元件上方的一印刷電路板的不同金屬墊。
  23. 如申請專利範圍第19項所述之半導體封裝，其中該被動元件的材料為銅。
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