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CN102479774A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN102479774A
CN102479774A CN2011103251826A CN201110325182A CN102479774A CN 102479774 A CN102479774 A CN 102479774A CN 2011103251826 A CN2011103251826 A CN 2011103251826A CN 201110325182 A CN201110325182 A CN 201110325182A CN 102479774 A CN102479774 A CN 102479774A
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China
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mentioned
layer
semiconductor packages
passive component
lower metal
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Granted
Application number
CN2011103251826A
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English (en)
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CN102479774B (zh
Inventor
詹归娣
林子闳
黄清流
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MediaTek Inc
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MediaTek Inc
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Publication of CN102479774A publication Critical patent/CN102479774A/zh
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Abstract

本发明提供一种半导体封装。上述半导体封装包括基板；第一保护层，设置于上述基板上；凸块下金属层，设置于上述第一保护层上；无源元件，设置于上述凸块下金属层上。本发明实施例的半导体封装可降低工艺成本，且上述无源元件具有低电阻和高品质因数。

Description

半导体封装
技术领域
本发明是有关于一种半导体封装，特别有关于一种半导体封装的无源元件。
背景技术
对现有的覆晶封装(flip chip package)而言，电感的要求为低电阻，使其可以达到高品质因数(Q factor)。电感的品质因数定义为当处于某一特定频率时，其电感电抗和电阻之间的比例，且电感的品质因数用来衡量电感的效能。电感的品质因数愈高，愈接近无损耗的理想电感。
现有覆晶封装的工艺通常使用位于晶片的内连线结构的额外金属层来改善电感的品质因数。然而，上述额外金属层会增加工艺成本，且会对产率对有不良的影响。
因此，在此技术领域中，需要一种高品质因数的电感，以满足上述需求且克服现有技术的缺点。
发明内容
为了要得到晶片上高品质因数的无源元件，本发明提供一种半导体封装。
本发明一实施例提供一种半导体封装，上述半导体封装包括基板；第一保护层，设置于上述基板上；凸块下金属层，设置于上述第一保护层上；以及无源元件，设置于上述凸块下金属层上。
本发明另一实施例提供一种半导体封装，上述半导体封装包括凸块下金属层，设置于基板上；无源元件，设置于上述凸块下金属层上；焊料，覆盖上述无源元件。
本发明另一实施例提供一种半导体封装，上述半导体封装包括凸块下金属层，设置于基板上；铜柱状物，设置于上述凸块下金属层上；焊料，设置于上述铜柱状物上。
本发明实施例的半导体封装可降低工艺成本，且上述无源元件具有低电阻和高品质因数。
附图说明
图1至9为本发明实施例的半导体封装的工艺剖面图。
图10为本发明实施例的半导体封装的无源元件的透视图。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来称呼特定的元件。本领域的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求书并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及权利要求书当中所提及的“包含”是开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此是包含任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表第一装置可直接电气连接于第二装置，或通过其它装置或连接手段间接地电气连接到第二装置。
图1至9为本发明实施例的半导体封装500的工艺剖面图。本发明实施例的半导体封装500为覆晶封装(flip chip package)。本发明实施例的半导体封装500可包括与凸块结构的导电柱(conductivepillar)整合的无源元件(passive device)，而导电柱设置于金属垫和导电凸块之间，以使上述无源元件的厚度远大于现有的设置于内连线结构中且没有额外金属层的无源元件的厚度。如果上述无源元件为电感，则可具有低电阻和高品质因数(quality factor(Q factor))。
请参考图1，提供半导体晶片300。在本发明的实施例中，半导体晶片300可包括基板200，其具有半导体元件202设置于其上。内连线结构220，设置于基板200和半导体元件202上。在本发明的实施例中，内连线结构220可提供半导体元件202的电性传输路径。在本发明的实施例中，设置于基板200上的内连线结构220可包括多个金属层、与金属层交错堆叠的多个介电层，和穿过介电层的多个介层孔插塞204、210、218。举例来说，内连线结构220的金属层可包括金属层208、214和金属垫224a、224b。另外，金属垫224a、224b属于内连线结构220的金属层中的最顶层金属层(uppermost metallayer)。在本实施例中，金属垫224a用于传输半导体晶片300的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号，而金属垫224b用于传输电源信号至后续形成于其上的无源元件。举例来说，内连线结构220的介电层可包括介电层206、212、216和保护层(passivation layer)222。另外，保护层222属于内连线结构220的介电层中的最顶层介电层(uppermost dielectric layer)。
接着，请再参考图1，在半导体晶片300上进行凸块工艺(bumpprocess)。利用沉积方式，顺应性形成保护层226，覆盖金属垫224a、224b。在本发明的实施例中，保护层226可包括氧化物、氮化物或氮氧化物。接着，蚀刻保护层226，以分别于金属垫224a、224b上形成开口227a、227b，以使部分金属垫224a、224b分别从开口227a、227b暴露出来。
接着，请再参考图1，可利用涂布方式，整体形成保护层228。在本发明的实施例中，保护层228可包括聚酰亚胺(polyimide)，当半导体晶片300遭受不同种类的环境压力时，保护层228可提供可靠的绝缘。
接着，请参考图2，利用包括微影和显影工艺的蚀刻工艺，移除部分保护层228，以分别于开口227a、227b上形成开口230a、230b。因此，部分金属垫224a、224b分别从开口230a、230b暴露出来。
接着，请参考图3，对图2所示的保护层228的进行硬化(curing)工艺，以固化保护层228。进行硬化工艺之后，保护层228的高度会下降，会因为保护层228的收缩以形成硬化保护层228a。
接着，请参考图4，可利用例如溅镀或电镀法的沉积方式，在硬化保护层228a上形成凸块下金属层(under bump metallurgy(UBM)layer)232。同时，凸块下金属层232形成开口230a、230b的侧壁以及底面。并且，凸块下金属层232延伸至硬化保护层228a的顶面上方。在本发明的实施例中，凸块下金属层232由钛层和位于钛层上的铜层构成。
图5至8显示位于凸块下金属层232上的无源元件和导电柱的形成方式。接着，请参考图5，在凸块下金属层232上全面性堆叠干膜光阻234。在本发明其他实施例中，也可使用液态光阻来代替干膜光阻234。接着，利用包括曝光和显影步骤的微影工艺蚀刻干膜光阻234，以在金属垫224a、224b的上方分别形成开口236a、236b，以确定出后续无源元件和导电柱的形成位置。在本发明的实施例中，干膜光阻234的厚度可介于20μm至40μm之间。
接着，请参考图6，可利用电镀方式，分别于开口236a、236b的底面上形成导电缓冲层237a、237b。在本发明的实施例中，导电缓冲层237a、237b可做为形成于其上的无源元件和导电柱的种晶层(seedlayer)、黏着层和阻障层。在本发明的实施例中，导电缓冲层237a、237b可包括镍。然后，分别于导电缓冲层237a、237b上形成导电柱238a和无源元件238b，并填充开口236a、236b。在本发明实施例中，导电柱238a可用做为后续导电凸块的焊点(solder joint)形成于其上，而导电凸块用于传输半导体晶片300的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。因此，导电柱238a可帮助增加凸块结构的机械强度。在本发明实施例中，导电柱238a可由铜形成，以防止在后续回焊工艺(solder re-flow process)中变形。例如电感、变压器、绕线或天线等的半导体封装的无源元件238b可与导电柱238a形成于同一层。在本发明实施例中，无源元件238b可为厚度厚(由干膜光阻234确定)和强壮的结构，特别是用于形成电感时。
接着，请参考图7，可利用例如使用适当蚀刻剂的湿蚀刻工艺的剥除工艺(stripping process)，移除干膜光阻234。进行剥除工艺之后，未被导电柱238a和无源元件238b覆盖的凸块下金属层232暴露出来。
接着，请参考图8，进行非等向性蚀刻工艺(anisotropic etchingprocess)，以移除未被导电柱238a和无源元件238b覆盖的凸块下金属层232，因此形成分别位于导电柱238a和无源元件238b下方的凸块下金属层图案(pattern)232a、232b。在进行如图8所示的工艺之后，完成本发明实施例的半导体封装的无源元件238b，其中凸块下金属层图案232b与无源元件238b完全重叠。注意金属垫224b仅用于传输电源信号至形成于其上的无源元件238b，因此金属垫224b与无源元件238b部分重叠但并非完全重叠。
接着，请参考图9，可利用电镀方式，在导电柱238a上形成导电缓冲层240。在本发明实施例中，导电缓冲层240为选择性的元件，其可做为形成于其上的导电凸块的种晶层(seed layer)、黏着层和阻障层。在本发明实施例中，导电缓冲层240可包括镍。
可利用搭配蚀刻光阻层的电镀工艺或网版印刷工艺，在导电缓冲层240上形成焊料。接着，移除上述蚀刻光阻层，且进行回焊工艺，以于导电柱238a上形成导电凸块242。在本发明实施例中，导电凸块242用于传输半导体晶片300的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。在本发明实施例中，导电柱238a、导电凸块242和两者之间的导电缓冲层240(选择性元件)共同构成凸块结构250。在本发明其他实施例中，可在无源元件238b上额外形成导电缓冲层或焊料，其中导电凸块242和焊料可位于同一层。经过上述工艺之后，完成本发明实施例的半导体封装500。
另外，半导体封装500可与如图9所示的印刷电路板248接合。在本发明实施例中，底部填充材料(underfill material)244可选择性填满的半导体封装500和印刷电路板248之间的空间。注意半导体封装500的导电凸块242接合至印刷电路板248的金属垫246，而印刷电路板248设置于半导体封装500的导电凸块242和无源元件的上方。
本发明实施例的半导体封装500提供无源元件238b，其与凸块结构250设置在相同层别(level)，上述凸块结构250介于半导体封装500的金属垫224b和印刷电路板248的金属垫246之间。如图9所示，例如为电感的无源元件238b具有两个末端，其中每一个末端可连接至半导体封装500的导电垫224b或印刷电路板248的导电垫246。在本发明实施例中，无源元件238b的两个末端可分别连接至设置于半导体封装500的内连线结构220顶面的两个不同的金属垫(如图10所示的实施例中，无源元件238b1的两个末端分别连接至两个不同的金属垫224b1和224b2)。在本发明另一实施例中，无源元件238b的其中一个末端可连接至设置于半导体封装500的内连线结构220顶面的金属垫224b，而无源元件238b的另一个末端可连接至设置于无源元件238b上方的印刷电路板248的金属垫(图未显示)。在本发明的又一实施例中，无源元件238b的两个末端可分别连接至设置于无源元件238b上方的印刷电路板248的两个不同的金属垫(图未显示)。
图10为本发明实施例的半导体封装的无源元件238b1的透视图。如图10所示的实施例中，举例来说，如果无源元件238b1为电感，无源元件238b1的两个末端可分别连接至设置于例如半导体封装500的内连线结构220顶面的两个不同的金属垫224b1和224b2。如果无源元件238b1例如为电感，其具有设置在相同层(level)的复数匝(turn)，则无源元件238b1可包括连接片段224b3，无源元件238b1的连接片段224b3与238b1的一部分238c相互交叉，但并未与部分238c直接接触。在本发明的实施例中，连接片段224b3可由最顶层金属层(与内连线结构220的金属层的金属垫224b1和224b2相同层)形成，以避免短路。
第1表现有晶片上电感(on-chip inductor)与本发明实施例之例如电感的无源元件的电性比较结果
Figure BSA00000597235100061
Figure BSA00000597235100071
Figure BSA00000597235100081
第1表显示现有晶片上电感(on-chip inductor)与本发明实施例的电感(之后简称为封装电感(package inductor))的电性比较结果。现有的晶片上电感设计位于半导体封装的内连线结构的金属垫(最顶层金属层)层。而本发明实施例的封装电感设计位于半导体封装的金属垫和导电凸块之间的层。本发明实施例的封装电感的厚度(约为30μm)会远大于现有的晶片上电感的厚度(约为2.8μm)。因为本发明实施例的封装电感(无源元件)的电阻值下降，所以本发明实施例的封装电感的品质因数(Q factor)(Q＝ωL/R，其中L为电感值，R为电阻值，而ω为角速度(弧度/秒))增大。如第1表所示，当现有晶片上电感和本发明实施例的封装电感做为振荡频率为4GHz、6.6GHz以及8GHz的电压控制振荡器时，相较于现有晶片上电感，本发明实施例的封装电感的品质因数(＞40)性能表现大为提升。
本发明实施例的半导体封装500的无源元件具有以下优点。本发明实施例的无源元件与凸块结构的导电柱位于相同的层因而不需额外的金属层，上述导电柱设置于金属垫和导电凸块之间。因此，可降低工艺成本。本发明实施例的无源元件的厚度远厚于设置于内连线结构中的现有无源元件。如果本发明实施例的无源元件为电感，则上述无源元件具有低电阻和高品质因数(Q factor)。另外，本发明实施例的无源元件可由铜形成，以防止其在后续回焊工艺(re-flow process)期间变形。此外，因为本发明实施例的无源元件不会被内连线结构的金属层和介电孔插塞的配置所限制，所以本发明实施例的无源元件的所在层别可具有较宽松的设计规则(design rule)。
本领域中技术人员应能理解，在不脱离本发明的精神和范围的情况下，可对本发明做许多更动与改变。因此，上述本发明的范围具体应以后附的权利要求界定的范围为准。

Claims (26)

1.一种半导体封装，包括：
基板；
第一保护层，设置于上述基板上；
凸块下金属层，设置于上述第一保护层上；以及
无源元件，设置于上述凸块下金属层上。
2.如权利要求1所述的半导体封装，其特征在于，上述无源元件包括电感、绕线或天线。
3.如权利要求1所述的半导体封装，其特征在于，更包括内连线结构，位于上述基板和上述第一保护层之间，其中上述内连线结构包括多个金属层和多个介电层。
4.如权利要求3所述的半导体封装，其特征在于，上述内连线结构包括金属垫，由上述内连线结构的上述多个金属层的最顶层金属层形成。
5.如权利要求4所述的半导体封装，其特征在于，上述金属垫从上述第一保护层的第一开口暴露出来。
6.如权利要求4所述的半导体封装，其特征在于，上述凸块下金属层覆盖从上述第一开口暴露出来的上述金属垫，且延伸至上述第一保护层上方。
7.如权利要求4所述的半导体封装，其特征在于，更包括第二保护层，位于上述基板和上述金属垫之间，其中上述第二保护层由上述内连线结构的上述多个介电层的最顶层介电层形成。
8.如权利要求1所述的半导体封装，其特征在于，更包括焊料，覆盖上述无源元件。
9.如权利要求4所述的半导体封装，其特征在于，上述无源元件具有两末端，分别连接至上述金属垫和设置于上述内连线结构的顶部的额外金属垫。
10.如权利要求4所述的半导体封装，其特征在于，上述无源元件具有两末端，分别连接至上述金属垫和设置于上述无源元件上方的印刷电路板的金属垫。
11.如权利要求4所述的半导体封装，其特征在于，上述无源元件具有两末端，分别连接至设置于上述无源元件上方的印刷电路板的不同金属垫。
12.如权利要求1所述的半导体封装，其特征在于，上述无源元件的材料为铜。
13.如权利要求8所述的半导体封装，其特征在于，更包括：
额外凸块下金属层，设置于上述第一保护层上，上述额外凸块下金属层与上述凸块下金属层隔绝；
导电凸块，设置于上述额外凸块下金属层上；以及
上述导电柱，位于上述额外凸块下金属层和上述导电凸块之间，其中上述导电柱和上述无源元件位于相同的层。
14.如权利要求13所述的半导体封装，其特征在于，上述导电凸块和上述焊料位于相同的层。
15.如权利要求6所述的半导体封装，其特征在于，更包括第三保护层，位于上述第一保护层和上述凸块下金属层之间，其中，上述第三保护层包括第二开口，暴露出部分从上述第一开口暴露出来的上述金属垫。
16.如权利要求15所述的半导体封装，其特征在于，上述第一保护层和上述第二保护层包括氧化物、氮化物、氮氧化物，且上述第三保护层包括聚酰亚胺。
17.如权利要求1所述的半导体封装，其特征在于，上述凸块下金属层与上述无源元件完全重叠。
18.如权利要求3所述的半导体封装，其特征在于，上述无源元件包括连接片段，跨越上述无源元件的一部分。
19.如权利要求18所述的半导体封装，其特征在于，上述连接片段由上述内连线结构的上述多个金属层的最顶层金属层形成。
20.一种半导体封装，包括：
凸块下金属层，设置于基板上；
无源元件，设置于上述凸块下金属层上；以及
焊料，覆盖上述无源元件。
21.如权利要求20所述的半导体封装，其特征在于，上述无源元件具有两末端，分别连接至位于上述凸块下金属层和上述基板之间的不同金属垫。
22.如权利要求20所述的半导体封装，其特征在于，上述无源元件具有两末端，分别连接至位于上述凸块下金属层和上述基板之间的金属垫和设置于上述无源元件上方的印刷电路板的金属垫。
23.如权利要求20所述的半导体封装，其特征在于，上述无源元件具有两末端，分别连接至设置于上述无源元件上方的印刷电路板的不同金属垫。
24.如权利要求20所述的半导体封装，其特征在于，上述无源元件的材料为铜。
25.如权利要求20所述的半导体封装，其特征在于，更包括：
额外凸块下金属层，设置于上述基板上，上述额外凸块下金属层与上述凸块下金属层隔绝；
导电凸块，设置于上述额外凸块下金属层上；以及
导电柱，位于上述额外凸块下金属层和上述导电凸块之间，其中上述导电柱和上述无源元件位于相同的层。
26.一种半导体封装，包括：
凸块下金属层，设置于基板上；
铜柱状物，设置于上述凸块下金属层上；以及
焊料，设置于上述铜柱状物上。
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