TW557582B - Compound semiconductor switch circuit device - Google Patents

Abstract

A compound semiconductor switch circuit device is provided, which can reduce the chip size of the switch circuit by omitting the shunt FET and can broaden the gate width of the FET in the switch circuit but needn't to enlarge the chip size. In the device, n+ type dopant diffusion area is used to form the resistor and n+ type dopant diffusion areas are also formed under adjacent pads and wiring layers, so that the distances between the pads and the wiring layers can be increased. Moreover, the disposition width of the winding resistor is reduced and the space originally for the resistor is then used to dispose the resistor and a part of the FET, so that the gate width of the FET can be enlarged even the chip size remains the same.

Description

557582

[Technical field to which the invention belongs The present invention relates to a body switch circuit device, a conductor switch circuit device [Known Technology] Field] A compound semiconductor that can be used for high-frequency switching, especially a compound semi-mobile phone that can be used in the 2 · 4GHz band or more In communication equipment for mobile bodies, the switching circuits of micro-antennas in the GHz band or the switching circuits for transmitting and receiving signals are often used. Switching elements that can cut such South frequency signals (for example: Japanese Patent Laid-Open Publication 9— 丨 8 丨6 4 2)) Because this element handles high frequencies, potassium and arsenic (GaAs) field-effect transistors (hereinafter referred to as FETs) are often used, thus promoting the single-crystal microwave integrated circuit (MM) that integrates the aforementioned switching circuit itself. IC) development. FIG. 4 (A) is a cross-sectional view of a GaAs FET. The surface portion of the undoped GaAs substrate 1 is doped with 1 ^ -type impurities to form an N-type channel region 2, and a gate electrode 3 is disposed in Schottky contact with the surface of the channel region 2, and On both sides of the gate electrode 3, a source electrode and a drain electrode 4, 5 which are in ohmic contact with the GaAs surface are arranged. The transistor forms a depletion layer in the channel region 2 directly below the potential of the gate electrode 3 to control the channel current between the source electrode 4 and the dead electrode 5. Fig. 4 (B) is a circuit diagram of the principle of a compound semiconductor switching circuit device called SPDT (Sigin 1 e Pole Double Throw) using a GaAs FET. The sources (or drains) of the first FET1 and the second FET2 are connected to a common input terminal IN, and the gates of the FET1 and FET2 are connected to the first and second control terminals Ctl-1 and Ctl-2 through resistors ri and R2, respectively. And the drain of each FET (or

313610.ptd Page 5 557582 V. Description of the Invention (2) Source) is connected to the first and second output terminals OUT1 and OUT2. The signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which the level signal is applied is turned ON so that the signal applied to the input terminal in can be transmitted to either party. Output terminal. The configuration purpose of the resistors R1 and R2 is to prevent the high-frequency signal from leaking through the gate electrode with respect to the DC potential of the control terminals C11-1, C11-2 which are AC grounds. An equivalent circuit diagram of the compound semiconductor switching circuit device is shown in FIG. 5. The microwave is based on a characteristic impedance of 50 Ω, and the impedance of each terminal is represented by R1 = R2 = R3 = 50Q resistance. In addition, when the potential of each terminal is set to VI, V2, and V3, the insertion loss (Insertiorl L 0 s s) and insulation (I s 〇 1 a t i 〇 η) are expressed by the following formulas. Insertion Loss = 20 log (V2 / VI) [dB] This is the insertion loss when a signal is transmitted from the common input terminal IN to the output terminal 〇uTl,

Isolation = 201og (V3 / VI) [dB] This is the insulation (Isolation) from the common input terminal I N to the output terminal 0 υ τ 2. In the compound semiconductor switching circuit device, in order to reduce the above-mentioned insertion loss (I nser t i οn Lo s s) as much as possible and improve insulation (isolation), the design of FETs that can be inserted in series on the signal path is very important. The reason for using GaAs FET as the fet is that GaAs has a higher electron moving speed than silicon (Si), so the resistance is small and the loss can be reduced. Since GaAs is a semi-insulating substrate, it is suitable for high insulation between signal paths Into. However, the price of GaAs substrates is second to none. If the equivalent of a pin diode can be manufactured in y, GaAs will lose competitiveness in cost competition.

313610.ptd ms »Page 6 557582 V. Description of the invention (3) In the above compound semiconductor switch circuit device, the resistance R of the channel region 2 of the FET is as follows: · 1 / en / z S [Ω] e ^ Electronic charge (1.6x 10 'η two-electron carrier concentration β ·· electron moving speed S: the cross-sectional area of the channel area (cm2) Therefore, in order to reduce the resistance R as much as possible, the channel width is designed to be larger, and then the channel area's interruption is increased Area to reduce the insertion loss (Insertion Loss). In this way, the capacitance component of the Yttky contact formed by the gate electrode 3 and the channel region 2 will be enlarged, and high-frequency input signals leak out from this and cause insulation (I s ο 1 ati ο η) deterioration. In order to avoid the above situation, the shunt f Ε τ was designed to improve the insulation (Isolation), but because the chip size is large and the cost is increased, the development is replaced by cheap silicon chips, so that it loses the market. Therefore, Development can eliminate the shunt FET to reduce the switching circuit of the chip. Figure 6 is a circuit diagram of a compound semiconductor switching circuit device with a width of 4 0 0 // m. Source electrodes of the first FET1 and the second FET2 Or electrode) are connected to the common input terminal IN, and the gate electrodes of FET1 and FET2 are connected to the first and second control terminals Ctl-1 and Ctl-2 through resistors R1 and R2, respectively, and the drain electrodes of FET1 and FET2 (Or source electrode) connected to the first and second round output terminals OUT1 and OUT2. Applied to the first and second control terminals ctl -1, '

The control signal of Ct 1-2 is a complementary signal. The FET on the side to which the level signal is applied is turned on, so that the input signal applied to the common input terminal IN can be transmitted.

313610.ptd 557582 V. Description of the invention (4) Output terminal to either side. The resistors R1 and R2 are arranged to prevent high-frequency signals from leaking through the gate electrode with respect to the DC potential of the control terminals C11 — 1, and c 11-2 as AC ground. The circuit configuration shown in Fig. 6 is roughly the same as the circuit of the compound semiconductor switching circuit device called SPDT (Single Pole Double Throw) using the Ga As FET shown in Fig. 4 (B). The gate of FET1 * FET2 The width Wg of the electrode is designed as 40 0 # m. The gate width Wg is smaller than the conventional one, which means that the on-resistance of the FET is increased, and by reducing the area of the gate electrode (Lgx Wg), the parasitic capacitance of the Schottky junction between the gate electrode and the channel region will be reduced, and There is a big difference in circuit operation. Fig. 7 is an example of a compound semiconductor wafer in which the above-mentioned compound semiconductor switching circuit device is integrated. The switching FET1 and FET2 are arranged in the center of the GaAs substrate, and the gate electrodes of each FET are connected to resistors R1 and R2. In addition, pads corresponding to the common input terminal IN, the output terminals OUT1 and OUT2 'control terminals Ctl-1 and Ctl-2 are provided around the substrate. The wiring system of the second layer shown by the dotted line and the gate metal layer (Ti / Pt / Au) 20 formed at the same time as the formation of the gate electrode of each FET are used. The wiring system of the third layer shown by the solid line is used to A pad metal layer (Ti / Pt / Au) 30 is formed by connecting each component and forming a pad. The resistive metal layer (AuGe / Ni / Au) 10 which is in resistance contact with the substrate of the first layer is used to form a source electrode, a drain electrode, and a take-out electrode at each end of each resistor of the FET. In FIG. 7, It is not shown because it overlaps with the pad metal layer. As can be seen from Fig. 7, the constituent parts are only connected to FETi, FET2, and resistor R1.

313610.ptd Page 8 557582 V. Description of the invention (5) and R2, common input terminals IN, output terminals OUT1 and OUT2, control pads corresponding to control terminals C11-1 and C11-2, and composed of the smallest constituent parts . In addition, since the FET1 is formed with a gate width of 400 / z m (the same is true for the FET2), the chip size can be reduced. That is, FET1 shown in Fig. 7 is formed in a rectangular channel region 12 surrounded by a dot chain. Two comb-shaped third-layer pad metal layers 30 extending from the lower side are connected to the source electrode 13 (or drain electrode) of the output terminal OUT1, and the first-layer resistive metal layer 10 is formed thereunder. Source electrode 1 4 (or drain electrode). In addition, two comb-shaped third-layer pad metal layers 30 extending from the upper side are connected to the drain electrode 15 (or source electrode) of the common input terminal ιN, and there is a first-layer resistive metal layer 1 below it. 〇 formed drain electrode 14 (or source electrode). The two electrodes are arranged in a comb-like shape, and the gate electrodes 17 formed by the gate metal layer 20 of the second layer are arranged on the channel region 12 in three combs. In addition, the comb-shaped drain electrode 1 3 (or source electrode) that extends from the upper center is shared by the FET1 and the FET2, and can be further downsized. Here, the gate width of 40 0 // m ′ means that the sum of the gate widths of the comb-shaped gate electrodes 17 of each F E T is 4 0 0 // m each. As a result, the size of the compound semiconductor wafer can be reduced to 0.31 × 0.31 mm2. This can significantly reduce the wafer size compared with the conventional compound semiconductor wafer size using a shunt FET. Fig. 8 (A) is a partially enlarged plan view of the FET1 shown in Fig. 7. In the figure, a rectangular region surrounded by a dot chain line is formed in the channel region 12 of the substrate. The four comb-shaped third-layer pad metal layers 30 extending from the left are connected to the source electrode 13 (or the drain electrode) of the output terminal OUT1, and a first-layer resistive metal layer 10 is formed thereunder. Source electrode 14 (or drain mini 557582

尨 、 * 拉 二 ΐ formed by four comb-shaped third pad metal layers 30 extending from the right side Ϊΐΐ 汲 input terminal 0 of the drain electrode 15 (or source electrode), two and one resistance metal layer 10 The drain electrode 16 (or the source electrode 2 is configured in a comb-like shape, and the gate electrode 17 formed by Dangshen's closed-electrode metal layer 20 is arranged on the channel region 12 in a comb shape. (8) and (B) are partial cross-sectional views of the FET. The substrate is provided with a channel region 12 and n + -type impurity diffusion regions forming source regions 18 and drain regions 19 on both sides thereof, A gate electrode 17 is provided on the channel region 12, and a drain electrode M and a source electrode 16 formed of a first-layer resistive metal layer 10 are provided on the n + -type impurity diffusion region. Then, the foregoing is provided thereon. The third layer of the pad electrode layer 13 and the source electrode 15 are formed by the pad metal layer 30, and the wiring of each element is performed. For this switching circuit, the gate width is reduced in the high-frequency band of 2-4 GHz or higher. The insertion loss (Inserti〇n L〇ss) caused by 400 // m has little deterioration, and it is known that the insulation (I s 0 1 ati 〇n) can With the reduction of the parasitic capacitance of ρ £ τ, it is improved, and the insulation is designed by giving priority to the design. 'With a gate width of 4 0 0 // m, the insulation above 20 d B (Isolation ) 〇 The compound semiconductor switch circuit device showing the actual pattern in Figure 7 is designed with the gate length Lg of FET1 and FET2: 0.5 / zm and the gate width Wg ^ 4〇〇 / zm 'to control the channel formation conditions to have different idss. , And then use FET1 and FET2 as the transmitting side and the receiving side respectively, so as to ensure that the insertion loss (Insertion Loss) on the transmitting side is 〇〇〇〇 heart, on the transmitting side 557582 V. Description of invention (7) The insulation (I s ο 1 ati ο η) on the receiving side is 2 0 d B. This feature is used for the use of Bluetooth (mobile phones, notebook PCs, mobile information terminals including wireless interconnection) Devices, digital cameras, and other peripheral devices to enhance communication specifications in mobile and business environments). 2. 4GHz band ISM Band (Industrial Scientific and Medical frequency band) in the field of spectral diffusion communication applications. To solve Question] As mentioned above, the chip size can be greatly reduced by eliminating the shunt FET and reducing the gate width to 40 〇α m. However, under the diversified needs of users, in order to achieve an increase or decrease of the maximum linear input power, When the FET's gate width is enlarged due to insulation properties, the size and shape of the FET shown in FIG. 7 may be increased, and the wafer size may be increased. However, at present, the performance of silicon semiconductor chips has also improved significantly, and the possibility of using them in the high-frequency band is gradually increasing. In the past, silicon wafers were difficult to use in high-frequency bands, and expensive compound semiconductor wafers were used. However, if the availability of silicon semiconductors increases, of course, compound semiconductor wafers with excessively high wafer prices will not compete with price competition. Therefore, in consideration of reducing the size of the wafer to reduce the cost, it is imperative to reduce the size of the wafer. A [Solution to the Problem] Guan Leiϊ: The compound semiconductor is made up of: in view of the above-mentioned shortcomings, and the compound semiconductor is opened on the surface of the channel region, and the source electrode and the gate are formed to form the first FETt and the second FET '. Use the source electrode of the two FETs as a common input terminal and the drain electrode or source of the two FETs

Page 11 557582 V. Description of the invention (8) The electrodes serve as the first and second output terminals, and have: first and second control terminals connected to the gate electrodes of the two FETs, and gates connected to the two FETs, respectively. Electrode and the first and second resistances of the two control terminals, and a control signal is applied to the gate electrode of the FET to turn on either FET, and the common input terminal and the first and second output terminals described above are either One side forms a signal road controller 'characterized by reducing the area occupied by at least one of the aforementioned resistors' and setting a part of the aforementioned one of the FETs in the vacated area so that, in the past, a sufficient area equipped with resistors, All resistors and a part of the FET are configured, and the FET's gate width can be increased within the same chip size. [Embodiments of the invention] Embodiments of the present invention will be described below with reference to Figs. 1 to 3. Fig. 1 is a circuit diagram of a compound semiconductor switching circuit device according to the present invention. The source electrodes (or drain electrodes) of the first FET1 and the second FET2 are connected to a common input terminal IN, and the gate electrodes of the FET1 and FET2 are connected to the first and second control terminals Ctl-1 and Ctl-2 through a resistor and R2, respectively. The drain electrodes (or source electrodes) of FET1 and FET2 are connected to the first and second output terminals OUT1 and OUT2. The control signals applied to the first and second control terminals Ctl-1 and Ctb 2 are complementary signals, and the FET on the side to which the level signal is applied is turned on so that the input signal applied to the common input terminal IN can be transmitted to Either output terminal. The resistors R1 and R2 are arranged to prevent high-frequency signals from leaking through the gate electrode with respect to the DC potential of the control terminals Ctb1, Ct1-2, which are AC grounds. The circuit structure shown in Figure 1 is a compound called SPDT (Single Pole Double Throw) using the Ga As FET shown in Figure 4 (B).

313610.ptd Page 12 557582 V. Description of the invention (9) The circuit of the principle of the semiconductor switch circuit device is roughly the same, but the biggest difference is that: first, it will be used as the gate electrode of the FET1 on the transmitting side (ON side) The gate width W g 1 is set to 5 0 0 // m, and the gate electrode Wg2 of the gate electrode of the FET2 on the receiving side (0 {? Ρ side) is set to 400 // m or less. In the transmitting-side (ON-side) FET, because only Idss is related to the maximum linear input power (ρo w e r), the ion implantation conditions in the channel region, that is, the impurity concentration and the acceleration voltage are controlled as much as possible to increase Idss. Furthermore, by setting the gate width W g 1 to 5 0 0 // m larger than the receiving side (0 F F side), the Idss in the transmitting side (ON side) is further increased. In other words, the maximum linear input power that 400 " m lacks can be increased. At the same time, for the receiving-side (OFF-side) FET, the most important thing is to be able to accommodate the maximum linear input power (no leakage of high-frequency signals). That is, the ability of the transmitting side (0 N side) FET to output the maximum linear input power and the receiving side (OFF side) capable of accommodating the maximum linear input power are not met, which will cause the switching circuit to fail to output. Maximum linear input power. Therefore, on the 'receiving side (OFF side), the pinch-of f voltage is reduced to maintain its ability to accommodate the maximum linear input power. In other words, by setting the gate width of the FET as the transmitting side (ON side) to 50 0 / zm 'as the gate width of the FET as the receiving side (0FF side) is 40 0 // m, The switching circuit used in the wireless LAN has a maximum linear input power of 22dB. In particular, in the present invention, even if the FET is enlarged to increase the maximum linear input power, the chip size does not change compared with the case of using a FET of 400 m. Figure 2 shows the compound semiconductor switch circuit device integration of the present invention. 313610.ptd Page 13 557582 V. An example of a compound semiconductor wafer made according to the description of the invention. The switching FET1 and FET2 are arranged at the center of the GaAs substrate, and the gate electrodes of each FET are connected to resistors R1 and R2. In addition, pads corresponding to the common input terminal IN, the output terminals OUT1 and OUT2, and the control terminals Ctl-1 and Ctl-2 are provided around the substrate. The wiring system of the second layer shown by the dotted line and the gate metal layer (Ti / Pt / Au) 20 formed at the same time as the gate electrode of each FET are formed, and the wiring system of the third layer shown by the solid line are used to A pad metal layer (Ti / Pt / Au) 30 is formed by connecting each component and forming a pad. The resistive metal layer (AuGe / Ni / Au) 10 which is in electrical contact with the substrate of the first layer is used to form the source electrode, the drain electrode, and the take-out electrode at each end of each resistor of the FET. In the second figure, It is not shown because it overlaps with the pad metal layer. As can be seen from Fig. 2, the component parts are solder pads corresponding to FET1, FET2, resistors R1 and R2, common input terminal IN, output terminal ουτί and OUT2, and control terminals Ct 1-1 and Ctl-2. Made of parts. Since FET2 is the same as that in FIG. 7, its description is omitted. In the FET1, three comb-shaped third-layer pad metal layers 30 extending from the lower side are connected to the source electrode 13 (or> and the electrode electrode) of the output terminal OUT1, and there is a first-layer resistive metal layer 1 below 0 formed source electrode 14 (or drain electrode). In addition, three comb-shaped third-layer pad metal layers 30 extending from the upper side are connected to the drain electrode 15 (or source electrode) of the input terminal IN, and the first-layer resistive metal layer 10 is formed thereunder. Drain electrode 14 (or source electrode). The two electrodes are arranged in a comb-like shape, and the gate electrode 17 formed by the second gate metal layer 20 is arranged on the channel region 12 in five combs.

313610.ptd Page 14 557582 V. Description of the invention (11) In addition, the comb-shaped drain electrode 1 3 (or source electrode) extending from the upper center is shared by FET1 and FET2 and can be miniaturized. The gate width is 5 0 0 m, which means that the total gate width of the comb gate electrode 17 of the FET is 50 0 // m. By reducing the occupied area of the resistor R1 and expanding the arrangement of the FET1 in the vacated area, the gate width of the FET1 can be increased.

The resistors R1 and R2 are n + -type impurity diffusion regions, which are formed simultaneously with the formation of the source and drain regions. In addition, under the peripheral ends of the common input terminal pad, control terminal Ctl-1 pad and Ctl-2 pad, output terminal ουτί pad and OUT2 pad, and the two FET gate electrodes, A ^ +-type impurity diffusion region shown by a one-dot chain line (the gate electrode is overlapped with the gate electrode at the peripheral end portion (not shown)). Here, the η + -type impurity diffusion region is not necessarily provided at the peripheral end portion, and may be provided under each pad and the gate electrodes of the two FETs. The n + -type impurity diffusion regions are formed at the same time as the source and drain regions are formed, and the distance between the n + -type impurity diffusion regions and the resistor at a portion adjacent to R 2 is 4 V m. The reason is described later, but through the η + -type impurity diffusion region, the distance between adjacent solder pads and resistors can be made close to a critical value that can secure an insulation property of 20 dB, that is, 4 // m. Although the resistor R1 is configured in a bent manner, the distance between the resistor R1 and the adjacent resistor R1 can be close to 4 # m.

If the distance between the resistors R1 is close to 4 # ^ and bent, the extra area can be used to expand between the control terminal ctl — 丨 arranged around “^” and the pad corresponding to the output terminal OUT1. ι〇〇 " ^ The gate electrode, source electrode, and drain electrode of FET1 are arranged. Compared with the FET2 side, it is known that 'the area occupied by the resistor R 丨 is reduced, and the total space of the resistor R 丨 is used in the space. Part of this, although it is the gate amplitude 5 0 0 // in, it can be compared with the gate amplitude

557582 V. Description of the invention (12) * FET2 below 400 / zm is arranged on the same area. In other words, it can be housed in the same chip size as a conventional switching circuit of a FETi with a gate width of 400 β. Next, the case where the pitch between each pad, the wiring layer, and the resistor is greatly reduced will be described. The solder pads, wiring layers, and resistors can be provided at a desired pitch in order to ensure predetermined insulation properties. That is, the insulation required for a compound semiconductor switching circuit device is more than 20 dB. In fact, if there is a distance of 4 m, an insulation of more than 20 d B can be sufficiently ensured. Although there is no theoretical basis, from the current thinking direction of semi-insulating GaAs * boards as insulating substrates, the withstand voltage is infinite. However, once measured, it was found that the withstand voltage was limited. Thus, in the semi-insulating GaAs substrate, the depletion layer is extended, and the distance of the depletion layer is changed according to the high-frequency signal. When the electrode adjacent to the depletion layer is reached, a high-frequency signal leaks out. However, a type impurity diffusion region is provided at the peripheral end portion of the adjacent side of the adjacent pattern, and if the pitch is set to 4 // m, the insulation of 20 dB or more can be sufficiently ensured. In addition, if the pitch is set to the left and right in the electromagnetic field simulation (Simulation), the insulation of about 40 d B can also be obtained in 24 (^ 2). Fig. 3 is a cross-sectional view taken along the line AA in Fig. 2. As shown in Fig. 3 As shown, the Qiutong input terminal is provided with a type impurity diffusion region 40 (indicated by a one-dot bond line) provided on the substrate 11 along its peripheral end. In addition, the gate metal layer 20 An n + -type impurity diffusion region 40 is also provided on the substrate below the peripheral end portion of the formed wiring layer 42 to connect the wiring layer 42 and the pad to the substrate n = ON. The n + -type impurity diffusion region 40 is also Can be placed under the solder pad and wiring layer 42

557582 5. Description of the invention (13) As long as it has the function of preventing the high-frequency signal applied to the bonding pad from being transmitted to the wiring layer 42 through the substrate 11. In Fig. 3, although the pads of the common input terminals are shown, the control pads Ctl-1 and Ctl-2 and the pads of the input terminals OUT1 and OUT2 have the same structure.

The resistors R1 and R2 are arranged to prevent high-frequency signals from leaking through the gate electrode with respect to the DC potential of the control terminals C11-1 and C11-2 as AC ground. However, if the pads of the control terminals Ctl-1, Ctl-2 and the wiring layer 42 are too close, high-frequency signals will be directly transmitted from the wiring layer 42 to the soldering of the control terminals Ctl-1, Ctl-2 through the enlarged depletion layer. Pad to allow the high-frequency signal of the wiring layer 42 to leak to the control terminals C11-1 and Ctl-2 as the AC ground. The n + -type impurity diffusion region 40 provided under the wiring layer 42 can prevent high-frequency signals from leaking from the wiring layer 42 to the adjacent pattern through the enlarged depletion layer on the substrate. An n + -type impurity diffusion region 40 is provided on the surface of the substrate 11 under each of the bonding pads and the wiring layer 42. Since the resistors ri and R2 are also formed by using the n + -type impurity diffusion region 40, the substrate 1 is not doped with impurities. 1 (system is semi-insulating, but the substrate resistance value is 1 × 107Ω · cm), the impurity concentration is increased (the ion type is 29Si +, and the concentration is 1 to 5x 108cm-3). As a result, since the depletion layer does not extend to each of the pads, the wiring layer 42, and the resistance, the adjacent

塾, the distance between the wiring layer and the resistor is set to 4 m, which can fully ensure the insulation of 20dB. It can also be seen from FIG. 2 that the pads of the common input terminal ^ are provided with n + -type impurity diffusion regions 40 along three sides in addition to the upper side, and the pads of the output terminals OUT1 and OUT2 are in addition to the corners of the GaAs substrate. (Corner) part

313610.ptd

Page 17 557582 V. Description of the invention (14) Outside the C-shaped ^ +-type impurity diffusion regions 4 are arranged along the four sides. The soldering pads of the control terminals Ctl-1 and Ctl-2 are in addition to the corners of the GaAs substrate and the Outside the part where the resistor and R2 are connected, along the four sides of the irregular pentagon, an n + -type impurity diffusion region 40 is set in a c-sub-shape 5. The portion without the n + -type impurity diffusion region 40 is a portion facing the peripheral end of the GaAs substrate. Even if the depletion layer is enlarged, a considerable distance is maintained from the adjacent solder pads, so that no high-frequency signal is lost. Part of the problem.

Therefore, since the five bonding pads occupy about half of the semiconductor wafer, the wiring layer and the resistor 'can be arranged near the bonding pad using the wiring layer structure of the present invention, and the space in the semiconductor wafer can be enlarged. In other words, the gate width of the FET can be enlarged while maintaining the same chip size. As a result, the size of the compound semiconductor wafer of the present invention can be limited to 0.31 × 0.31 min2. This is the same size as a compound semiconductor wafer that previously used a switch circuit with a ρEτ of 400 m. Since the enlarged views and cross-sectional structures of FET1 and FET2 are the same as those shown in FIG. 8, the explanation is omitted. In addition, F E T, which is a constituent element of the present invention, is a FET having different channel formation conditions such as channel region concentration and acceleration voltage, or different gate widths, but the FET characteristics are not limited to this. It may be a FET having the same FET characteristics.

In addition, in the embodiment of the present invention, although only one F E T arrangement is described, two FETs may be applied. Furthermore, the 'n + type impurity diffusion region may be formed all at the same time as the source and drain regions are formed, or may be a region formed by another process. Also, n + -type impurity diffusion regions may be formed by different processes, respectively.

557582

5. Description of the invention (15) [Effects of the invention] As described in detail above, according to the present invention, the following effects can be obtained.

First, by providing resistors in the n + -type impurity diffusion region, n + -type impurity diffusion regions can be provided directly under the pads occupying almost half of the size of the semiconductor wafer and under the wiring layer of the FET or at the peripheral ends. The distance between adjacent pads, wiring layers, and resistors is reduced to a range that ensures insulation. Thereby, since the space between adjacent resistors R1 adjacent to each other can be arranged close to 彳 and ^ ', the area occupied by the resistors can be reduced. In other words, by using the extra space, a part of the gate electrode, the source electrode, and the drain electrode of FET1 and all the resistances can be arranged at the control terminal Ctl-1 and the output corresponding to the periphery of FET1. Between the solder joints of terminal OUT1. Compared with the FET2 side, it can be known that by using the space of the resistor part to arrange all of the resistor R1 and a part of FE T1, the gate width can be set to 5 m and FET1 with Idss increased. It is arranged on the same area as the FET2 with a gate width of 400 // m. In other words, it has the advantage that the switch circuit that can obtain a maximum linear input power of 22 dB and the switch circuit of the FET which uses a 400 " m gate width in the past two FETs can be housed in the same chip size.

Second, because the distance between the minimum component and the pads, wiring layers, and resistors is shortened as described above, the size of the semiconductor wafer can be reduced, and the price competitiveness of the semiconductor wafer can be greatly improved. In addition, since the chip size can be reduced, it can be mounted in a small package (SMCp6 1.6mm x 1. 6mm x 0.75mm) smaller than the conventional small package (Mcp6 size is 2.1mm) 2.0mm. 3. Since the compound semiconductor switch circuit device of the present invention is

313610.ptd Page 19 557582 V. Description of the invention (16) The design of the shunt FET is omitted. Therefore, the constituent parts are composed of E T1, output terminal OUT1, and FET2, resistors R1 and R2, and common input terminal in , 0UT2, control terminal CU-1 and Ct Bu 2 small pads constitute the advantages of component parts.

557582 Brief description of the drawing [Simplified description of the drawing] Fig. 1 is a circuit diagram for explaining the present invention. Fig. 2 is a plan view for explaining the present invention. Fig. 3 is a sectional view for explaining the present invention. (B) Circuit FIG. 4 is a cross-sectional view of (A) for explaining the conventional example; FIG. 5 is an equivalent circuit diagram for explaining the conventional example. FIG. 6 is a circuit diagram for explaining a conventional example. FIG. 7 is a plan view for explaining a conventional example. FIG. 8 is a (A) plan view for explaining a conventional example; (B) a cross-sectional view [element symbol description] 2 > 12 channel region 3 > 17 gate electrode 4 source electrode 5 drain electrode 10 resistance metal layer 11 Substrate 13, 14 Source electrode (or drain electrode) 15 > 16 Drain electrode (or source »electrode) 18 Source region 19 Drain region 20 Gate metal layer 30 Pad metal layer 40 n + Type Impurity Diffusion Region 42 Wiring LayerΗ 313610.ptd Page 21

Claims (1)

557582 I Case No. 91108310_ & Year of Month 丨 > Revision_ VI. Patent Application Scope 1. A compound semiconductor switch circuit device is formed on the surface of a channel region with a source electrode, a gate electrode and a pole electrode. Brother 1 FET and Brother 2 FET use the source or drain electrodes of the two FETs as common input terminals, and the FET and source or source electrodes of the two FETs as brother 1 and 2 output terminals, and have: The first and second control terminals of the FET gate electrodes are connected, and the first and second resistors of the gate electrodes of the two FETs and the two control terminals are connected respectively, and a control signal is applied to the gate electrodes of the two FETs to Those who turn on the FET of either side and form a signal path with the common input terminal and any of the first and second output terminals are characterized by reducing the area occupied by at least one of the first and second resistors, and A part of the FET of the aforementioned one is disposed on the output region. 2. A compound semiconductor switching circuit device, which is formed on the surface of the channel region with a first electrode and a second FET provided with a source electrode, a gate electrode, and a drain electrode, and the source or drain electrodes of the two FETs are used as a common The input terminal uses the drain electrode or the source electrode of the two FETs as the first and second output terminals, and includes first and second control terminals connected to the gate electrodes of the two FETs and connected to the two FETs, respectively. The gate electrode and the first and second resistors of the two control terminals, and a control signal is applied to the gate electrodes of the two FETs to turn on either FET, and the common input terminal and the first and second output terminals Those who form a signal path on either side are characterized in that the area occupied by at least one of the first and second resistors is reduced, and a part of the one of the FETs is provided on the vacated area, and the 313610.ptc Page 1 2003. 08. 08. 023 557582 _Case No. 91108310_ Year March IV Amendment_ VI. The FET on one side of the patent application is used as the transmitting side of the aforementioned signal path, and the FET on the other side is used Used as the receiving side of the aforementioned signal path. 3. The compound semiconductor switching circuit device according to item 1 or item 2 of the scope of patent application, wherein the bending interval of the aforementioned resistor is reduced to reduce the occupied area. 4 · If the compound semiconductor switch circuit device of item 1 or item 2 of the scope of patent application, a part of the aforementioned FET is arranged between a pad corresponding to the aforementioned control terminal and a pad corresponding to the output terminal, so that Increase the gate width of the FET. 5. The compound semiconductor switching circuit device according to item 1 or item 2 of the patent application scope, wherein the aforementioned resistor is a high-concentration region provided by diffusing a conductive impurity on the substrate. 6. The compound semiconductor switch circuit device according to item 5 of the scope of patent application, wherein the distance between the adjacent resistors is close to a critical value that can ensure a predetermined insulation property. 7. The compound semiconductor switch circuit device according to item 1 or item 2 of the patent application scope, wherein the aforementioned resistance is formed in a high-concentration region where a conductive impurity is diffused, and the corresponding input terminal, control, and Terminals and output terminals under the peripheral end of the pad or the entire pad, and under the peripheral ends of the wiring layer of the two FETs above or under the entire wiring layer, are provided with other conductive impurities diffused to a high level. Concentration zone. 8. For the compound semiconductor switching circuit device of the seventh scope of the application for a patent, wherein the distance between the adjacent regions of all the high-concentration regions described above is close to a certain degree. 313610.ptc 2003. 08. 08. 024 Page 2 557582 _Case No. 91108310_'S Month > Day Amendment_ VI. Patent Application Scope Guaranteed near the critical value of predetermined insulation. 9. The compound semiconductor switching circuit device according to claim 5 in the patent application scope, wherein the diffusion region of the source region and the drain region is used as the aforementioned high concentration 313610.ptc Page 3 2003. 08.08. 025