TW495989B - Chemical compound semiconductor switch circuit device - Google Patents

Abstract

A chemical compound semiconductor switch device is introduced. Conventionally, in order to reduce the insertion loss, the gate width Wg is chosen the maximum value to lower the ""ON"" FET resistance. The FET size increases. Meanwhile, the spacing between bonding pad and lead line layer is kept larger than 20 μm. This invention focuses on the design of high frequency band larger than 24 GHz and omits the distributed FET to confirm isolation. The ""ON"" FET resistance reduction is considered decomposedly and the gate width of the switch-used FET is set below 700 μm to scale down its size. Meanwhile, high concentration region 40 on the periphery of the bonding pads for high frequency signal coupling is set to make sure the smaller room's voltage endurance. So the size of the chemical compound semiconductor switch device is greatly reduced.

Description

495989

Description of the invention (Printed by Intellectual Property of the Ministry of Economic Affairs for employee consumer cooperatives [Technical Field to which the Invention belongs] This invention relates to compound semiconductor switching circuit devices used in high-frequency switching applications, and more particularly to devices used in the 2.4 GHz band or higher. Those who use compound semiconductor switching circuits. [Known technology] Mobile communication devices such as mobile phones use microwaves in the GHz band, and they use switching elements that switch the high-frequency signals for antenna switching circuits and transmitting and receiving switching circuits. (Eg, Japanese Patent Laid-Open No. 9_181642). This device is also used to operate high-frequency wave bands, using potassium / bang (GaAs) field-effect transistors (hereinafter referred to as FETs). Therefore, the above-mentioned switching circuit body is also carried out. Development of integrated monolithic microwave integrated circuit (MMIC). Figure 7 (A) shows a cross-sectional view of a GaAs FET. It is formed by doping n-type impurities on the surface of the non-doped GaAs substrate 1; ^ -Type channel area 2, and gate 3 of shokuky contact is arranged on the surface of N-type channel area 2, and on both sides of gate 3 are arranged (^ 8 surface is ohmic) The source / drain 4, 5 of the ohmic contact. The transistor system uses the potential of the gate 3 to form an empty layer in the direct channel area 2 to control the channel current between the source 4 and the drain 5. Figure 7 (B) shows the principle circuit diagram of the so-called SPDT (Single Pole Double Throw) compound semiconductor switching circuit device using GaAs FET. It is the source (or drain) of the first and second FET1 and FET2. Pole) is connected to the common input terminal 1N, and the gates of each of the FET1 and FET2 are electrically connected to each other ----------------- ^ ----------- -----------, 玎 ------------------ line (please read the precautions on the back before filling in this page) China National Standard (CNS) A4 Specification (210 X 297 mm) 1 312628 495989

The resistance R1 or R2 is connected to the control terminals of the first and second and Ctl_2, and then the drain (or source) of each FET is connected to the output terminals of the first and second, OUT1, OUT2. The signals applied to qh and cu_2 are auxiliary signals, so that the FET to which the Η level signal is applied is ON, so that the signal applied to the turn-on terminal 1N is transmitted to either output terminal. The resistors μ and R2 are provided for the purpose of preventing the leakage of high-frequency signals from the DC potential of the control terminals Ct 1-1 and Ct 1-2, which are grounded to AC, through the gate electrode. An equivalent circuit diagram of the compound semiconductor switching circuit device is shown in FIG. 8. Because the microwave circuit is usually based on its characteristic impedance of 50 Q 'and the impedance of each terminal is represented by r1 = R2 = R3 = 50 Ω resistor. Since the potential of each terminal is represented by VI, V2, and V3, the insertion loss (isolation loss) and isolation (isoaion) can be expressed by the following formulas. Insertion Loss = 20 log (V2 / V1) [dB] This is the insertion loss when a signal is transmitted from the common input terminal IN to the output terminal ουτί, and

Isolation, 10 g (V3 / Vl) [dB] This is the isolation from the common input terminal IN to the output terminal 0ϋΤ2. In the compound semiconductor switching circuit device, it is necessary to reduce the above-mentioned insertion loss (Insertion Loss) as much as possible, and it is required to improve isolation (Isolation). Therefore, the FET connected in series with the signal path is designed to be essential. As the FET, a GaAs FET is generally used because GaAs has a higher electron mobility than Si, so that it can achieve lower loss and lower impedance, and is suitable for high isolation because GaAs is a semi-insulating substrate. GaAs

f Please read the precautions on the back before filling in the blocks on this page)-Binding and ordering. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed in accordance with China National Standard (CNS) A4 (210x297). 2 312628 The Ministry of Economic Affairs recommends property A to print 495989 A7 for consumer cooperatives. B7 V. Description of the invention (3) The substrate is higher in price than Si. If an equivalent PIN diode can be manufactured in Si, it will be cost competitive. unfavorable. Fig. 9 is a circuit diagram of a conventional compound semiconductor switching circuit device. In this circuit, the switching terminals FET1 and FET2 output terminals OUT1, OUT2 and shunt FET3 and FET4 are connected to the ground, and the gates of the shunt FET3 and FET4 are applied to the control terminals of FET2 and FET1. As a result of the complementary signals of Ctl-2 and Ctl-1, when FET1 is turned on, shunt FET4 is turned on, and FET2 and shunt FET3 are turned off. In this circuit, when the signal path of the common input terminal 1N-output terminal OUT 1 is turned on and the signal path of the common input terminal 1N-output terminal OUT2 is turned off, since the shunt FET4 is ON, the output terminal OUT2 The leakage of the input signal, that is, the ground capacitor C leaks to the ground terminal ', so the isolation is improved. Fig. 10 shows an example of a compound semiconductor wafer in which the compound semiconductor switching circuit device is integrated. The switching FET1 and FET2 are arranged on the left and right central portions of the GaAs substrate, and the shunt FET3 and FET4 are arranged near the left and right lower corners, and the gates of the FETs are connected to R1 'R2, R3, and R4. Pads corresponding to the common input terminal 1N, output terminals OUT1, OUT2, control terminals Ctl-1, Ctl-2, and ground terminal GND are placed on the peripheral edge of the substrate. After the sources of the shunt FET3 and FET4 are connected, they are connected to the ground terminal GND via the ground capacitor C. In addition, the second layer wiring shown by the dotted line is a gate metal layer (Ti / Pt / Au) formed at the same time when each FET gate electrode is formed, and the third layer wiring shown by the solid line is the connection and development of each element. ----------------- ^ ---------------------- 1T --------- ----------- Line (Please read the precautions on the back before transcribing each block on this page) This paper size applies to China National Standard (CNS) A4 (210x 297 mm) 3 312628 495989 5 2. Description of the invention (4) A metal layer (Ti / Pt / Au) is formed to form a welding pad. On the first substrate, an ohmic metal layer (AuGe / Ni / Au) in ohmic contact is used to form the source, gate, and lead-out electrodes at each end of each Fet. In FIG. 10, and The pad metal layers overlap and are not shown. An enlarged plan view of a part of the FET1 shown in Fig. 10 is shown in Fig. 11 (A). In the figure, a rectangular area surrounded by a one-point chain line is formed in the channel area of the base plate 11. The third comb-shaped third pad metal layer 30 extending from the left side is connected to the source 13 (or drain) of the output terminal OUT1, and there is a first ohmic metal layer 1 under the bottom. The source 14 (or drain!) Formed. There are four comb-shaped third pad metal layers 30 extending from the right side, which are connected to the drain 15 (or source) of the common input terminal 1N, and there is a first ohmic metal layer below it. 10 formed drain (or source). The two poles are arranged in a comb shape. Figure 11 is a cross-sectional view of a portion of a watch FET. An n-type channel region 12 'is formed on the substrate π, and an n + -type high-concentration region forming a source region 18 and a drain region 19 is provided on both sides thereof, and a gate electrode 7' is provided at the channel region 12 at a high concentration. The field is provided with a source 14 and a source 16 formed by a first Mö metal layer 10, and as described above, a drain 13 and a source 15 are formed by a third solder metal layer 30, and wiring of each element is performed. In the above-mentioned compound semiconductor switching circuit device, in order to minimize the insertion loss (Insertlon L0ss) of the feti and the anode 2, a design method of reducing the resistance at the time of the FET by adopting as large an interrogation width wg as possible is used. For this reason, due to the increase in the closed-electrode width Wg, the size of the feti & fet2 has been increased, and the wafer size has been developed in an increasing direction. (CNS) A4 (210 4 intended 312 628 19 A7 B7 V. Description of the invention (5 Also, the compound semiconductor switch circuit device uses a GaAs substrate with a semi-insulating substrate, and the thermocompression bonding is directly connected to it) Circuit, wiring or welding wire. $ Because the operating signal is a high-frequency wave in the GHz band, a separation distance of more than 20 // m needs to be set in order to ensure the isolation between adjacent wiring. It is also required for compound semiconductor switching circuits. The isolation of the device is more than 20dB. When the isolation obtained by experiments is more than 20dB, a separation distance of more than 20 // m is required. Although the evidence of this theory is insufficient, so far the semi-insulating GaAs substrate is the insulation substrate of the insulation substrate. From an idea point of view, the withstand voltage is infinite. However, according to the actual measurement, it can be seen that the withstand voltage is limited. Therefore, the empty layer extends in the semi-insulating GaAs substrate, and this varies with the distance of the empty layer of the high-frequency signal. When the empty layer reaches the adjacent electrode, high-frequency signal leakage will occur there. Therefore, 'to ensure isolation above 20dB, it is inferred that a space above 20 # m is needed. The distance can be seen from Figure 10. In the conventional compound semiconductor switching circuit device, Hanyou corresponds to the common input terminal 1N, output terminals OUT1, OUT2, and printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the note on the back first) Matters are reprinted on this page) The pads of the control terminals Ctl-1, Ctl-2, and the ground terminal GND are located on the peripheral edge of the substrate. If the pads are separated by at least 20 # m to form a wiring layer, the wafer size will be changed. Increasing direction [Problems to be Solved by the Invention] In the compound semiconductor switch circuit device described above, in order to minimize the insertion loss of FET1 and FET2, the gate width wg is set to a large value, In order to reduce the resistance design method when the FET is ON, the size of each FET will be increased. It is also necessary to ensure the isolation between the pad and the wiring layer. This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm). ) 5 312628 495989 V. Description of the invention (6) Maintain a separation distance of 2 0 // m. =, The conventional compound semiconductor switch circuit device tends to the direction of the chip A 'and the direction of the substrate A: The substrate will be lost due to the replacement of compound semiconductor switching circuit devices with cheap silicon chips. [Means for Solving Problems] The present invention was made in view of the above reasons ^ ^ By reducing the gate width, the size of the FET is reduced, and at the same time, it is difficult to shorten the distance between the zinc pad and the wiring layer, so as to achieve the reduction of compound semiconducting and dry limb switching circuit devices. Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative (please read the precautions on the back before filling in the blocks on this page), that is, 'the first and second FETs with source, idle, and non-polar are formed on the surface of the channel layer. The sources or terminals of the two FETs are connected as a common input terminal: and the drain or source terminals connected to the two FETs are the i-th and second output terminals, and control is applied to the control terminals connected to the gates of the two FETs. Signal, and any -square < FET is blocked, and the compound semiconductor switch circuit device having a signal path in which any one of the above-mentioned common input terminal and any of the above-mentioned first and second output terminals is used as a common signal The input terminal, the first and second output terminals, and the control terminal are provided with a high-concentration area below the peripheral end portion of the pad so that the distance from other patterns of the compound semiconductor switch circuit device directly disposed on the semi-insulating substrate is 2〇 # m or less. [Embodiments of the invention] & Embodiments of the invention will be described below with reference to Figs. 1 to 6. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 6 312628 495989 A7 B7 V. Description of the invention (Figure 1 is a circuit diagram showing the compound semiconductor switch circuit device of the present invention. In the figure, the first FET1 and The source (or drain) of the second FET2 is connected to the common input terminal 1N, and the gates of the FET1 and the FET2 are connected to the j and the second control terminals cn and Ctl_2 via resistors R1 and R2, respectively. And the FET2 terminal (or source) is connected to the first and second output terminals OUT1 and OUT2. The control signals applied to the J and 2 control terminals Ct 1 -1 and Ct 1 -2 are complementary signals Is to turn on the FET to which the Ή level signal is applied to transmit the signal applied to the common input terminal 1N to any one of the output terminals. The resistors R1 and R2 are equipped with the control terminals CU4 and CtK2 which are grounded to AC. The DC potential is to prevent the leakage of high-frequency signals through the gate. The circuit shown in Figure 1 is the use of GaAs shown in Figure 7 (B) (Please read the precautions on the back before writing (Blocks on this page) Assembly •. Order · FET 'is called SPDT (Single P The principle circuit of the compound semiconductor switch circuit device of ole Double Throw) has a slightly similar circuit configuration, except that the maximum difference point is to set the gate width Wg of FET1 and FET2 to 700 # m or less. 'The gap between the pad and the wiring layer The distance is greatly reduced. The reduction of the gate width Wg is smaller than in the past, which means that the FET's ON is increased. ○ 1 smart resistor, and the reduction of the gate area (Lgx Wg) also means that the gate wall is small and the gate M property and channel. Therefore, the parasitic capacity of the field-based junction bonding has a considerable difference in circuit operation and bureaucracy. The reduction in the distance between the pad and the wiring layer by the consumption of labor and consumption is to reduce the size of the cooperative 41 1 compound semiconductor wafer. A great contribution. The second figure printed by the company is an example of a compound semiconductor wafer in which the compound semiconductor switch circuit device of the present invention is integrated. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 312628 -Line 495989 A7 Description (8) ^ - configuration at the central portion of the GaAs substrate and the switching operation feti FET2 'among the FET in Table 1 Yuxiang Yang T 1, ό ο old ΓΑ ® connected resistors R1, R2?. The pads corresponding to the common input, input terminal 1N, output terminal ουτί, OUT2, control terminal Cu j Ctl-2, etc. are also arranged around the substrate. In addition, the second layer wiring shown by a dotted line is a gate metal layer S (Ti / Pt / Au) 20 formed at the same time when each FET gate electrode is formed, and the third layer wiring shown by a solid line is a connection of each element And a pad metal layer (Ti / Pt / Au) for forming a pad is performed. On the substrate of layer i, an ohmic metal layer (AuGe / Ni / Au) 10 in ohmic contact forms the source electrode, the gate electrode, and the lead-out electrodes at each end of each resistor in the ohmic contact. It is not shown because it overlaps with the pad metal layer. As can be seen from Figure 2, the components are only pads corresponding to ρ] ΕΤ1, FET2, resistors Rl, R2, common input terminals in, output terminals OUT1, OUT2, control terminals Ctl-1, Ctl-2, etc. Therefore, compared with the conventional compound semiconductor switch circuit device shown in FIG. 10, it is constituted with the minimum required components. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the present invention, the gate width of FET1 (also the same for FET2) is set to less than 700 // m, which is less than half of the conventional gate width. Half the size. That is, ρΕτι shown in FIG. 2 is formed in the rectangular channel area 12 surrounded by a one-point chain line. The third comb-shaped third pad metal layer 30 extending from the lower side is connected to the source 13 (or the drain) of the output terminal OUT1, and there is an i-th Mohm metal layer 10 below The formed source 14 (or drain). The third pad metal layer 30 in the shape of three combs extending from the upper side is connected to the non-electrode 15 (or source) of the common input terminal 1N, and there is a first layer of mho metal Paper size applies Chinese National Standard (CNS) A4 specification (210x297 mm) 8 312628 495989 V. Description of the invention (9) Drain 14 (or source) formed by layer 10. The two thunder-clad poles are arranged in a comb-like ring shape, and four sacrifice weaves are arranged therebetween, in the channel area of the gate electrode n formed by the second gate metal layer 20. Furthermore, since the intermediate comb-shaped electrode 13 (or source electrode) extending from above is shared by feti & fet2 ', it can be further miniaturized. The so-called gate width here is 70 or less, which means that the sum of the gate widths of the FET comb-shaped gates 17 is 7 0 0 // m or less, respectively. The cross-sectional structures of the above-mentioned FET1 and FET2 are the same as those of the conventional one shown in Fig. N (B), and therefore the description is omitted. Secondly, a possible design for omitting the shunt FET in the high-frequency band above 2.4 GHz and ensuring isolation is explained below. Fig. 3 shows the relationship between the gate width Wg and the insertion loss when the gate length Lg of the FET is 0.5 #m. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

When inputting a signal at 1 GHz, reducing the gate width Wg from looo # m to 600 " m results in degradation of insertion loss (Insertion Loss) of about 0.35 to 0.55dB and 0.2dB. When the input signal is only 2.4GHz, if the gate width Wg is shortened from 1000 # m to 600 // m, there will be insertion loss (Insertion Loss) of 0.6 to 0.65 dB and only 0_05 dB. This is because the insertion loss (Insertion Loss) is affected by the ON resistance of the FET when the input signal is 1 GHz, and the insertion loss (Insertion Loss) is less acceptable when the input signal is at 2.4 GHz. The reason for the impact. This is because the 2.4GHz input signal has a higher frequency than the 1GHz input signal. Therefore, the effect of the ON resistance of the FET is inversely smaller than the effect due to the capacitance component of the FET gate electrode. For this reason, for high-frequency waves above 2.4GHz, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 9 312628 495989 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. ) Because the capacitance component of the FET has a greater influence on the insertion loss (Insertion Loss) than the ON resistance, a design focusing on reducing the capacitance component is more effective than reducing the ON resistance. This is a completely opposite concept to the conventional design. Fig. 4 also shows the relationship between the gate width Wg and the isolation when the gate length Lg of the FET is 0.5 / zm. When the # sign is input to the right of 1GHz, the gate width is shortened from i〇〇〇 # m to 600 #m, which means that the isolation is improved from 19.5 to 23.5dB and 4.0dB. Similarly, when inputting a signal at 2.4GHz, if the gate width Wg is shortened from 1000 # m to 600 # m, the isolation of 14 to 18 dB and 4 (MB) is improved. That is, the isolation (Is) lati〇n) is improved with the ON resistance of the FET. Therefore, the high-frequency band above 2.4GHz can be known from Figure 3, considering the slight degradation of insertion loss (Insertion Loss), it is better to consider Figure 4 Isolation design can reduce the size of compound semiconductor wafers. In other words, when a 2.4GHz input signal has a gate width Wg of less than 7000, it can ensure an isolation of more than 5dB at i6, and A gate width Wg of less than 600 #m can ensure an isolation of more than 18dB (is〇iati〇n). In the compound semiconductor switch circuit device of the present invention in which the actual pattern is shown in Fig. 2, the gate length Lg is designed to be 0. 5 # m, gate width of 600 // m and uFET2 'to ensure insertion loss (ins Loss) of 0.65dB and isolation (ls〇lati〇n) of 18dB. This feature can be used as a Bluet00th (mobile phone, laptop pc, portable information Terminal, digital camera, and other two machines connected to each other wirelessly J This paper size applies to China National Standard (CNS) A4 specifications (2iGx 297 ^ jy 10 312628 (Please read the notes on the back before writing each page on this page) -丨 Installation, ordering · line 495989 V. Description of invention (η) and improving communication specifications of the active environment or working environment, etc.) 2 4〇1_ ^ frequency ISM Band (Industrial Scientific and Medical frequency band) spectrum diffusion communication application The communication switch in the field is utilized. The problem of further shortening the distance between the bonding pad and the wiring layer will be described later. Figures 2 and 6 show the brilliant structure of the compound semiconductor switch circuit device of the present invention. As shown in the top view of the figure, five pads including a common input terminal 1N, output terminals OUT1, OUT2, control terminals CtM, and CD-2 are arranged around the substrate. Each pad is shown in FIG. N + -type high-concentration area 40 provided along the upper periphery of the substrate 11 (indicated by a two-dot chain line in the second figure); most of it is provided on the intermetallic layer 20 on the substrate; and overlapped Gate metal layer The pad metal layer 30 on 20 is formed as a feature. Among them, the high-concentration area 40 is formed simultaneously in the ion implantation process for forming the source area and the drain area. Therefore, the fine gold wire 41 is On the pad metal layer 3 of the pad, spherical bonding is performed.) Thereby, it is different from the conventional case where all the pads are directly formed on the substrate u, and it is arranged on the surface of the substrate below the peripheral edge portion of the pad. High concentration areas ㈣. Therefore, it is different from the surface of the substrate u (semi-insulating, substrate resistance value · lx 107 Ω / cm) without impurities, and due to the high impurity concentration (ion species: 29Si, concentration to 5x 108 cm) 3) The empty layer on the periphery of the pad is not extended, so the distance between the pad and the adjacent wiring layer can be shortened from 20 // m to 5 # m to ensure the isolation of 20dB. 1 As shown in Figure 2, the pads of the common input terminal 1N are in addition to the size of the paper on which the Chinese National Standard (CNS) A4 specification (210 x 297 mm) is applied. 11 (correction page) 312628 (Please read the note on the back first) Please fill in this page again.) Order. 丨 • Line 丨-495989 A7 B7 V. Description of the invention (I2) One side is set to 40 in the concentration range, and the pads at the output terminals OUT1 and OUT2 are kept. The corner portion of the GaAs substrate is set, and a high-concentration area 40 in the shape of a € is arranged along its 4 sides, and the pads on the control terminals and cu_2, except for the corner portion of the GaAs substrate and the connection resistors R1 and R2, follow an irregular pentagon C-shaped high-concentration areas 40 are provided on the four sides. And the part without the high-concentration area 40 is facing the trowel on the periphery of the GaAs substrate. Therefore, although the empty layer is enlarged, a sufficient distance from the adjacent pads and wiring can be maintained to avoid leakage. The problem. Since the five pads occupy almost half of the semiconductor wafer, if the pad structure of the present invention is used, the wiring layer can be arranged near the pads, so that the semiconductor wafer can be reduced in size. As a result, the size of the compound semiconductor wafer of the present invention can be accommodated at 0.37 × 0.30 mm2, which means that the size of the conventional compound semiconductor wafer can be reduced by 20%. The compound semiconductor switch circuit device of the present invention has also achieved a variety of printed circuit characteristics improvement for consumer cooperatives of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Its-: The voltage standing wave ratio VSWR (V〇ltage Standing_Wave RaU〇) representing the reflection of high-frequency wave input power by the switch is 1.1 to 1.2. Since vsWR is the ratio of the maximum value and the minimum value of the voltage standing wave that occurs between the reflected wave and the input wave in the discontinuous part of the high-frequency wave transmission line, in the ideal state, the VSWR small system indicates that the reflection is zero. : In a conventional compound semiconductor switching circuit device having a shunt FET, its VSWR = about 1.4, and therefore, the voltage standing wave ratio is greatly improved in the present invention. The reason is that in the compound semiconductor switch circuit device of the present invention, only FET1 and FED are used in the high-frequency wave transmission line, because the M It standard is applicable to the Chinese National Standard (CNS) A4 specification (X 297 male cage) 12 312628 495989 Ministry of Economic Affairs • Intellectual property, bureau staff, printed by the cooperative A7 B7 V. Description of invention (D) Therefore, the circuit is simple, and an extremely small size FET is used in the device. Secondly, it indicates the linearity characteristic of the deviation level of the output signal of the high-frequency input signal, which is 30dBm when the PIN is 1dB. The linear characteristics of the input and output power of this wheel are shown in Figure 5. The ideal output-to-input power ratio is 1 'because the insertion loss (Insertion Loss) reduces the output power in this part. When the input power becomes larger, the output power can be deviated. The point where the output power of the input power drops by ldB is represented by PIN idB. For a compound semiconductor switching circuit device having a shunt FET, PiN 1dB is .26 dBm ', which is only 30 dBm in the compound semiconductor switching circuit device of the present invention without a shunt FET, and thus improved by about 4 dB or more. This is because when a shunt FET is used, it is affected by the multiplication of its 0FF switching and the pinch-off voltage of the shunt FET. In the present invention without a shunt FET, only It is affected by the switching FET that is OFF. [Effects of the Invention] As described above, the present invention has many effects as follows. First, focusing on the high-frequency band above 2.4GHz and omitting the shunt FETs to ensure isolation (Isolation), the concept of reducing the resistance of the conventional FET ON is adopted, and the gates of the FET1 and FET2 gates will be used for switching operations. The pole width Wg is set below 700 // m. As a result, the sizes of FET1 and FET2 used for switching operations can be reduced, insertion loss (Insertion Loss) can be suppressed to a small value, and the advantage of ensuring isolation (Isolation) can be obtained. Secondly, in the compound semiconductor switch circuit device of the present invention, it may be designed to omit the shunt FET structure. For this reason, its components only correspond to ------------------ ^ ---------------------- 、 Order --------------------% (Please read first (Notes on the reverse side are reproduced on this page.) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public dreams). 13 312628 495989 A7 B7 V. Description of the invention (14 Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs FET1 and FET2, resistors ri, r2, common input terminals 1N, wheel-out terminals OUT1, OUT2, control terminals, and Ctl_2 solder pads are printed. Therefore, the conventional compound semiconductor switch circuit device can be compared with the conventional one, which has the advantage of a minimum component structure. Third, because a high-concentration area is provided at the periphery of the pad, which occupies about half of the size of the semiconductor wafer, the wiring layer adjacent to the pad can be arranged to a limit close to 5 // m. Therefore, high-frequency wave signals can be combined. And the small space withstand pressure, has the advantage of a large shrinkage (shrink). Fourth, as mentioned above, it can minimize the components and pads and wiring The distance between the layers is shortened, and a semiconductor wafer size that is 20% smaller than that of a conventional compound semiconductor switching circuit device is obtained. Therefore, the price competitiveness with silicon semiconductor wafers can be greatly improved. Also, because the wafer size can be miniaturized, Assemble smaller components (SMCP6, 1.6 × 1 · 6χ, 0.75mm) than conventional small components (MCP6, x2 0 × 09nm). Fifth, at a height of more than 2.4GHz, by Park T In the old backhaul, its insertion loss (Insemon Loss) does not increase significantly. Therefore, the required isolation can be obtained by omitting the shunt. For example, in a 3GHz input signal, 'the gate width is set to 3 0 0 # m, also benefited from the benefit of Yahachi. 々 Ensuring sufficient isolation in the absence of shunt FETs. 6th In the compound semiconductor switch circuit device of the present invention, it stands for a switch that inputs power to high-frequency waves. The reflected voltage standing wave ratio w (Voltage Standing-Wave Ratio) can be]] t ',,, · · to 1 · 2, so that a switching component with less reflection can be provided. Seventh, in the invention of Yan was semiconductive "button _I semiconductor switching circuit device, the first read request may be - noted that the back side of the reading means and then fill the present block of each page Order • Line 14312628

Printed by the Ministry of Economic Affairs Hui • Property Co., Ltd. Λ Industrial Consumer Expenses Co., Ltd. Α7

Will indicate the output signal to high frequency

PlN ldB increased to 30dBm, characteristic. The linearity characteristic of the deviation level of the wave input signal. Therefore, the linearity of the switching device can be greatly improved. [Simplified description of the drawing] FIG. 1 is a circuit diagram illustrating the present invention. Figure 2 is a top view illustrating the present invention. Figure 3 is a diagram illustrating the characteristics of the present invention. Fig. 4 is a characteristic diagram illustrating the present invention. Fig. 5 is a characteristic diagram illustrating the present invention. Fig. 6 is a diagram for explaining the present invention. Fig. 7 is a diagram for explaining the conventional example. (A) sectional view and (B) circuit diagram of each block. -Figure 8 is an equivalent circuit diagram illustrating a conventional example. Brother 9 is a circuit diagram illustrating a conventional example. Fig. 10 is a plan view illustrating a conventional example. FIG. 11 is a (A) plan view and (B) a cross-sectional view illustrating a conventional example. [Explanation of component symbols] 1 GaAs substrate 2 N-type channel area 3 Schottky contact gate electrode 4 source 5 drain 10 ohm metal layer 11 substrate 12 channel area 13 drain 14 source (or drain) 15 source 16 Promise (or source) 17 Gate electrode 18 Source field 19 Drain field 20 Gate metal layer This paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 15 312628 Line 495989 A7 B7 V. Description of the Invention (I6) 30 ί Dry metal layer 40 South concentration field 41 line gold welding wire Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumption Cooperative Society Printed on paper The size of the paper is applicable to Chinese National Standard (CNS) A4 (210 x 297 mm) 16 312628

Claims (1)

495989 ONE ~~ • ONE '<, 495989 ONE ~~ • ONE' <, year W year (monthly deduction 丨 丨 '_You Di 9 0 1 1 2 5 9 (May 30, 91) 1. A type of compound semiconductor switch circuit device is formed on the channel layer surface with a source electrode, a gate electrode, and a non-electrode! And a rule D, and the source or The drain is connected as a common input terminal, and the two terminals or source terminals are S 1 and s 2 output terminals. Control signals are applied to the control terminals connected to the gates of the two FETs, so that the FETs on either side Is turned on to form a compound semiconductor switch circuit device in which the common input terminal and any of the first and second output terminals are signal paths, wherein the common input terminal, the first and second output terminals, and A high-concentration area is provided below the peripheral end portion of the pad of the upper control terminal so that the distance from other patterns of the compound semiconductor switch circuit device directly provided on the semi-insulating substrate is 20 // m or less. A GaAs substrate is used. For the above half The edge semiconductor substrate, and the above-mentioned channel layer is formed on the surface. 2. The compound semiconductor switch circuit device described in the first item of the patent application scope, which is adjacent to the above-mentioned solder pad portion, and surrounds the above-mentioned Those in the concentration field. 3. For the compound semiconductor switch circuit device described in item 丨 of the patent application scope, wherein the central portion of the pad is touched on the semi-insulating substrate and is not fixed, and is fixed to the central portion of the pad Crimp wiring. 4. If the compound semiconductor switch circuit device described in item 丨 of the scope of patent application is 312628, this paper size applies to China National Standard (CNS) A4 'grid (21 () χ 297ϋ) 495989 For the above-mentioned high-concentration areas, the diffusion areas of the source area and drain area are used. For example, the compound semiconductor switching circuit device described in item 1 of the patent application range, wherein the first and second FETs are formed by a gate electrode forming a shottky contact with the channel layer, and formed on the channel layer. The source and drain of an ohmic contact. Printed by the Staff Welfare Committee of the Central Bureau of Standards of the Ministry of Economic Affairs