535218 A7 B7 五 、發明說明（ 經濟部智慧財產局員工消費合作社印製 复JI之背景:發明曰係關於用於電子組件製造之半導體材料基板，尤 _ I Μ月確而舌，本發明係關於單晶矽晶 ® ’包含有減少自_雜且無空洞之背面的外延碎層。 在由恰克勞斯基（CzGehralski)法生長之單梦晶體之 ^多晶珍首先在具有或不具掺雜質之石英㈣内溶化。 ^夕晶碎已燒化且溫度平衝化後，種子結晶被浸入溶物内 然後萃取以在石英料旋轉時形成以㈣。單晶梦鍵塊 再被切成各個矽晶圓，其受到若干加工步驟，包括拋光/ 研磨、蚀刻及磨光，以產生具有如鏡般光澤之正面之最後 矽晶圓。& 了磨光正面以外’許多裝置廠商亦要求具有如 釦般光澤（磨光背面（該晶圓一般稱爲"雙面磨光"）。爲了 製備最後晶圓供裝置製造，@圓可實施化學汽相沈積法如 外延沈積法以在晶圓之正面上生長通常爲約^請與 200㈣厚之薄石夕層’使裝置可直接在外延層上製成。傳 外延沈積法揭示於美國專利5,9〇4,769號及5,769,942號。 外延沈積法通常包括二個步驟。在第一步驟中，在矽 圓裝入沈積室内並下向在旋轉晶座上後，晶圓之前面在 1150°C下施加清潔氣體如氫或氫/鹽酸混合物以"預烘焙,， 清潔硬晶圓之正面並除去該表面上之任何天然氧化物以谷 許外延碎層連續又均句地生長在正面上。在外延沈積法之 第二步驟中，曰%圓之前面在約腻或以上施加蒸氣狀矽 源如砂烷或三氣石夕烷以沈積並生長，夕之外延層在正面上。 在外延沈積法之二個步驟期間，石夕晶圓係藉旋轉晶 約 流 日曰 約 及 容 * V»-!^ ^ ----^---7 訂---------線· (請先閱讀背面之注意事項再填寫本頁) 4 本纸張尺度適ffl中國國家標準（CWS)A4規格（21〇 X 297公愛 A7 535218 五、發明說明（2 於外延沈積室内，旋轉晶座通常在過程中旋轉以確保外延 層之均勾生長。旋轉晶座通常由高純度石英所構成並具有 反化矽層全覆盍石英以減少在鬲溫過程中污物如自石英 釋出進人四周之量。用於外延生長之傳、统旋轉晶座爲先行 技藝已知者且述於美國專利4,322,592號，4,496,6〇9號， 5,200，157號，及5,242,501 號。 、在裝載過程期間，氣體可被截留在傳統旋轉晶座與晶圓 之間’、因爲晶圓會向下在旋轉晶座上，造成晶圓”漂浮”而以 不希望之位置滑動在旋轉晶座上（例如，部份離開凹面”袋 狀物”）。此可導致不均勻外延生長。此外，在預洪培步驟 期間，小量清潔氣體如氫氣可散佈在晶圓與旋轉晶座間之 =之晶圓邊緣四周，而進入晶圓與旋轉晶座間之空間内。 右晶圓之背面用氧化物層（通常約3〇〇〇A至約55〇〇入厚）密封 時，、散佈之氫氣不會與氧化物層充分反應而在層内產生針 孔或元全除去氧化物層。若背面爲許多裝置廠商希望之蝕 刻或磨光表面且僅具有薄天然氧化物層（通常爲約15人至 約30A)時，氫氣或氫/鹽酸混合物通常完全除去接近背面 外緣之天然氧化物層，其中清潔氣體散佈在晶圓四周，且 當蝕刻自晶圓之外緣向内移動時，在暴露矽表面之天然氧 化物層内產生針孔開口。此等針孔開口通常形成於晶圓之 圓周邊緣向内之環狀區内。 在外延沈積過程期間，小量切源氣體亦可散佈在晶圓 (、旋轉晶座間之晶圓邊緣四周並進入晶圓與旋轉晶座間之 2間内。若晶圓之背面被氧化物密封時，石夕膜之成核及生 -5- 本纸張尺度適用中國國家標準 .“丨^ ^ ----I----Γ 訂---------線. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 535218 A7 五、發明說明（3 ) 訂 長實質上會抑制。在天然氧化物層完全被清潔氣體蚀刻掉 (區内，生切之平滑連續層。然而，在清潔氣體尚未完 全除去天然氧化物層之區内，天然氧化物層内之針孔暴露 石夕晶圓並容許含硬源氣體沈積碎於針孔内，並在外延沈積 期間在晶圓後侧上產生非均勻♦膜。因此，對於僅具天然 氧化物層之蝕刻或磨光背面之晶圓，在預烘焙步驟期間， 產生於天然氧化物層内之針孔t導致在背面上之不連續矽 生長，其在亮光照明下出現模糊狀。此在晶圓背面上之模 糊狀態或"空洞"係由具有直徑爲約〇 5 _及爲約1〇_高 《小石夕生長或隆起物所構成。此等發之隆起物散射光且導 致換糊狀態可視爲不宜，因爲其會干涉機械觀測及光學高 溫測定系統’其在裝置加工時觀測晶圓之背面。空洞在亮 光下在雙面磨光晶圓之如鏡般光澤背面上藉雷射表面掃= 器特別可見於肉眼（參照圖12Α)。反之，單面磨光晶圓之 相當粗糙背面導致反射光之明顯程度之擴散散射，其可減 少空洞之外觀。 在外延矽層之高溫生長期間所遭遇之另一問題爲，在高 溫預烘焙及外延生長步驟期間，掺雜劑原子如硼或磷之向 外擴散通過碎晶圓之背面。使用傳統旋轉晶座，自背面向 外擴散之掺雜劑原子可散佈在晶圓邊緣與旋轉晶座之間朝 向卵圓之正面。此等摻雜劑原子會被包含且污染生長沈積 層並惡化晶圓邊緣附近之電阻率一致性。若晶圓之背面被 氧化物密封時，摻雜劑原子實質上不會自背面向外擴散。 然而’具有蚀刻或磨光背面之石夕晶圓在外延沈積過程期間 -6 - 本紙張尺度適用中關家標準（CNS)A4規格（210 X 297公爱 535218 A7 B7 經濟部智慧財產局員工消費合作社印制衣 五、發明說明（4 ) 圪受摻雜劑原子自背面之向外擴散，其導致正面之 動摻雜。 3 爲了嚐試消除背面空洞及自動摻雜，已提出若干方法。 爲了消除背面空洞。Nakamura (曰本未審查專利申請案 JP1 1-16844)揭示在晶圓裝入外延反應器以前，進行氟 剥除及/或高溫氫退火步驟高達丨〇日。該法增加額外加工 步驟，其會大大增加沈積過程之複雜性及成本。以以如等 人（美國專利5,960,555號）揭示一種藉利用具有機内通道之 旋轉晶座沿晶圓邊緣供導引洗滌氣體流至晶圓之邊緣來防 止正面之反應性源氣體散佈至晶圓背面之方法。此法要求 現存外延沈積室之實質修改並利用增加之洗滌氣體流動， 其可造成洗滌氣體溢出至正面並與源氣體混合，其會惡化 所得外延膜。 曰〜 爲了減少自動摻雜，Hoshi (曰本未審查專利申請案Jpu_ 87250)揭示在旋轉晶座之邊緣上使用眞空吸入以抽空旋轉 晶座邊緣上之硼摻雜劑並防止自動摻雜。此法會影響晶圓 邊緣一致性及厚度且需要對現存外延沈積系統作^質修 改。Nakamura (曰本未審查專利申請案Jpi〇_223545)揭示一 種改良旋轉晶座，在旋轉晶座之邊緣上具有狹縫，使向外 擴散之接雜劑原子會透過狹缝下推而進入廢氣中。此方法 亦谷Τ»午貫貝之沈積氣體被抽更在晶圓之背面下方，其可導 致珂述空洞影響以及廢氣系統之過早腐蝕與安全問題。 因此，迄今爲止，控制空洞對矽晶圓之背面的影響以及 在外延沈積過程期間與摻雜劑自背面之向外擴散相同之自 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 7訂· 線. 535218 經濟部智慧財產局員工消費合作社印製 A7 、發明說明（6 ) 晶圓之裝置。該裝置包括旋轉晶座，具有大小 一2上支持秒晶圓。旋轉晶座具有開口密度爲約。 = 與約4開口 W間之表面，…夕晶圓呈—般平2 Ϊ面 口容許流體流過表面供流體接觸碎晶圓之 層在：有：關2 #用於外延沈積法之裝置，其中外延矽 I持^ 面切晶®基板上生長。裝置包括室， = = 持裝置及支持晶圓支持裝… 入口及容；體、源氣及洗務氣體進入裝置之氣體 谷冲上述氣體離開裝置之氣體出口。 本發明之其他目的及牿 下將卩料見及部份指出。 可根據本發明用作原料之單晶矽晶圓之結構。 圓，，之具體例之俯視圖。 面内本發明晶圓支持裝置之具體例。^面所取之截 Ξ:=Γ!圓支持裝置之具體例之截面圖。 α明晶圓支持裝置之具體例之截面圖。 圖心室，顯示晶圓支持裝之具體例。 月〈外延反應室，顯示晶圓支持裝之具體例。 本纸張尺度適 297公釐） (請先閱讀背面之注意事項再填寫本頁) ¾ 丄ο535218 A7 B7 V. Description of the Invention (Background of Printing and Reprinting of JI by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: Invention is about semiconductor material substrates used in the manufacture of electronic components, especially ___________ months, the present invention is about Monocrystalline Silicon® includes an epitaxial fragmentation layer that reduces self-doped and void-free backside. Polycrystalline crystals grown in a single dream crystal grown by the CzGehralski method are first with or without dopants The quartz crystal is melted. ^ After the crystal grains have been burned and the temperature is flattened, the seed crystals are immersed in the solution and then extracted to form a crystal when the quartz material is rotated. The single crystal dream bond block is then cut into individual silicon. Wafers, which are subjected to several processing steps, including polishing / grinding, etching, and polishing to produce a final silicon wafer with a mirror-like front side. &Amp; Outside of the polished front side, many device manufacturers also require such buttons General gloss (polished backside (this wafer is generally called " double-sided polished "). In order to prepare the final wafer for device fabrication, @ 圆 may implement chemical vapor deposition methods such as epitaxial deposition to On the front The length is usually about 200 请 with a thin layer of thin stone, so that the device can be made directly on the epitaxial layer. The epitaxial deposition method is disclosed in US Patent Nos. 5,104,769 and 5,769,942. The epitaxial deposition method usually includes two In the first step, after the silicon circle is loaded into the deposition chamber and downward on the rotating wafer base, a clean gas such as hydrogen or a hydrogen / hydrochloric acid mixture is applied to the front surface of the wafer at 1150 ° C to pre-bake. Clean the front side of the hard wafer and remove any natural oxides on the surface. The epitaxial fragmentation layer grows continuously and uniformly on the front side. In the second step of the epitaxial deposition method, the front surface of the% circle is At about or above, a vaporous silicon source such as sarane or triazine is applied to deposit and grow, and the epitaxial layer is on the front surface. During the two steps of the epitaxial deposition method, the Shixi wafer is made by rotating the crystal. The date and time of the flying day * V »-! ^ ^ ---- ^ --- 7 Order --------- line · (Please read the notes on the back before filling this page) 4 papers Zhang Zhishi ffl Chinese National Standard (CWS) A4 specification (21〇X 297 public love A7 535218 V. Description of the invention (2 in extension In the deposition chamber, the rotating crystal base is usually rotated during the process to ensure the uniform growth of the epitaxial layer. The rotating crystal base is usually composed of high-purity quartz and has an anti-silicon layer and is covered with rubidium quartz to reduce the contaminants such as The amount released from the quartz into the surroundings of the person. The epitaxial growth and conventional rotating crystal holders are known in the art and described in U.S. Patent Nos. 4,322,592, 4,496,609, 5,200,157, and 5,242,501. During the loading process, gas can be trapped between the traditional rotating wafer base and the wafer ', because the wafer will be down on the rotating wafer base, causing the wafer to "float" and slide and rotate at an undesired position On the wafer (for example, partly off the concave "pocket"). This can lead to uneven epitaxial growth. In addition, during the pre-flooding step, a small amount of cleaning gas, such as hydrogen, may be scattered around the edge of the wafer between the wafer and the rotating wafer and enter the space between the wafer and the rotating wafer. When the back side of the right wafer is sealed with an oxide layer (usually about 3,000 A to about 55,000 in. Thick), the scattered hydrogen will not fully react with the oxide layer and cause pinholes or elements in the layer. Remove the oxide layer. When the back is an etched or polished surface that many device manufacturers want and only has a thin layer of natural oxide (usually about 15 people to about 30A), hydrogen or hydrogen / hydrochloric acid mixtures usually completely remove the natural oxide near the outer edge of the back Layer, in which the cleaning gas is scattered around the wafer, and when the etching moves inward from the outer edge of the wafer, a pinhole opening is created in the natural oxide layer exposing the silicon surface. These pinhole openings are usually formed in an annular region inwardly of the peripheral edge of the wafer. During the epitaxial deposition process, a small amount of cut source gas can also be scattered around the wafer (the edge of the wafer between the rotating pedestals and into the space between the wafer and the rotating pedestal. If the back of the wafer is sealed with an oxide ， The nucleation and production of Shixi film-5- This paper standard is applicable to Chinese national standards. "丨 ^ ^ ---- I ---- Γ Order --------- line. (Please first Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 535218 A7 V. Description of the invention (3) The length will be substantially suppressed. The natural oxide layer is completely etched away by the cleaning gas (in the area A smooth continuous layer of raw cutting. However, in areas where the cleaning gas has not completely removed the natural oxide layer, pinholes in the natural oxide layer expose the Shi Xi wafer and allow hard-containing gas to be deposited in the pinholes. A non-uniform film is produced on the backside of the wafer during epitaxial deposition. Therefore, for wafers with only an etched or polished backside of a natural oxide layer, during the pre-baking step, the Pinhole t causes discontinuous silicon growth on the back, which is in bright light A blur appears under the bright light. This blur state or "void" on the back of the wafer is composed of a small stone evening growth or bulge with a diameter of about 0.05 and a height of about 10_. These hairs The bumps scatter light and cause the paste exchange state to be considered inappropriate because it interferes with the mechanical observation and optical pyrometry system 'which observes the back of the wafer during the device processing. The cavity is polished on both sides by bright light as in a cavity The laser-like surface scanner on the mirror-like glossy back surface is particularly visible to the naked eye (see Figure 12A). Conversely, the rather rough back surface of a single-side polished wafer results in a significant degree of diffused scattering of reflected light, which can reduce the appearance of voids Another problem encountered during the high temperature growth of the epitaxial silicon layer is that during the high temperature pre-baking and epitaxial growth steps, dopant atoms such as boron or phosphorus diffuse out through the backside of the broken wafer. Using conventional spin crystals The dopant atoms that diffuse outward from the back can be scattered between the wafer edge and the front of the rotating wafer toward the front of the oval. These dopant atoms will be contained and contaminate the growth deposit and deteriorate Resistivity uniformity near the edge of the wafer. If the backside of the wafer is sealed with oxide, the dopant atoms will not substantially diffuse outward from the backside. However, a Shi Xi wafer with an etched or polished backside is epitaxial During the deposition process-6-This paper size applies the Zhongguanjia Standard (CNS) A4 specification (210 X 297 Public Love 535218 A7 B7 Printing of clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) Agent atoms diffuse outward from the back surface, which results in dynamic doping of the front surface. 3 In order to try to eliminate back surface voids and automatic doping, several methods have been proposed. In order to eliminate back surface voids. Nakamura (Japanese unexamined patent application JP1 1- 16844) reveals that before the wafer is loaded into the epitaxial reactor, fluorine stripping and / or high-temperature hydrogen annealing steps are performed for up to 0 days. This method adds additional processing steps, which can greatly increase the complexity and cost of the deposition process. For example, U.S. et al. (U.S. Patent No. 5,960,555) discloses a method of preventing a reactive source gas from spreading to the back of a wafer by using a rotating wafer base with an internal channel to guide the cleaning gas flow to the edge of the wafer along the edge of the wafer. Method. This method requires a substantial modification of the existing epitaxial deposition chamber and utilizes an increased flow of scrubbing gas, which can cause the scrubbing gas to overflow to the front and mix with the source gas, which can deteriorate the resulting epitaxial film. ~ In order to reduce automatic doping, Hoshi (Japanese unexamined patent application Jpu_87250) discloses the use of a hollow suction on the edge of a rotating wafer to evacuate boron dopants on the edge of the rotating wafer and prevent automatic doping. This method will affect the consistency and thickness of the wafer edge, and requires modification of the existing epitaxial deposition system. Nakamura (Japanese unexamined patent application Jpi0_223545) discloses an improved rotating crystal base with a slit on the edge of the rotating crystal base, so that the diffused dopant atoms will be pushed down through the slit to enter the exhaust gas. in. This method also evacuates the deposition gas of WuTangBei to the bottom of the wafer, which can lead to the effects of voids and premature corrosion and safety problems of the exhaust system. Therefore, to date, the effect of controlling voids on the backside of silicon wafers and the same self-calibration of dopants from the backside to the outside during the epitaxial deposition process are compliant with the Chinese National Standard (CNS) A4 specification (21〇X). 297 mm) (Please read the notes on the back before filling out this page) 7 Orders · Lines. 535218 A device for printing A7 and invention description (6) wafers by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The device includes a rotating wafer base with a size of 2 on a second wafer. The rotating crystal base has an opening density of about. = Surface with about 4 openings,… the wafer is in a normal level 2 The surface opening allows fluid to flow through the surface for the fluid to contact the layer of broken wafers: Yes: Off 2 #Equipment for epitaxial deposition method, Among them, epitaxial silicon I is grown on a dicing wafer® substrate. The device includes a chamber, = = holding device and supporting wafer support device ... Inlet and volume; gas, source gas, and cleaning gas entering the device. Valley punches the gas outlet of the gas leaving the device. Other objects and aspects of the present invention will be described and partially pointed out below. Structure of a single crystal silicon wafer that can be used as a raw material according to the present invention. Top view of a specific example of a circle. A specific example of the wafer support device of the present invention. ^ Surface taken 面: = Γ! Sectional view of a specific example of a circle support device. α is a cross-sectional view of a specific example of a wafer support device. The ventricle in the figure shows a specific example of wafer support. "Epitaxial reaction chamber" shows a specific example of wafer support. The size of this paper is 297 mm) (Please read the notes on the back before filling this page) ¾ 丄 ο
、發明說明（ 例 圖9爲本發明之外延反應室，圖1〇爲本發明之外延^^ 〇 •肩不日日0支持裝之具體 經濟部智慧財產局員工消費合作社印製 圖根據本發明生長之矽曰π μ # 電:Γ*傳统實際應用之圉表 延層之 背面密封掛，晶圓標圖，及圖12Β:】=生〈外延後無 外延密封物之晶圓標_。 發明產生之 圖13雜表面毫微表面狀態標圖， 面〈毫微..表面狀態。圖！ 3 A爲 卜k日曰0之則 圓# m 75 FI M u , 吏用傳統旋轉晶座產生之晶 Η 4^13Β爲使用多孔旋轉晶座產生之晶圓標圖。 ::顯示晶圓之氧沈澱輪摩’其 體例製備。 I ¥又狂八 圖 15 爲用於EPICENTURA,反應器（ApplledMatedals公司， = clara，加州)供定位晶圓在反應器内之機械裝置之概 :圖。在此圖中，旋轉晶座支持軸105與晶圓提升轴107 呈X換位置。 圖1 6爲用於EPI CENTURr反應器供定位晶圓在反應器 内之機械裝置之概略圖，其中旋轉晶座支持軸iq5及晶圓 提供升軸1 〇 7呈原始位置。 圖丨7爲用於EPI CENTURA®反應器供定位晶圓在反應器 内之機械裝置之概略圖。在此圖中，旋轉晶座支持軸1 〇 5 與晶圓提升軸1 0 7呈處理位置。 -10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --線· 535218 經濟部智慧財產局員工消費合作社印制农 A7 五、發明說明（8 圖18爲用於EPI CENTURA@反應器供定位晶圓在反應器 内之機械裝置之概略圖。此圖顯示當晶圓根據本發明被快 速冷卻以影響晶圓内之晶格空位輸廓時，旋轉晶座支持軸 1 〇 5與晶圓提升軸i 〇 7之較佳位置。 圖19爲用於EPI CENTURA@反應器供定位晶圓在圖以之 反應器内之機械裝置之俯視圖。 對應參考字元顯示整個附圖之對應部份。 1 佳是屬例之詳細説明 根據本發明，發展一種單晶碎晶圓，包含其上沈積有外 延矽層之實質上無自動掺雜之正面與無氧化物密封物及空 洞之背面。 A.珍晶圓基板 本發明之原料較佳爲單晶矽晶圓基板，其係自根據任何 傳統恰克勞斯其生長法之變易生長之單晶錠塊切成片。若 希望然氧之晶圓基板時，原料最好自根據任何傳統漂浮區 結晶生長法之變易生長之單晶錠塊切成片。生長矽錠塊以 及標準矽切片、拋光、蚀刻及磨光技術爲先行技藝中已知 者，且揭示於，例如，F· shimura，半導體矽結晶技術 (Academic press公司，1989);及矽化學蝕刻，（J Grabmaier， ed·，Springer-Verlag，紐約，1982)。 參知、圖1 ’單晶石夕晶圓1包含晶圓基板4，其較佳具有中 心軸8、正面3及通常垂直於中心軸之背面5，在正、背面 間之虛中心平面7，接合正面3與背面5之圓周邊緣2及自 中心軸延伸至圓周邊緣2之半徑9。背面沒有氧化物密封 -11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） •丨、—i-丨-—.—r 訂---------線 (請先閱讀背面之注意事項再填寫本頁) 8 IX 2 5 3 5 經濟部智慧財產局員工消費合作社印製 A7 ~~~~~~~----——---- 、發明說明（1〇 ) B·外延矽層 據本發明製備之單晶$晶圓包含其上沈積有外延梦層 :表面。外延層可沈積在全部晶圓上，或者，僅在部之晶 圓上。參照圖1，外延芦1 ο、v>择士曰 Λ 卜心層1 0 /尤積在晶圓之正面3上，較佳 曰曰圓《正個正面3上。是否較佳使外延層沈積在晶圓之 壬何其他部份上端視希望使用之晶圓而定。對於大部份應 用’外延層在晶圓之任何其他部份上之存在或不存在並 重要。 自广克勞斯基法製備之錠塊切片之單晶石夕晶圓之表面上 寺第八有、、、口曰曰產生之麻點（”c〇Ps,，）。然而，用於積體電路 製造之晶圓通常需要具有基本上無⑶ps構成之表面。具有 基本上無COP表面之晶圓可藉沈積外延矽層在晶元之表面 上製備。该外延層填滿C0ps，最後產生平滑晶圓表面。此爲 近來科學研究之主題。參照schmolke等人，The Electrochem Soc· Proc·，ν〇ΐ· PV98]，p 855 (1998); mr〇fumi 等人，咖 j Appl. Phys·，ν〇1· 36, ρ· 2565 (1997)。通常，晶圓表面上之 COPs係使用厚度爲至少約〇1 之外延矽層除去。較佳的 是，外延層具有厚度爲至少約〇1 Am且低於約2 。更佳 的疋’外延層具有厚度爲約〇·25 " m至約1 " m，最佳爲約 〇 · 5 // m 至約 1 a m。 須知，當外延層用於消除C〇ps以外之目的時，該目的需 要一種外延層厚度，其大於用來除去COPs之較佳厚度。例 如，若外延層除了消除COPs以外用以提供晶圓表面電性 時’外延層之厚度可高達約2〇〇 ju m。通常，提供電性沈積 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) € 訂· 丨線· 535218 A7 B7 五、發明說明（13) (請先閱讀背面之注意事項再填寫本頁) 稀有氣體（例如，He，Ne*Ar)，H2，HF氣體，HC1氣體或 二組合。更佳的是，清潔氣體包含Η 2或Η 2或H C 1之組合。 最佳的疋’清潔氣體基本上由Η 2組合。須知雖然可使用含 2又氛圍，但該氛圍較不佳，因爲其容易在表面上形成 氮化物，其會干擾後續表面上之外延沈積。清潔氣體之流 =通常爲約1升/分鐘與約5〇升/分鐘之間，較佳爲約1〇升/ 刀鐘與約2 〇升/分鐘之間，供至少約1 〇秒。 、暴露晶圓之背面至清潔氣體以除去天然氧化物層實質上 減少或消除空洞效應，其造成天然氧化物層内之針孔。換 : ’在生長外延矽前除去天然氧化物導致晶圓背面，在 日曰圓旦冗光或雷射表面掃描器下其上空洞不可見於肉 眼。 經濟部智慧財產局員工消費合作社印製 、在天然氧化物層之移除前或期間，晶圓較佳在不會造成 滑動之速率下加熱。明確而言，若晶圓被加熱太快時，熱 級別會發展，其會產生内部應力，足以在晶圓内造成不同 平面而互相相對移動（即，滑動）。在約75〇Ό至約8〇〇1以 下，印圓之快速加熱不會明顯造成滑動，但在約8〇〇_9⑼。c 至約115(M2〇(TC間之快速加熱晶圓則會造成滑動。頃發現 輕摻雜之晶圓（例如，摻有硼且具有電阻率爲約丨 約100 Ω-cm之晶圓）特別容易滑動。爲了避免此問題，晶 圓較佳在平均速率爲約2〇°C/秒至約35。〇/秒下，自約8〇〇_ 900°C加熱至氧化矽移除溫度。 在自晶圓之正、背面移除天然氧化物層I，中斷清潔氣 體之流動而反應室内之溫度調整至約6〇〇。〇與約⑻。〇之 16- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 535218 A7 B7 五、發明說明（14 濟 彗 員 工 消 費 ::較佳爲至少約11〇〇。。，更佳爲至少約ιΐ5〇。。。然後， 晶圓之^面與含矽之源氣體接觸以沈積外延層在正面上。 、疋在除去天然氧化物後，表面接觸源氣體歷3 〇秒 =下，更佳，約20秒以内，最佳爲約10秒以内。在移除 氧化石夕層後等待開始秒沈積約i Q秒容許晶圓之溫度穩定化 並變成一致。 外延沈積較佳由化學汽相沈積實施…般而言，化學汽 相沈積涉及暴露晶圓之表面至切之氛圍於外延沈積反應 器’例如，EPI CENTURA⑨反應器内（Applied Matedai^ 司， Santa Clara，加州）。在本發明之一較佳具體例中，晶圓之 表面暴露至包含矽之揮發性氣體（例如，sici4，siHc^， γ 2C12 SiH/l，或SiH4)之氛圍。氛圍較佳亦含有載子氣 to (最佳爲Η:)。在一具體例中，在外延沈積期間，矽源爲 SiE^Cl2或S1H4。右使用SiH^Cl2時，在沈積期間反應器壓力 較佳爲約500至約760托爾。另一方面，若使用時，反 應器壓力較佳爲約HK)托爾。最佳的是，在沈積期間石夕源 爲SiHClr此較其他源便宜得多。此外，可在大氣壓力下 進行使用SiHCl3之外延沈積。此較有利，因爲不需要眞空 泵，且反應器室不必太堅固以防崩溃。此外，安全上較二 顧慮且空氣泄入反應器室之機會較少。 在外延沈積期間，晶圓表面之溫度較好保持在足以防止 含矽 < 氛圍沈積多晶矽在表面上之溫度下。通常，在此期 間表面之溫度較佳爲至少爲約9〇(rC。更佳的是，表面之溫 訂 線 Ϊ -17- 本或張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 535218 A7 -------- B7____ 五、發明說明（17 ) 許加工氣體之流體流動至晶圓之正、背面。 (請先閱讀背面之注意事項再填寫本頁) 通常，外延沈積反應器包括一通常由石英構成之室、容 許處理氣體進入反應器之氣體入口、自反應器除去處理氣 把之氣體出口、加熱矽晶圓之加熱元件、支持晶圓之旋轉 晶座及支持旋轉晶座及晶圓之旋轉構件。在本發明中，旋 轉晶座一後用晶圓支持裝置取代，其容許流體接觸晶圓之 正面’除後晶圓之整個背面。有利的是，容許流體接觸晶 圓之正、背面實質上在負荷期間可消除”漂浮，，。此外，晶 圓支持裝置容許用外延層沈積法之預烘焙步驟之清潔氣體 實質上接觸矽晶圓之整個背面且實質上化學方式除去整個 天然氧化物層，因此，在外延層之生長期間，當源氣體接 觸矽晶圓之背面時，矽之平滑連續層會生長且背面上之空 洞效應會明顯減少或消除。此外，晶圓支持裝置容許包含 於矽晶圓内之摻雜劑原子在外延沈積過程期間自晶圓之^ 面向外擴散成爲自洗滌氣流中晶圓之正面負荷掉並離開廢 氣。消耗自外擴散之摻雜劑原子可防止實質量之摻雜劑散 佈在晶圓與旋轉晶座邊緣之間並接觸正面，導致正面之不 宜自動接雜。 經濟部智慧財產局員工消費合作社印製 晶圓支持裝置可以任何容許加工氣體’特別是清潔氣髀 及洗滌氣體接觸晶圓基板之背面之方式構成。晶圓支持^ 置可作成某種大小以容納任何直徑矽晶圓包括例如， mm ’ 2〇〇咖及3〇〇匪晶圓及更大。晶圓支持裝置可由傳 統材料如高純度石墨構成，用碳化矽或玻璃碳層覆蓋石奪、 以在高溫外延沈積過程期間減少污物自石墨釋入=圍= -20- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） 535218 A7 B7 五、發明說明（18 ) I。用以構成晶圓支持裝置之石墨通常爲至少約99%，更 佳爲至約99.9%，最佳爲至少約99.99%純石墨。又，石墨 車父佳含有低於約20 PPm全部金屬，特別是鐵、鉬、銅及 鎳’更佳爲低於約5 ppm全部金屬，特別是鐵、鉬、銅及 鎳。覆蓋石墨之碳化矽或玻璃碳塗膜具有厚度爲約75 至約150 "m，較佳爲約100 至約125 。類似於石墨，碳 化石夕或玻璃碳塗膜應具有全部金屬濃度爲低於約2〇 ppm， 較佳馬低於約5 ppm。 本發明之外延沈積反應器亦包括任意裝置以改良晶圓之 品質或加強料通過量。例如，邊環可定位在矽晶圓及/或 晶圓支持裝置之周邊外部，以藉絕緣晶圓之邊緣及/或在 其接觸晶圓表面前預熱流入室内之加工氣體來增強越過晶 圓之溫度一致性。此外，反應器亦可包括室分隔器，其加 強含矽源氣流與洗滌氣體之分離，藉以增加沈積法之效 率。類似於旋轉晶座，邊環及室分隔器通常由塗佈碳化石夕 或玻璃碳之石墨所構成。 E .多孔旋轉晶座 1 · 是圓散佈在内環狀凸緣上之多孔旋 在一特別組態或具體例中，晶圓支持裝置爲多孔旋轉晶 座。現參照圖2，顯示有多孔旋轉晶座1 2之截面圖。具有 内環狀凸緣13之多孔旋轉晶座12，其可支持具有正面3與 背面5之矽晶圓基板4。多孔旋轉晶座1 2具有多孔表面 14，具有複數孔或口 15，16，17，18，19, 20, z 1 及 2 2 〇 用於具有背面逢控處理之單晶圓反應器（例如，Appiied -21 - 本紙用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 7訂： -線 經濟部智慧財產局員工消費合作社印製 535218Description of the invention (Example: Figure 9 shows the extension reaction chamber of the present invention, and Figure 10 shows the extension of the present invention ^^ ○ • The shoulders are not supported every day. Supported by the Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumption Cooperative, printed drawings according to the present invention The growing silicon is called π μ # Electric: Γ * The traditional practical application of the back surface epitaxial layer is sealed on the back, the wafer map, and Figure 12B:] = the wafer label without epitaxial seal after epitaxy. Generated Figure 13 Miscellaneous surface state map of the surface, surface <nano .. surface state. Figure! 3 A is the first day of the day 0 # 之 则 圆 # m 75 FI M u The wafer 4 ^ 13B is a wafer map produced using a porous rotating crystal base. :: shows the preparation of the wafer's oxygen precipitation wheel friction. I ¥ Also crazy Figure 15 is for EPICENTURA, reactor (AppliedMatedals company , = Clara, California) Overview of the mechanical device for positioning the wafer in the reactor: Figure. In this figure, the rotating wafer support shaft 105 and the wafer lifting shaft 107 are X-positioned. Figure 16 is used for EPI CENTURr reactor is a schematic diagram of the mechanical mechanism for positioning the wafer in the reactor, in which the rotation The support shaft iq5 and the wafer lifting shaft 1 07 are in their original positions. Figure 7 is a schematic diagram of the mechanical device used in the EPI CENTURA® reactor for positioning the wafer in the reactor. In this figure, the rotating crystal The support shaft 1 〇5 and the wafer lifting shaft 1 107 are in the processing position. -10 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this Page)-Line · 535218 Printed Agricultural A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8 Figure 18 is a schematic diagram of the mechanical device used to position the wafer in the reactor at EPI CENTURA @ Reactor. This figure shows the preferred positions of the rotating wafer support axis 105 and the wafer lifting axis i 07 when the wafer is rapidly cooled in accordance with the present invention to affect the lattice vacancy profile in the wafer. Top view of the mechanical device in the reactor where the wafer is located at EPI CENTURA @ Reactor. Corresponding reference characters show the corresponding parts of the entire drawing. 1 Detailed description of the case According to the present invention, develop a Single-crystal shredded wafer including deposits thereon The epitaxial silicon layer has substantially no automatic doped front side and oxide-free sealant and cavity back side. A. Jane wafer substrate The raw material of the present invention is preferably a single crystal silicon wafer substrate, which is based on any traditional Klaus cuts single crystal ingots that grow easily. If oxygen substrates are desired, raw materials are best cut from single crystal ingots that grow easily according to any conventional floating zone crystal growth method. Wafers. Growing silicon ingots and standard silicon slicing, polishing, etching, and polishing techniques are known in the art and are disclosed in, for example, F. Shimura, Semiconductor Silicon Crystallization Technology (Academic press, 1989); and silicon Chemical Etching, (J Grabmaier, ed., Springer-Verlag, New York, 1982). Referring to FIG. 1, the single crystal evening wafer 1 includes a wafer substrate 4, which preferably has a central axis 8, a front surface 3, and a back surface 5 generally perpendicular to the central axis, and a virtual center plane 7 between the front and back surfaces. The circumferential edge 2 of the front surface 3 and the back surface 5 is joined, and a radius 9 extending from the central axis to the circumferential edge 2 is joined. No oxide seal on the back -11 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) • 丨, —i- 丨 -—.— r Order --------- line ( (Please read the notes on the back before filling this page) 8 IX 2 5 3 5 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ~~~~~~~ 1) B. Epitaxial silicon layer A single crystal wafer prepared according to the present invention includes an epitaxial dream layer: a surface deposited thereon. The epitaxial layer can be deposited on the entire wafer or only on the wafer. Referring to FIG. 1, the epitaxial reed 1 ο, v > Zeshi said Λ Buxin layer 10 / especially on the front side 3 of the wafer, preferably said circle "on the front side 3". Whether the epitaxial layer is preferably deposited on the other part of the wafer depends on the wafer to be used. The presence or absence of most applications' epitaxial layers on any other part of the wafer is not important. On the surface of the ingot slab of the ingot slab prepared from the Klaussky method, there are eight pits ("c0Ps,") on the surface of the wafer. However, it is used for Wafers manufactured by bulk circuits usually need to have a surface that is essentially free of CDps. Wafers with a surface that is essentially free of COP can be prepared by depositing an epitaxial silicon layer on the surface of the wafer. The epitaxial layer is filled with COps and finally smoothed. Wafer surface. This is the subject of recent scientific research. See schmolke et al., The Electrochem Soc · Proc ·, ν〇ΐ · PV98], p 855 (1998); mrófumi et al., Appl. Phys · ,, ν〇1 · 36, ρ · 2565 (1997). Generally, the COPs on the wafer surface are removed using an epitaxial silicon layer having a thickness of at least about 0. Preferably, the epitaxial layer has a thickness of at least about 0. 1 Am. And less than about 2. A better epitaxial layer has a thickness of about 0.25 m to about 1 m, and most preferably about 0.5 m to about 1 am. It should be noted that when the epitaxial layer is When used for purposes other than Copps, this purpose requires an epitaxial layer thickness that is greater than that used to remove COPs. Thickness. For example, if the epitaxial layer is used to provide wafer surface electrical properties in addition to eliminating COPs, the thickness of the epitaxial layer can be as high as about 200 μm. Generally, electrical deposition is provided. 13- This paper applies Chinese national standards (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) € Order · 丨 Line · 535218 A7 B7 V. Description of the invention (13) (Please read the precautions on the back before Fill out this page) Noble gases (eg, He, Ne * Ar), H2, HF gas, HC1 gas or a combination of two. More preferably, the cleaning gas contains 气体 2 or Η 2 or a combination of HC 1. Best 疋'The cleaning gas is basically a combination of Η2. It should be noted that although the atmosphere containing 2 can be used, the atmosphere is not good because it easily forms nitrides on the surface, which will interfere with epitaxial deposition on subsequent surfaces. The flow of cleaning gas = Normally between about 1 liter / minute and about 50 liters / minute, preferably between about 10 liters / knife clock and about 20 liters / minute, for at least about 10 seconds. Back-to-clean gas to remove natural oxide layer substantially reduces or eliminates voids Effect, which causes pinholes in the natural oxide layer. Change: 'Removing the natural oxide before growing the epitaxial silicon leads to the back of the wafer, and the holes above it are not visible to the naked eye under Japanese or Japanese red light or laser surface scanners. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, before or during the removal of the natural oxide layer, the wafer is preferably heated at a rate that does not cause slippage. To be clear, if the wafer is heated too quickly The thermal level will develop, which will generate internal stress, which is enough to cause different planes in the wafer to move relative to each other (ie, slide). Below about 7500 约 to about 8000, the rapid heating of the Indian circle does not cause significant slippage, but at about 8000_9⑼. c to about 115 (M2〇 (rapid heating of wafers between TC will cause slippage. Lightly doped wafers are found (for example, wafers doped with boron and having a resistivity of about 丨 about 100 Ω-cm) It is particularly easy to slide. To avoid this problem, the wafer is preferably heated from about 800-900 ° C to the silicon oxide removal temperature at an average rate of about 20 ° C / sec to about 35 ° / sec. The natural oxide layer I was removed from the front and back of the wafer, the flow of the cleaning gas was interrupted, and the temperature in the reaction chamber was adjusted to about 60.0 ° and about 20 °. 16- This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 535218 A7 B7 V. Description of the invention (14 Jihui employee consumption: preferably at least about 1 100 ..., and more preferably at least about 550 ... The surface of the circle is in contact with the silicon-containing source gas to deposit an epitaxial layer on the front surface. After removing the natural oxide, the surface contacts the source gas for 30 seconds =, preferably, within about 20 seconds, and most preferably Within about 10 seconds. Wait for the start of seconds after removing the oxidized stone layer and deposit about i Q seconds to allow the wafer temperature to stabilize Epitaxial deposition is preferably carried out by chemical vapor deposition ... In general, chemical vapor deposition involves exposing the surface of the wafer to the tangential atmosphere in an epitaxial deposition reactor ', for example, in an EPI CENTURA (R) reactor (Applied Matedai ^ (Santa Clara, California). In a preferred embodiment of the present invention, the surface of the wafer is exposed to an atmosphere containing a volatile gas containing silicon (eg, sici4, siHc ^, γ 2C12 SiH / l, or SiH4). The atmosphere is better to also contain the carrier gas to (preferably Η :). In a specific example, during epitaxial deposition, the silicon source is SiE ^ Cl2 or S1H4. When SiH ^ Cl2 is used on the right, the reactor is during the deposition The pressure is preferably about 500 to about 760 Torr. On the other hand, if used, the reactor pressure is preferably about HK) Torr. Most preferably, Shi Xiyuan is SiHClr during sedimentation, which is cheaper than other sources In addition, epitaxial deposition using SiHCl3 can be performed at atmospheric pressure. This is advantageous because no air pump is needed and the reactor chamber does not have to be too sturdy to prevent collapse. In addition, safety concerns and air leakage into the reaction Less opportunity During the epitaxial deposition, the temperature of the wafer surface is preferably maintained at a temperature sufficient to prevent silicon-containing atmospheric deposition of polycrystalline silicon on the surface. Generally, the surface temperature during this period is preferably at least about 90 (rC. More Preferably, the surface temperature setting line Ϊ -17- This or Zhang scale is applicable to China National Standard (CNS) A4 (210 X 297 mm) 535218 A7 -------- B7____ V. Description of the invention (17 ) Allow the fluid of the process gas to flow to the front and back of the wafer. (Please read the notes on the back before filling this page.) Generally, the epitaxial deposition reactor includes a chamber usually made of quartz, a gas inlet that allows the processing gas to enter the reactor, a gas outlet that removes the processing gas from the reactor, and a heater. Heating elements for silicon wafers, rotating wafer holders that support wafers, and rotating members that support rotating wafer seats and wafers. In the present invention, the rotating wafer holder is replaced by a wafer support device, which allows the fluid to contact the front side of the wafer 'except the entire back surface of the wafer. Advantageously, allowing the fluid to contact the front and back of the wafer substantially eliminates "floating" during the load. In addition, the wafer support device allows the cleaning gas from the pre-baking step of the epitaxial layer deposition method to substantially contact the silicon wafer The entire back surface is substantially chemically removed from the entire natural oxide layer. Therefore, during the growth of the epitaxial layer, when the source gas contacts the back surface of the silicon wafer, a smooth continuous layer of silicon will grow and the void effect on the back surface will be obvious. Reduce or eliminate. In addition, the wafer support device allows the dopant atoms contained in the silicon wafer to diffuse outward from the wafer's surface during the epitaxial deposition process to load off the front side of the wafer in the self-cleaning airflow and leave the exhaust gas. Consumption of dopant atoms that diffuse from the outside can prevent the dopant of real mass from being scattered between the wafer and the edge of the rotating wafer and contacting the front side, resulting in unfavorable automatic incorporation of the front side. The wafer support device can be constructed in any manner that allows the processing gas, especially the cleaning gas and the cleaning gas, to contact the back surface of the wafer substrate. The wafer support device can be made to a certain size to accommodate any diameter silicon wafer including, for example, mm '200mm and 300mm wafers and larger. The wafer support device can be composed of conventional materials such as high-purity graphite Cover the stone with a silicon carbide or glassy carbon layer to reduce the release of contaminants from the graphite during the high temperature epitaxial deposition process. = Wai = -20- This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇χ 297) (Centi) 535218 A7 B7 V. Description of the invention (18) I. The graphite used to form the wafer support device is usually at least about 99%, more preferably to about 99.9%, and most preferably at least about 99.99% pure graphite. Also, Graphite Chevron contains all metals below about 20 PPm, especially iron, molybdenum, copper, and nickel ', more preferably less than about 5 ppm of all metals, especially iron, molybdenum, copper, and nickel. Silicon carbide or graphite covered with graphite The glassy carbon coating film has a thickness of about 75 to about 150 " m, preferably about 100 to about 125. Similar to graphite, a carbon carbide or glassy carbon coating film should have a total metal concentration of less than about 20 ppm, It is preferably less than about 5 ppm. The epitaxial deposition reactor of the present invention Includes any device to improve wafer quality or enhance material throughput. For example, a side ring can be positioned outside the periphery of a silicon wafer and / or wafer support device to insulate the edge of the wafer and / or contact the wafer The processing gas flowing into the chamber is preheated in front of the round surface to enhance the temperature consistency across the wafer. In addition, the reactor can also include a chamber divider, which enhances the separation of the silicon-containing source gas stream from the washing gas, thereby increasing the efficiency of the deposition method. Similar to the rotating crystal base, the side ring and the cell divider are usually composed of graphite coated with carbonized stone or glassy carbon. E. Porous rotating crystal base 1 · It is a porous screw that is circularly scattered on the inner annular flange. In a special configuration or specific example, the wafer supporting device is a porous rotary crystal base. Referring now to FIG. 2, a cross-sectional view of the porous rotary crystal base 12 is shown. A porous rotary wafer holder 12 having an inner annular flange 13 can support a silicon wafer substrate 4 having a front surface 3 and a back surface 5. The porous rotating pedestal 1 2 has a porous surface 14 with a plurality of holes or ports 15, 16, 17, 18, 19, 20, z 1 and 2 2 0 for a single wafer reactor with a backside process (eg, Appiied -21-This paper uses Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the notes on the back before filling out this page)
五、發明說明（a) 經濟部智慧財產局員工消費合作社印製 佳1有密度爲約〇·2孔/cm2與約4孔/cm2，更佳爲約〇·8孔 /cm與約175孔/cm2之間。此處所用之密度意指均 均勻密度。 < 卜瓜較佳的是，多孔旋轉晶座内之孔實際上具有小直 ^ ’但不容許碳化矽或玻璃碳塗膜限制流體流過孔至矽晶 圓之月面。若旋轉晶座内之孔鑽入太大時，由局部化溫度 非均勻在背面上造成之晶圓正面上之毫微表面狀態問題會 發生。多孔旋轉晶座内之大直徑孔可導致熱點或冷點透過 位於矽晶圓下方之加熱燈之直接照射背面在矽晶圓背面上 之發展。此等熱或冷點造成溫度級別以形成橫過矽晶圓之 正面而可導致不均勻外延矽生長在矽晶圓之正面上。外延 白之不均勻生長明顯降晶圓品質。多孔旋轉晶座上之孔可 在七、斜角度下鑽入旋轉晶座内以進一步減少藉加熱燈直接 照射背面之可能性且形成熱或冷點導致不均勻外延生長在 正面上’但仍容許氣體滲透旋轉晶座並接觸背面且容許向 外擴散之摻雜劑原子自背面移走。爲了進一步減少形成熱 或冷點之潛力及由晶圓透過孔之直接照明在矽晶圓上溫度 級別之產生且減少或消除任何由提升針孔造成之或冷點， 在石夕to圓上下方之加熱燈之燈功率比可調整並調合以自燈 產生平衡熱。 現參照圖4，顯示在利用本發明之多孔旋轉晶座1 2之外 延生長過程期間使用之外延反應室3 0。多孔旋轉晶座i 2 接附至旋轉支持物3 1，3 2且具有大小及構型以在外延沈 積過程期間支持在内環狀凸緣丨3上之晶圓基板4。矽晶圓 -24 - 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） • -.1 1-----------：----Μ ^--------I —^wi (請先閱讀背面之注意事項再填寫本頁) -ϋ an I I n ϋ ϋ n ϋ ·1 ·1 n ϋ - 535218 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（23 ) 天然氧化物之移除^、* a u v "午千⑺連、·、貝外延矽層生長在矽晶圓背 Γ任何！：上.:其係在外延層之生長期間與源氣體接 因此實貝上消除任何背面上空洞之形成。此外，多孔 旋轉晶座内之孔容許惰性氣體或氫接觸晶圓之背面，使在 步ι與外延生長步碟期間自背面向外擴散之掺雜劑原 子會自石夕晶圓帶走並進入廢氣且實質上減少自動掺雜晶圓 正面之可能性。 2·遇~圓散佈查上之多孔旋轉晶庙 在本發明i替代具體例巾，乡孔旋轉晶座可具有大小及 構型以容許矽晶圓直接散佈在多孔表面上，因此消除内環 狀凸緣13，如圖4所示。現參照圖5，顯示有多孔旋轉晶 座又截面，其中矽晶圓直接散佈在多孔表面上。矽晶圓基 板4之背面5直接設置在多孔旋轉晶座4 〇之多孔表面4 i 上。雖然晶圓基板4之背面5直接與多孔表面4 1接觸，但 流動於多孔旋轉晶座4 〇下方之氣體可透過孔42，43，44， 45 ’ 46 ’ 47，48及49滲透多孔表面4丨且實質上接觸晶圓基 板4之整個背面5。 3 · 一晶一圓散佈在凹面多孔表面上之多孔旋轉晶座 在另一替代具體例中，圖5所示之實施例多孔旋轉晶座 可被進一步修改，使多孔表面以圓盤狀成形以僅容許矽晶 圓之外緣接觸多孔旋轉晶座。現參照圖6，顯示有多孔旋 轉晶座5 0之截面，其中矽晶圓直接散佈在旋轉晶座5 〇之 多孔表面5 1上。矽晶圓基板4之背面5直接設置於多孔旋 轉晶座50之多孔表面51上。多孔表面51形成如同圓盤， -26 (請先閱讀背面之注意事項再填寫本頁) ;% τ訂· 線‘ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 535218 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（24 ) 使石夕晶圓基板4之外緣2直接接觸多孔表面5 1而晶圓基板4 背面5之其餘部則未直接接觸多孔表面5 1。在使用時，孔 52，53，54，55，56，57及5 8容許流體流過其間至晶圓之 背面。 熟悉此技藝者認同的是，本發明之多孔旋轉晶座可與各 種沈積反應器包括桶式、薄餅式及迷你分批式反應器一起 使用而與所用之旋轉晶座之形狀無關。 F·基有延伸提升針之旋棘晶庙 現參照圖7，在本發明之替代具體例中，晶圓支持裝置 可爲傳統旋轉晶座6 0，其中至少三個提升針6丨_ 6 3仍呈延 伸或向上位置遍及整個外延沈積過程（即，在預烘妗及 延生長期間）。提升旋轉晶座6〇上方之秒晶圓容許^預烘 口期間導人外延沈積室3 Q内之清潔氣體以接觸並自晶圓基 板4之背面5除去天然氧化物層且防止化學汽相沈積引出之 =洞的形成。同樣’在外延矽層之生長期間導入外延沈積 室3 0内之洗條氣體可導引自昔 、 正面3並防止外延石夕層導之::二面雜5。釋放〈摻雜劑原子離開 G ·麗放式晶圓乞持裝署 在本發明之替代具體例中，晶圓被支持之方 上暴露晶圓之整個背面至直接 貫貝 式晶圓支持裝置）之輕射。使用外延沈'、=件（即，開放 圓支持裝置最好視特殊應用而定。例如，、門^開放式晶 物可容許晶圓更快地到達所欲：攻式晶圓支持 量。此外，開放式晶圓支持 二因而增加料通過 支持物可谷許晶圓較在容許更均勻 本紙張尺度翻巾關緖 •27 297^¾) (請先閱讀背面之注意事項再填寫本頁) € 訂.- -線· 535218V. Description of the invention (a) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 with a density of about 0.2 holes / cm2 and about 4 holes / cm2, more preferably about 0.8 holes / cm and about 175 holes / cm2. As used herein, density means uniform density. < It is preferable that the pores in the porous rotating crystal base actually have small straight ^ 'but do not allow the silicon carbide or glassy carbon coating film to restrict fluid flow through the pores to the full moon surface of the silicon crystal. If the hole in the rotating wafer is too large, the problem of nano surface conditions on the front side of the wafer caused by the localization temperature unevenness on the back side will occur. The large diameter holes in the porous rotating wafer base can lead to the development of hot or cold spots on the back of the silicon wafer through the direct irradiation of the backside of the heating lamp located below the silicon wafer. These hot or cold spots cause temperature levels to form across the front side of the silicon wafer and can cause uneven epitaxial silicon to grow on the front side of the silicon wafer. Epitaxial white uneven growth significantly reduces wafer quality. The holes on the porous rotating crystal base can be drilled into the rotating crystal base at an oblique angle of seven to further reduce the possibility of directly illuminating the back surface by the heating lamp and the formation of hot or cold spots leading to uneven epitaxial growth on the front surface. The gas penetrates the rotating crystal base and contacts the back surface and allows outdopant dopant atoms to be removed from the back surface. In order to further reduce the potential for the formation of hot or cold spots and the generation of temperature levels on silicon wafers by direct illumination of the through-holes of the wafer and to reduce or eliminate any cold spots caused by lifting pinholes, the upper and lower sides of the circle The lamp power ratio of the heating lamp can be adjusted and blended to generate balanced heat from the lamp. Referring now to Fig. 4, the use of an epitaxial reaction chamber 30 during the epitaxial growth process using the porous rotary crystal base 12 of the present invention is shown. The porous rotating pedestal i 2 is attached to the rotating supports 3 1, 3 2 and has a size and configuration to support the wafer substrate 4 on the inner annular flange 3 during the epitaxial deposition process. Silicon Wafer-24-This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) • -.1 1 -----------: ---- M ^- ------- I — ^ wi (Please read the notes on the back before filling out this page) -ϋ an II n ϋ ϋ n 1 · 1 · 1 n ϋ-535218 A7 Employee Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs Printed 5. Description of the invention (23) Removal of natural oxides ^, * auv " Wu Qianlian, ..., epitaxial silicon layer is grown on the silicon wafer back Γ any! : Up .: It is in contact with the source gas during the growth of the epitaxial layer. Therefore, the formation of any voids on the back surface is eliminated. In addition, the holes in the porous rotating crystal base allow inert gas or hydrogen to contact the back of the wafer, so that the dopant atoms that diffuse outward from the back during the step and epitaxial growth step will be taken away from the Shi Xi wafer and enter The exhaust gas substantially reduces the possibility of automatically doping the front side of the wafer. 2 · The porous rotating crystal temple on the circular distribution check is replaced by the specific example in the present invention. The rotary hole crystal base of the hole can have a size and configuration to allow the silicon wafer to be directly scattered on the porous surface, thus eliminating the inner ring. The flange 13 is shown in FIG. 4. Referring now to FIG. 5, there is shown a cross section of a porous rotating pedestal in which a silicon wafer is directly spread on a porous surface. The back surface 5 of the silicon wafer substrate 4 is directly disposed on the porous surface 4 i of the porous rotary crystal base 40. Although the back surface 5 of the wafer substrate 4 is in direct contact with the porous surface 41, the gas flowing below the porous rotating crystal base 4 can penetrate the porous surface 4 through the holes 42, 43, 44, 45 '46' 47, 48, and 49.丨 and substantially contact the entire back surface 5 of the wafer substrate 4. 3 · Porous rotating crystal holders scattered on a concave porous surface in one crystal. In another alternative embodiment, the porous rotating crystal holder in the embodiment shown in FIG. 5 can be further modified so that the porous surface is formed in a disc shape to only The outer edge of the silicon wafer is allowed to contact the porous rotating wafer base. Referring now to FIG. 6, there is shown a cross-section of a porous rotating crystal base 50, in which a silicon wafer is directly spread on a porous surface 51 of the rotating crystal base 50. The back surface 5 of the silicon wafer substrate 4 is directly disposed on the porous surface 51 of the porous rotary crystal holder 50. The porous surface 51 is formed like a disc, -26 (please read the precautions on the back before filling this page);% τ order · line 'This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 535218 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (24) The outer edge 2 of Shixi wafer substrate 4 is in direct contact with the porous surface 5 1 and the rest of the back surface 5 of wafer substrate 4 is not in direct contact. Porous surface 5 1. In use, the holes 52, 53, 54, 55, 56, 57 and 58 allow fluid to flow therethrough to the back of the wafer. Those skilled in the art agree that the porous rotating crystal holder of the present invention can be used with various deposition reactors including barrel, wafer, and mini-batch reactors regardless of the shape of the rotating crystal holder used. F. Rotary spine crystal temple with extended lifting pins Now refer to FIG. 7. In an alternative specific example of the present invention, the wafer support device may be a traditional rotating crystal holder 60, of which at least three lifting pins 6 丨 _ 6 3 It remains in an extended or upward position throughout the epitaxial deposition process (ie, during prebaking and extension growth). Raise the second wafer above the rotating wafer 60. Allow the clean gas in the epitaxial deposition chamber 3 Q during pre-bake to contact and remove the natural oxide layer from the back 5 of the wafer substrate 4 and prevent chemical vapor deposition. Leading out = formation of holes. Similarly, during the growth of the epitaxial silicon layer, the strip-washing gas introduced into the epitaxial deposition chamber 30 can be guided from the past, the front 3, and the epitaxial layer is prevented from leading to the second side: 5. Release (Dopant atoms leave G. Radiator wafers. In the alternative embodiment of the present invention, the entire back of the wafer is exposed on the side where the wafer is supported to the direct penetrating wafer support device.) Light shot. The use of epitaxial sinkers, pieces (that is, the open circle support device is best depending on the particular application. For example, the gate ^ open crystal can allow the wafer to reach the desired faster: off-wafer wafer support. In addition ， Open wafer support II. Therefore, it is possible to increase the amount of material through the support. The wafer can be more uniform than the paper size. (27 297 ^ ¾) (Please read the precautions on the back before filling this page). --Line · 535218
經濟部智慧財產局員工消費合作社印制衣 五、發明說明（％) 處理器所ΙΪ1 土 . 環狀、斤用者。現參照圖10，環支持物90較佳包含内 一 、彖9 1以支持晶圓基板4及外環狀階梯9 2，其作用極 :凸緣環以絕緣晶圓之圓周邊緣並預熱反應氣體以防滑 H· 積法之效率 盘右干實驗以評估製造本發明單晶晶圓之本發明方法 棘田1^效率。例如，約2.75鱗厚之外延層係使用典型旋 =座及多孔旋轉晶座沈積在具有電阻率爲約g•祕 、’’、0·01 Ω-cm之200 mm直徑摻硼晶圓基板上。現參照圖 1 1，可見具有背面氧化物密封物之晶圓具有實質上均勻㊉ =橫過晶圓表面。同樣，使用多孔旋轉晶座沈積在晶= 士而典背面氧化物密封物之外延層具有實質上均勻電 :::圓表面。然而，使用標準旋轉晶座沈積在晶圓上而 :二面二化物密封物之外延層具有不均勾電阻率橫過晶圓 表面-电阻率繪製之”w”形狀作爲表面位置之函數乃由於 大郅份加工變數如溫度及氣體流動之操縱以補償圓周邊緣 附近之自動摻雜而保持電阻率在可接受限制内。、、々 縱，電，從中心至約圓周邊緣10_^4二= 阻率於最後10 mm由於自動摻雜實質上會減少。例如，: 圓周邊緣向内1G_内之外延層之電阻率可減少約^至 2。。/二或約5。％或以上，端視基板與外延層之電阻率之= 異而定。 二 現參照圖12八，Tencor®SP1模糊標圖清楚顯示由 統支持台沈積外延⑦層在晶圓上而無背面氧化物密封^ -29 - 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .J.----1,---.--------一---Ί ^---------^ . (請先閱讀背面之注意事項再填寫本頁) _ 535218 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（27 ) 造成之背面空洞之位置。相對照地，圖1 2 B示出使用本發 明多孔旋轉晶座消除空洞而不用背面氧化物密封物。 現參照圖13 A，ADE® CR-83 SQM毫微表面狀態標圖清楚 示出使用傳統旋轉晶座導致外延層直接在具有亳微表面狀 態爲約60 nm之提升針孔上方。相對照地，圖1 3 b顯示使 用多孔旋轉晶座實質上減少外延層在提升針孔上方之毫微 表面狀怨至低於約20 nm。 評估三個具有不同孔大小，空間及密度之多孔旋轉晶座 之具體例供在外延沈積過程期間支持2〇〇 mm直徑矽晶圓。 各具體例具有大約等距孔，垂直鑽過底部以形成具有半徑 爲約9 5耄米之孔之圓柱型式。孔之數目及大小改變如下·· 多孔旋轉晶座A包含2 74個具有直徑爲約丨.32 mm之孔（孔 金度爲約0.95孔/ cm2);多孔旋轉晶座B包含5 4 8個具有直 徑爲約1.32 mm之孔（孔密度爲約195孔一1112);多孔旋轉晶 座C含274個具有直徑爲約丨.02 mm之孔（孔密度爲約〇95孔 / cm )。各具體例亦具有3個直徑爲約8爪爪之提升針孔，在 自旋轉晶座中心約90 mm鑽孔且隔開約12〇。。 使用則述多孔旋轉晶座製成具有矽外延層之許多矽晶 圓各曰曰圓均典背面2洞及正面上之自動摻雜。迄今結果 丁對万;不同孔岔度間之空洞或自動摻雜無任何優點。然 而，用旋轉晶座C，具有較小直接之孔的旋轉晶座製成之晶 圓上可見外延矽晶圓表面上之減少毫微表面狀態。明確而 言，使用旋轉晶座AU生長之具有约3 _厚外延層之晶圓 ·”>、在直接在孔上方之表面上之毫微表面狀態爲約2〇 nm (請先閱讀背面之注意事項再填寫本頁) 7訂· -30- 535218 A7 B7 五、發明說明（29) 造万法開始使高溫加工步驟之使用降至最小。雖然有些方 法保持足夠向溫加工步驟以產生剝蚀區及本 2密度，惟材料上之公差太緊以致無法提供市售產品。目 前其他高度先進電子裝置製造方法絲毫不含向外擴散步 驟。因爲在有源裝置區内形氧沈澱物相關之問題，所以此 等電子裝置製造廠必須使用晶圓，其不能在其加工條件下 在晶圓之任何地方形成氧沈澱物。結果I G潛力會失去。 然而，本發明容許在晶圓内形成晶格空位之模板，其造 成理心了均勻氧沈澱物之深度分佈，以在熱處理晶圓時开^ 成於晶圓内（參照wo 00/34999，2〇〇〇，6，15，刊出，併二 本文供參考）。通常，是否形成晶格空位之模板的決定部 份乃基於晶圓基板之組合物。明確而言，硼加強氧沈澱， 結果，重摻雜P型基板（例如，p+及p++基板）形成足夠2沈 澱物，使模板之形成通常不需要而輕摻雜1>型基板（例如，b P基板）通常需要模板之形成供I G目的。 圖14顯示該氧沈澱物分佈，其可藉熱處理根據本發明製 備之晶圓形成。在此特殊具體例中，晶圓基板4 (具有或不具 有沈積，面3上之外延層）之特徵在區”及％，（，，剥蝕區，，)〃， 其不具氧沈澱物9 5。此等區分別自正面3及背面5延伸 深f爲t及t，。較佳的是，t&t，各爲1〇至約1〇〇 ，更佳 的是，爲約50至約100 。在無氧沈澱物區”及^，之 間，有一區9 4，其含有實質上均勾濃度之氧沈殿物。對於 大部份應用，區94内之氧沈殿物濃度至少爲約5χι〇8沈㉛ 物w，更佳的是，爲約lxl〇9沈澱物w。須知，圖:’: -32- 本纸張尺度適用中國國家標準（CNS)A4規^i7〇 x 297公f l»n^n ϋ l~«n Ί ϋ ϋ it n n n · ϋ I (請先閱讀背面之注意事項再填寫本頁) 訂： 丨線. 經濟部智慧財產局員工消費合作社印制衣 535218 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（3〇 ,目的爲僅藉例示本發明之一具體例幫助熟悉此技藝者瞭 解本發明。本發明不限於該具體例。例如，本發明亦可被 用以形成僅具一個剝蝕區93之晶圓（代二個剥蝕區93及 93f) 〇 爲了形成晶格空位之模板，晶r通常先被加熱，然後在 速率爲至少約10C/秒下冷卻。加熱晶圓之目的爲：（昀形 成自行空隙及空位對（即，夫倫克爾缺陷）於晶格内，其被 均勻分佈遍及晶圓，及（1))溶解存在於晶圓内之不穩定氧 沈澱物成核中心。通常，加熱至較高溫度導故較大數之夫 倫克爾缺陷被形成。冷卻步驟之目的爲產生晶格空位之不 均勻分佈，其中S位渡度在或接近晶圓之中心爲最大，並 以晶圓之表面方向減少。據信此晶格空位之不均勻分佈係 由接近晶圓表面之一部份空位在冷卻期間擴散至表面因而 變成消失所造成，導致較低濃度之空位接近表面。 對於大部份應用，晶圓較佳加熱至浸泡溫度爲至少約 1175°C。更佳的是，其被加熱至浸泡溫度爲約12〇〇至约 1300°C，最佳爲約1225至約1250。(：。當晶圓之溫度到達所 欲浸泡溫度時，晶圓翠度較佳保持在浸泡溫度下—段 間。較佳期間通常爲約1 〇至約1 5秒。在目前典型市隹 延沈積反應器内，晶圓較佳保持在浸泡溫度爲約丨2至约 15秒。另一方面，在目前典型市售rta爐内，晶圓較佳 保持在浸泡溫度爲約1 0秒。 通常，晶圓被加熱，同時暴露至氛圍。在本發明之一 體例中，氛圍爲氧化氛圍，其包含H2〇及H2。然而，更^ -33- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） J J—,— (請先閱讀背面之注意事項再填寫本頁) ----.---•—訂---------線 0 535218 五 經濟部智慧財產局員工消費合作社€务Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (%) Processor 1 所 1. Referring now to FIG. 10, the ring support 90 preferably includes an inner ring 彖 1 9 1 to support the wafer substrate 4 and an outer ring step 9 2. Its function is as follows: the flange ring insulates the peripheral edge of the wafer and preheats the reaction. The efficiency of the method of the present invention for manufacturing the single crystal wafer of the present invention was evaluated by conducting a right-dried experiment on the efficiency of the gas with a non-slip H · product method. For example, an epitaxial layer of about 2.75 scale thickness is deposited on a 200 mm diameter boron-doped wafer substrate with a resistivity of about 1.00 Ω-cm using a typical spin-on seat and a porous spin crystal holder. . Referring now to FIG. 11, it can be seen that the wafer with the backside oxide sealant is substantially uniform ㊉ = across the wafer surface. Similarly, the epitaxial layer deposited on the backside of the oxide seal using a porous rotating crystal base has a substantially uniform electrical ::: round surface. However, the use of a standard rotating wafer is deposited on the wafer and the epitaxial layer of the dihedral sealant has uneven resistivity across the wafer surface-the "w" shape drawn by the resistivity as a function of surface position is due to Manipulation of large processing variables such as temperature and gas flow to compensate for automatic doping near the peripheral edge while keeping resistivity within acceptable limits. ,, 々 Vertical, electrical, from the center to about the peripheral edge 10_ ^ 4 2 = resistivity in the last 10 mm will be substantially reduced due to automatic doping. For example, the resistivity of the inner epitaxial layer can be reduced by about ^ to 2 if the peripheral edge is inward 1G_. . / Two or about 5. % Or more, depending on the resistivity of the substrate and the epitaxial layer = different. With reference to Figure 12A, the Tencor® SP1 fuzzy map clearly shows that the epitaxial layer is deposited on the wafer by the support desk without oxide seal on the back surface ^ -29-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) .J .---- 1, ---.-------- a --- Ί ^ --------- ^. (Please read the back first Please pay attention to this page before filling in this page) _ 535218 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Location of the back surface caused by the invention description (27). In contrast, Fig. 12B shows the use of the porous rotating crystal holder of the present invention to eliminate voids without using a back oxide seal. Referring now to FIG. 13A, the ADE® CR-83 SQM nanosurface state plot clearly shows that the use of a conventional rotating crystal base causes the epitaxial layer directly above a lift pinhole with a 亳 microsurface state of approximately 60 nm. In contrast, Fig. 13b shows that the use of a porous rotating crystal holder substantially reduces the nano-surface appearance of the epitaxial layer above the lift pinhole to below about 20 nm. Specific examples of three porous rotating wafers with different pore sizes, spaces, and densities were evaluated to support 200 mm diameter silicon wafers during the epitaxial deposition process. Each embodiment has approximately equidistant holes, which are drilled vertically through the bottom to form a cylindrical pattern with holes having a radius of about 95 mm. The number and size of the holes are changed as follows: Porous rotary crystal holder A contains 2 74 holes with a diameter of about 丨 .32 mm (pore gold degree is about 0.95 holes / cm2); porous rotary crystal holder B contains 5 4 8 It has pores with a diameter of about 1.32 mm (pore density is about 195 pores-1112); the porous rotating crystal base C contains 274 pores with a diameter of about .02 mm (pore density is about 0.95 pores / cm). Each specific example also has three lifting pinholes with a diameter of about 8 claws, which are drilled at about 90 mm in the center of the self-rotating crystal holder and spaced about 120 apart. . A plurality of silicon crystals with a silicon epitaxial layer are made using the porous rotating crystal base. The circular holes are each 2 holes on the back surface and automatic doping on the front surface. The results so far Ding Duanwan; there are no advantages in voids or automatic doping between different pore fork degrees. However, with the rotating wafer C, a crystal wafer made of a rotating wafer with a smaller direct hole has a reduced nano-surface state on the surface of the epitaxial silicon wafer. Specifically, a wafer having a thickness of about 3 mm thick using a rotating wafer AU ""> has a nano-surface state on the surface directly above the hole of about 20 nm (please read the Please fill in this page again for attention) 7th order -30- 535218 A7 B7 V. Description of the invention (29) The manufacturing method has begun to minimize the use of high temperature processing steps. Although some methods remain sufficient to warm processing steps to produce erosion Area and this 2 density, but the material tolerances are too tight to provide commercially available products. At present, other highly advanced electronic device manufacturing methods do not contain any outward diffusion steps. Because of the problems related to the formation of oxygen deposits in the active device area Therefore, these electronic device manufacturers must use wafers, which cannot form oxygen deposits anywhere on the wafer under their processing conditions. As a result, the IG potential is lost. However, the present invention allows the formation of lattice vacancies within the wafer. Template, which causes a uniform depth distribution of oxygen deposits to be formed in the wafer when the wafer is heat-treated (see wo 00/34999, 2000, 6, 15, published, and two This article (Reference). Generally, the part of the decision whether to form a template for the lattice vacancies is based on the composition of the wafer substrate. To be clear, boron enhances the oxygen precipitation, and as a result, heavily doped P-type substrates (eg, p + and p ++ substrates) Forming enough 2 precipitates for template formation is usually not required and lightly doped 1 > type substrates (for example, b P substrates) usually require template formation for IG purposes. Figure 14 shows the distribution of this oxygen precipitate, which can be heat treated The wafer prepared according to the present invention is formed. In this particular specific example, the characteristics of the wafer substrate 4 (with or without deposition, epitaxial layer on the surface 3) are in the regions "and%, (,, etched regions ,, ) 〃, it does not have an oxygen precipitate 9 5. These zones extend from the front 3 and back 5 respectively to a depth f and t. Preferably, t & t are each 10 to about 100, and more preferably about 50 to about 100. Between the "anaerobic sediment zone" and ^, there is a zone 94, which contains a substantially uniform concentration of oxygen sinks. For most applications, the concentration of oxygen sinks in zone 94 is at least about 5 × 08. The sediment w, more preferably, is about lxl09 precipitate w. Note: Figure: ': -32- This paper size applies the Chinese National Standard (CNS) A4 regulations ^ i7〇x 297 公 fl »n ^ n ϋ l ~ «n Ί ϋ ϋ it nnn · ϋ I (Please read the precautions on the back before filling out this page) Order: 丨 Line. Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative Printing 535218 Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperative A7 V. Invention Description (30), the purpose is to help those skilled in the art to understand the invention by exemplifying only one specific example of the invention. The invention is not limited to this specific example. For example, the invention can also be used In order to form a wafer with only one ablated region 93 (instead of two ablated regions 93 and 93f). In order to form a template for the lattice vacancies, the crystal r is usually first heated and then cooled at a rate of at least about 10C / sec. The purpose of heating the wafer is to: (昀 form self-contained voids and vacancy pairs (ie, Frenkel Trapped in the crystal lattice, which is uniformly distributed throughout the wafer, and (1)) the nucleation center of unstable oxygen precipitates present in the wafer. Generally, heating to a higher temperature leads to a larger number of husbands Runkel defects are formed. The purpose of the cooling step is to produce an uneven distribution of the lattice vacancies, where the S-site transition is greatest at or near the center of the wafer and decreases in the direction of the wafer's surface. It is believed that this lattice vacancy The uneven distribution is caused by a portion of the vacancies near the wafer surface spreading to the surface during cooling and thus disappearing, resulting in vacancies of lower concentration approaching the surface. For most applications, the wafer is preferably heated to the immersion temperature It is at least about 1175 ° C. More preferably, it is heated to a soaking temperature of about 12,000 to about 1300 ° C, and most preferably about 1225 to about 1250. (: When the temperature of the wafer reaches the desired soaking At the temperature, the wafer greenness is preferably maintained at the immersion temperature-interval. The preferred period is usually about 10 to about 15 seconds. In the current typical market deposition reactor, the wafer is preferably kept at immersion. The temperature is about 丨 2 to about 15 seconds. In the current typical commercially available rta furnace, the wafer is preferably kept at the immersion temperature for about 10 seconds. Generally, the wafer is heated while being exposed to the atmosphere. In one aspect of the present invention, the atmosphere is an oxidizing atmosphere. It includes H2〇 and H2. However, more ^ -33- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) JJ —, — (Please read the precautions on the back before filling this page) ----.--- • —Order --------- line 0 535218 Consumer Cooperatives of the Intellectual Property Bureau of the Five Ministry of Economic Affairs
A7 - -------____、發明說明（31 ) 的是，在氧化氛圍中之氧化劑爲氧氣，其係在濃度爲至少 約300 ppm (即，每1，000,0〇〇莫耳全部氣體“ο莫耳〇2)下 存在於氛圍内。更佳的是，氧濃度爲約3 〇 〇至約2〇〇〇 PPm，最佳爲約3 0 0至約500 ppm。氧化氛圍之其餘部份較 佳基本上由不會與矽表面或氧化劑反應之氣體所組成。更 佳的是，氣體之其餘部份基本上由稀有氣體或n2，更佳爲 稀有氣體，最佳爲Ar所組成。氧化氛圍在加熱期間最好暴 露至至少外延表面。更佳的是，氧化氛圍被暴露至基本上 晶圓之整個表面。 在本發明之另一具體例中，氛圍基本上無氧化劑。當形 成晶格空位之模板於外延反應器（如上所述）時，較佳爲基 本上典氧化劑之鼠圍’不論在晶圓上形成表面模糊之傾 向，由於安全方面之顧慮（避免爆炸）及粒子之產生，其在 氧化劑與未反應氣矽烷進入接觸時發生。基本上無氧化劑 之氛圍會包含還原氣體（例如，Η 2)及/或惰性氣體（例如， 稀有氣體如He，Ne，Ar，Kr及Xe)。較佳的是，氛圍基本上 由H2 ’ Ar及其混合物所組成。 在氧化氣圍内晶圓之熱處理後，迅速冷卻晶圓。此冷卻 步驟可便利地實施於相同氛圍内，其中進行熱處理。或 者’其較佳於不會與晶圓表面反應之氛圍之實施。較佳的 是’晶圓在速率爲至少約1 〇。〇 /秒下冷卻。更佳的是，晶 圓在速率爲至少約1 5 °C/秒，較佳爲至少約2 0 °C/秒，最佳 爲至少約5 0 °C /秒下冷卻。此快速冷卻速率較佳在晶圓之 溫度藉由晶格空位透過單晶矽擴散之溫度範圍減少時使 ..J--->Ί.---^------- (請先閱讀背面之注意事項再填寫本頁) 線· -34- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 535218 A7 B7 五、發明說明（32) 用。一旦晶圓冷卻至晶格空位相對地移動之溫度外之溫度 時，冷卻速率不會明顯地影響晶圓之沈澱特性，因此並非 (請先閱讀背面之注意事項再填寫本頁) 決定性。通常，晶格空位在大於約100(rc之溫度下相對地 移動。 在一特佳具fa例中，晶圓之平均冷卻速率，當其溫度從 浸泡溫度降低至低於浸泡溫度約l5〇t之溫度時，至少爲 約1 0 C /秒（更佳的是至少約1 5 °C /秒，仍更佳的是至少約 2 0 C/秒，最佳的是至少約5〇°C/秒）。在另一特佳具體例内， 晶圓之平均冷卻速率，當其溫度自浸泡溫度降至低於浸泡 μ度約250 C之溫度時，至少爲約1 〇°c/秒（更佳爲至少約151 /秒，仍更佳爲至少約20Ό/秒，最佳爲至少約5(rc/秒）。 -丨線· 加熱及快速冷卻可實施於，例如，任何數目之市售快速 熱退火（f’RTA’’）爐，其中晶圓係藉高電力燈之燈組加熱。 R 丁 A爐可快速加熱矽晶圓。例如，許多可在幾乎内可加熱 晶圓自室溫至1200°C。適當市售爐之例包括AG Ass〇ciates 公司（Mountain View，加州）之型號 61〇 爐及 Applied Matedals 公司（Santa Clara，加州）之 CENTURA⑧ RTP。 經濟部智慧財產局員工消費合作社印製 或者，加熱及快速冷卻可實施於外延沈積反應器内，但 其限制條件爲所欲冷卻速率可在反應器内達成。申請人等 決定加熱及冷卻步驟可實施於EPI CENTURA®反應器内。 參照圖15及圖19，該反應器包括支持晶圓之支持台1〇1。 支持台101固定安裝在旋轉晶座支持軸1〇5之臂1〇3上， 支持軸1 0 5滑動自如地安裝在晶圓提升軸丨〇 7之口徑丨〇 6 内。曰日圓k升軸被士裝供垂直移動在反應器之下圓頂（圖 -35- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 535218 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（33 ) 未示）内之圓柱形開口内。氣動機構（圖未示）可操作以視 需要一起或單獨地垂直移動旋轉晶座支持軸1 〇 5及晶圓提 升軸1 0 7。機構進一步可操作以轉動旋轉晶座支持軸1 〇 5 在口徑1 0 6内，使旋轉晶座1 〇 1與晶圓可轉動。旋轉晶座 包括鋼針1 0 9，可滑動自如地安裝於旋轉晶座中之開口 内，以在其下端嚙合晶圓提供軸之止塊丨丨1。針丨〇 9之上 端可支持晶圓。傳統上，針1 09僅在轉移來回反應器期間 用以支持晶圓。 爲了定位晶圓供EPI CENTURA®反應器内之熱處理，晶 圓例如藉具有大小安裝在鋼針丨〇 9間之刮刀u 3輸送至反 應器（參照圖1 9)。旋轉晶座支持軸丨〇 5及提升軸丨〇 7自圖 1 5所示之父換位置向上移至圖1 6所示之原來位置。旋轉 晶座支持軸105之向上運動造成針1〇9 (其與晶圓提供軸 1 0 7嚙合）嚙合晶圓之背面並提升晶圓離開刮刀i i 3。然後 刮刀自反應器移除。參照圖1 7，旋轉晶座支持軸丨〇 5進一 步被向上移動，而晶圓提升軸丨〇 7仍靜止不動。此造成針 109相對於旋轉晶座101向下滑動，直到旋轉晶座工“之 上表面進入接觸晶圓隽止。之後，旋轉晶座丨〇丨支持晶 圓。同時，支持軸105連續向上移動，直到旋轉晶座1〇\ 與環115爲共同平面爲止。此時，旋轉晶座呈加工位置。 然後起動高電力燈之燈組(圖未示)以加熱晶圓，同時其係 藉加工位置之旋轉晶座丨〇丨支持。較佳的是，旋轉晶座 1 0 1與晶圓被旋轉且加熱，使晶圓會更均勾地加熱。叫 傾發現晶圓於EPI CENTURA®反應器内之典型平均冷卻 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公ί ---- "J---,-J---*------- (請先閱讀背面之注意事項再填寫本頁) · -·線- 535218 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（34 ) 速率（即，约1 〇至1 5 C /秒）傾向於遠低於可在晶格室位相 對地移動之溫度下於R T A爐内達成之典型平均冷卻速率 (即，約7 0至1 〇 〇 C/秒）。此郅份乃由於與晶圓接觸之旋轉 日口座101 (參照圖i 7)在完成加熱後有時仍熱之事實。因 此，爲了増加冷卻速率，晶圓較佳爲移動至儘量遠離旋轉 晶座1011位置。此可在完成加熱後立刻旋轉晶座支持軸 1 0 5降至圖1 8所示之交換位置達成。在交換位置中，晶圓 僅由針1 0 9支持，使晶圓之實質上所有背面及所有正面不 接觸任何其他固態熱表面（除了針1 0 9以外）。此外，晶圓 儘f返離熱旋轉晶座丨〇丨定位。藉提升晶圓離開旋轉晶座 1 (H，晶圓 < 冷卻速率會大約加倍（即，平均冷卻速率從範 圍爲約1 0至1 5 C/秒增至範圍爲約2 5至約3 〇。〇/秒）。 、在另一具體例中，所欲冷卻速率可在外延沈積反應器内 i-成/、包含開放式背面晶圓支持裝置，例如上述針支持 物或環支持物。藉使用開放式背面晶圓支持裝置，消除旋 2晶座之絕緣功率，可加熱並更快速冷卻晶圓。明確而 二’相對照於支持在旋轉晶座上之提升針上之晶圓，並通 常在速率爲約25至約3(rC/#不冷卻，在針支持物或環支 持物上足晶圓通常在速率爲約7 〇至約1 〇 〇秒下冷卻。 開放式背面晶圓支持裝置較佳，因爲產生剝蝕區之熱加工 可併入外延沈積法中而不用提升晶圓在可能損害晶圓之針 上之的附加物理接觸。 /艮據本發明製備之不均w位構型爲隨後加熱晶圓時供 虱沈積 <楗板。明確而言，當加熱晶圓基板4(參照圖14) (請先閱讀背面之注音？事項再填寫本頁} € --線· -^7 _A7--------____, invention description (31) is that the oxidant in the oxidizing atmosphere is oxygen, which is at a concentration of at least about 300 ppm (that is, every 1,000,000,000 moles The entire gas is present in the atmosphere. More preferably, the oxygen concentration is from about 3,000 to about 2000 ppm, and most preferably from about 300 to about 500 ppm. The remaining part is preferably basically composed of a gas which does not react with the surface of silicon or an oxidant. More preferably, the remaining part of the gas is basically composed of a rare gas or n2, more preferably a rare gas, and most preferably Ar Composition. The oxidizing atmosphere is preferably exposed to at least the epitaxial surface during heating. More preferably, the oxidizing atmosphere is exposed to substantially the entire surface of the wafer. In another embodiment of the invention, the atmosphere is substantially free of oxidants. When When the template for forming the lattice vacancies is used in the epitaxial reactor (as described above), it is preferable that the perimeter of the oxidant is basically the same. Regardless of the tendency of the surface to be blurred on the wafer, safety concerns (avoid explosion) and particles Produced by the reaction between oxidant and unreacted gas silane. Occurs during contact. A substantially oxidant-free atmosphere will contain reducing gases (eg, Krypton 2) and / or inert gases (eg, noble gases such as He, Ne, Ar, Kr, and Xe). Preferably, the atmosphere is basic It consists of H2 'Ar and its mixture. After the heat treatment of the wafer in the oxidizing gas, the wafer is quickly cooled. This cooling step can be conveniently implemented in the same atmosphere where the heat treatment is performed. Or' It is better than The implementation of an atmosphere that will react with the surface of the wafer. It is preferred that the wafer is cooled at a rate of at least about 100.0 / sec. More preferably, the wafer is cooled at a rate of at least about 15 ° C / sec. , Preferably at least about 20 ° C / sec, and most preferably at least about 50 ° C / sec. This rapid cooling rate is preferably at a temperature at which the wafer temperature diffuses through the single crystal silicon through the lattice vacancies When the range is reduced: J --- > Ί .--- ^ ------- (Please read the precautions on the back before filling out this page) Line · -34- This paper size applies Chinese national standards (CNS) A4 specification (210 X 297 mm) 535218 A7 B7 V. Description of the invention (32) Use. Once the wafer is cooled to the lattice empty At a temperature other than the relative moving temperature, the cooling rate will not significantly affect the precipitation characteristics of the wafer, so it is not (please read the precautions on the back before filling this page). Decisive. Generally, the lattice vacancy is greater than about 100 ( rc moves relatively at the temperature. In a special case, the average cooling rate of the wafer is at least about 10 C when the temperature of the wafer decreases from the immersion temperature to a temperature lower than the immersion temperature of about 150 t. Per second (more preferably at least about 15 ° C / second, still more preferably at least about 20 ° C / second, and most preferably at least about 50 ° C / second). In another particularly preferred embodiment, the average cooling rate of the wafer is at least about 10 ° c / sec (more preferably at least when the temperature of the wafer is reduced from the immersion temperature to a temperature below the immersion μ degree of about 250 C). About 151 / second, still more preferably at least about 20 Ό / second, and most preferably at least about 5 (rc / second).-Line heating and rapid cooling can be performed, for example, on any number of commercially available rapid thermal annealing ( f'RTA '') furnace, in which the wafer is heated by a high-power lamp. R D-A furnace can quickly heat silicon wafers. For example, many can heat the wafers from room temperature to 1200 ° C within almost. Examples of suitable commercially available furnaces include Model 61o furnaces from AG Assciates (Mountain View, California) and CENTURA⑧ RTP from Applied Matedals (Santa Clara, California). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs or heated And rapid cooling can be implemented in the epitaxial deposition reactor, but the limitation is that the desired cooling rate can be achieved in the reactor. The applicant and others have decided that the heating and cooling steps can be implemented in the EPI CENTURA® reactor. Refer to Figure 15 and Figure 19, the reaction Including support table 101 for supporting wafers. The support table 101 is fixedly mounted on the arm 10 of the rotating wafer support shaft 105, and the support shaft 105 is slidably mounted on the wafer lifting shaft. Caliber 丨 〇6. The Japanese Yen k-liter shaft is fitted for vertical movement under the reactor dome (Figure-35- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 535218 Economy Printed by A7 B7 of the Consumer Cooperatives of the Ministry of Intellectual Property Bureau. 5. In the cylindrical opening in the description of invention (33). Pneumatic mechanism (not shown) can be operated to move the rotating crystal holder vertically together or separately as needed. Axis 10 and wafer lifting axis 107. The mechanism is further operable to rotate the rotary wafer support shaft 1.05 within a diameter of 106, so that the rotary wafer 100 and the wafer can be rotated. The rotary wafer It includes a steel pin 10, which can be slidably installed in an opening in a rotating crystal base to engage the wafer stopper of the wafer at its lower end 丨 丨 1. The upper end of the needle 丨 09 can support the wafer. Traditionally Needle 1 09 is used to support the wafer only during transfer to and from the reactor. The wafer is positioned for heat treatment in the EPI CENTURA® reactor. For example, the wafer is conveyed to the reactor by a scraper u 3 with a size installed between steel pins 丨 09 (see Figure 19). Rotating wafer support shaft 丨 〇5 And the lifting axis 丨 〇7 moved upwards from the position shown in Figure 15 to the original position shown in Figure 16. The upward movement of the rotating wafer support shaft 105 caused the needle 10 (which is in line with the wafer supply axis 1 0 7 Engage) Engage the back of the wafer and lift the wafer away from the scraper ii 3. The scraper was then removed from the reactor. Referring to FIG. 17, the rotating wafer support shaft 5 is further moved upward, and the wafer lifting shaft 7 is still stationary. This causes the needle 109 to slide downward relative to the rotating wafer base 101 until the upper surface of the rotating wafer base enters the contact wafer. After that, the rotating wafer base supports the wafer. At the same time, the supporting shaft 105 moves upward continuously. Until the rotating wafer base 10 and the ring 115 are in the same plane. At this time, the rotating wafer base is in the processing position. Then start the lamp set (not shown) of the high-power lamp to heat the wafer, and it is based on the processing position. Rotary wafer holders 丨 〇 丨 support. It is better that the rotary wafer holder 101 and the wafer are rotated and heated, so that the wafer will be heated more evenly. It is found that the wafer is inside the EPI CENTURA® reactor. The typical average cooling size of this paper applies to China National Standard (CNS) A4 specifications (21G X 297) ---- " J ---,-J --- * ------- (Please read first Note on the back, please fill in this page again) · · · Line-535218 Printed A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (34) The rate (ie, about 10 to 15 C / sec) tends to be far Below the typical average cooling rate achieved in an RTA furnace at temperatures that can be moved relatively in the lattice compartment (i.e. (Approximately 70 to 100 ° C / sec). This is due to the fact that the rotating sundial holder 101 (see Fig. I 7) which is in contact with the wafer sometimes remains hot after heating is completed. Therefore, in order to increase the cooling rate, The wafer is preferably moved to a position as far away as possible from the rotating wafer base 1011. This can be achieved by rotating the wafer support shaft 105 immediately after completion of heating to the exchange position shown in FIG. 18. In the exchange position, the wafer is only Supported by pin 10, so that virtually all backsides and all front sides of the wafer do not contact any other solid thermal surface (except pin 10 9). In addition, the wafer is returned as far as possible from the thermal rotation wafer 丨 〇 丨 positioning By lifting the wafer away from the rotating wafer seat 1 (H, the wafer < cooling rate will be approximately doubled (ie, the average cooling rate will increase from a range of about 10 to 15 C / sec to a range of about 25 to about 3 〇 / 〇). In another specific example, the desired cooling rate may be i- / in the epitaxial deposition reactor, including an open back wafer support device, such as the above-mentioned needle support or ring support. Eliminates the insulation power of the spin-on 2 wafer by using an open back wafer support The wafer can be heated and cooled faster. Clear and two 'compared to wafers supported on a lift pin on a rotating wafer base, and usually at a rate of about 25 to about 3 (rC / # without cooling, in the needle The support or ring support foot foot wafer is usually cooled at a rate of about 70 to about 100 seconds. An open back wafer support device is preferred because the thermal processing that produces the ablated area can be incorporated into the epitaxial deposition method. Without increasing the additional physical contact of the wafer on the pins that may damage the wafer. / The uneven w-position configuration prepared according to the present invention is for lice to deposit <楗 plates when the wafer is subsequently heated. Specifically, when heating the wafer substrate 4 (refer to FIG. 14) (Please read the note on the back? Matters before filling out this page} €-line ·-^ 7 _
535218 A7 B7 五、發明說明（35 ) 時，氧會快速聚集以在含有較高空位濃度之晶圓基板4之 區94内形成沈澱物95，但不會聚集在接近含有較低命位 „晶圓表面3’5之區93’93,内。通常，氧在溫：爲 5 00至約800 C下成核，且在溫爲約7〇〇至約1〇〇〇乇下生長 沈澱物。因此，例如’氧沈澱物95在晶圓内之不均勻分 會在電子裝置製造方法之熱處理循環期間形成，假使該熱 處理循環時常在溫度接近8〇0。〇下進行。 … 晶格空位在晶圓内之模板的形成及隨後氧沈殿可在晶圓 及/或裝置製造過程期間任何時刻進行，但其限制條件爲 較後之加工步驟不會消除氧沈澱成核中心/氧沈澱物(例 如，後續加熱晶圓至充分溫度歷時短至足以將成核中心/ =沈殿物溶解人碎内）。在本發明之—較佳具體例中，晶 格空位之模板及核核中心/氧沈殿物之形成發生在沈積外 延層之後。例如，如上所述’晶格空位之模板係在外延沈 積之晶圓製造過程期間形成而成核/沈澱則在電子裝置製 造過程之熱處理循環期間進行。在另_具體例中，晶格空 模板及成核中心/氧沈戮之形成發生在外延層之沈積 ::成核中心’氧沈澱係藉加熱晶圓至一溫度歷時足以生 =成核中心/氧沈澱大至足以存在於任何後續熱處理（即， 成核中心/乳沈澱之半大於”臨界半徑”）而形成。 #於上述，可見本發明之苦千3 π丄 月之右十目的皆已達成。因爲在不 :離本發明之範圍以外，可對上述多孔旋轉晶座作各種改 =所以希望是上迷所含之所有事物闡明爲例示性而非限 制性。 (請先閱讀背面之注意事項再填寫本頁) · -丨線· 經濟部智慧財產局員工消費合作社印製 -38 -535218 A7 B7 5. In the description of the invention (35), oxygen will rapidly accumulate to form a precipitate 95 in the region 94 of the wafer substrate 4 containing a higher vacancy concentration, but will not accumulate near the crystals containing a lower life position. The region 3'5 of the round surface is 93'93, inside. Generally, oxygen is nucleated at a temperature of about 500 to about 800 C, and a precipitate is grown at a temperature of about 700 to about 1000 ° F. Therefore, for example, the uneven distribution of the oxygen precipitate 95 in the wafer will be formed during the heat treatment cycle of the electronic device manufacturing method, provided that the heat treatment cycle is often performed at a temperature close to 80.000.... The formation of the template inside and subsequent oxygen sinking can be performed at any time during the wafer and / or device manufacturing process, but the limitation is that later processing steps will not eliminate the oxygen precipitation nucleation center / oxygen deposits (e.g., subsequent The wafer is heated to a sufficient temperature for a short period of time sufficient to dissolve the nucleation center / = Shen Dianwu dissolved in human debris). In the preferred embodiment of the present invention, the template of the lattice vacancy and the formation of nuclear core center / oxygen Shen Dianwu Occurs after the deposition of epitaxial layers. As mentioned above, the template of the lattice vacancies is formed during the epitaxially deposited wafer manufacturing process, and the nucleation / precipitation is performed during the heat treatment cycle of the electronic device manufacturing process. In another example, the lattice empty template and the The formation of the nuclear center / oxygen sink occurs in the deposition of the epitaxial layer :: The nucleation center 'oxygen precipitation is sufficient to generate heat by heating the wafer to a temperature = nucleation center / oxygen precipitation is large enough to exist in any subsequent heat treatment ( , Half of the nucleation center / milk precipitate is greater than the "critical radius"). #From the above, it can be seen that the ten purposes of the present invention have been achieved. Because it is not outside the scope of the present invention Various modifications can be made to the above-mentioned porous rotating crystal base = so I hope that all things contained in the above description are exemplified and not restrictive. (Please read the precautions on the back before filling this page) ·-丨 Line · Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives -38-