523910 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 製 式使來 。通區相元體 在Ϊ 用42可不之 . ， 一7Γ泣 ， ？ 之 ΐ 形或線 體，散線字晶 ccdt作6 及則中 ί何表 之比 3 體電此 之料元：晶開擴元與電斷失 halfa新58能，胞 億存因 行資位 電隔個位是此切消isc更 S 功多億 記 諸態 和出和 之相一與極制被間 M)o種 Μ 之太記 之gf尤 列讀線 接互中是閘控或時未sh此eft件得在 渠 丨ΐ 成胞元 連而其區且來道著t-、 r 於3ί。元失存 以 +何 ΛΓ 由 溝容電*¥ 0 0 e* 00^0 離S配記之 器通向汲連閘經而 。)0持記荷種 隔多中 其由當 容由方 c相至流流 π 新率AM之對電此 和 豸 ，。適 電藉之區器壓間電1]?更頻^言會之出 胞rss 胞制動 與其流極容電之漏)ί被新M(前荷存讀 有 -Hu Aft 億 · 億控驅 個，電汲電之區於 1 須更 R 項電儲來 記BMO記來由 一區據為式當極由ho必之態 1 之所器3-有 MRA式線藉 有散依稱渠適汲荷es器大動第小若大-具 MMD陣元是 含擴。個溝加和電hr容較為圍太。放 種 15 彡 矩位中 常個制一與施區之(t電要稱範中響出 一CSW 。有和胞 通二控另是由極存限億需亦利器影讀 及(1_元含線億 胞有來而區藉源儲臨記流胞專容之之 涉路 ί 位片元記 億含極區極 c 在所至此電億請電良接 明。電0 料晶字入 記體閘極源接流中失，漏記申式不連 發法體1C資AM由寫 CAM晶由源，連電容消前之種知渠有所 本方積些種DR可料成DR電是為接相使電荷之高此已溝性以 造 這一 且資達 此道稱連線， 電準較，中 用能 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 523910 A7 B7 2 五、發明說明（） 資訊。此種資訊會消失且造成讀出上之錯誤。為了防止 此種讀出上之錯誤，則建議使漏電流降低。為了減小此 漏電流則各記億胞須藉由一種隔離溝渠（S T I )而互相隔離 。通常此種區域（其中此隔離溝渠即將形成）是藉由以微 影術所結構化之層來界定。因此，曝光時須對準已存在 之這些結構（例如，溝渠式電容器）。由於原來就已存在 一種曝光對準精確性，則隔離溝渠之位置會相對於溝渠 式電容器而變動。因此，偶然會有下述現象：此隔離溝 渠使溝渠式電容器完全與電晶體相隔離。相關之記億胞 因此不可使用，這通常亦適用於其它許多記億胞中，這 是因為所有之記億胞都是以相同之隔離溝渠曝光步驟而 被隔開。 若此種曝光對準精確性不會使溝渠式電容器完全隔離 ，則由此隔離溝渠所造成之電性連接會受到限制，這是 因為該隔離溝渠之一部份已取代了溝渠式電容器及導電 性溝渠填料。這樣會使溝渠式電容器連接至電晶體時之 電阻較高，這樣會慢慢地使記憶胞成為不可使用。可容 許之對準精確性因此較該隔離領之内直徑小很多。 積體密度逐漸提高使最小之結構大小F減小，且亦使 曝光對準精確性減小。但最小之結構大小F和曝光對準 精確性之比值並不是定值的，因為曝光對準精確性相對 於最小之結構大小F而言減小得較慢。隨後之微影術之 各步驟之與此有關之相對於已存在之各結構之變動性之 提高因此同樣會增加。 本發明之目的是提供一種記億體之製造方法，其中此 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 經濟部智慧財產局員工消費合作社印製 之 注 意 事523910 A7 B7 V. Description of the Invention (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. It can be used in the same way as the 42-phase phase element. A 7Γ cry, the shape of a line or a line, scattered lines The word crystal ccdt is 6 and the ratio in the table is 3. The material of the electric power: the crystal expansion and the power loss of the halfa new 58 energy. In addition, there are more than one million records of the states and the sum of the states and the quilt. The type of the GF's gf, especially the read line connection, is gated or not. ΐ Cells are connected to each other and the area is t-, r in 3ί. Yuan lost with + Ho ΛΓ from the ditch Rongdian * ¥ 0 0 e * 00 ^ 0 from the device assigned to S to Qilian gate. ) 0 holds a variety of types, which are from the opposite phase c to the current π new rate AM and 豸. The suitable electricity borrowed by the device voltage and electricity 1]? More frequent ^ speech meeting of the cell rss cell brake and its current capacity leakage) ί by the new M (front load storage read -Hu Aft billion · billion control drive The electric power draws the electric power in the area of 1. The R term of the electric storage must be used to record the BMO. The electric power is recorded in the area as the pole. The electric power must be in the state of 1. The 3-type MRA line is borrowed. The largest movement of the server is as small as possible-with MMD array elements are expanded. A groove plus a power hr capacity is too large. Seeds of 15 mm in the moment position are often used in one system and the application area. A CSW sounded. You and Cellular Two Controls were also read by the extreme storage limit of billions of needs and also sharp tools and (1_ yuan containing the line billion cells have come, and the district borrowed from the source Chu Linji cell tolerate the road involved ί The bit chip contains 100 million poles, and the region c is so good. Please be informed. The electricity 0 material crystal word is lost in the gate source connection of the body. Write the CAM crystal from the source, and the capacitors have some knowledge before the capacitors are removed. Some DR can be expected to be DR. The reason is that the charge is high for the phase connection. Line, electricity comparison, medium energy (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 523910 A7 B7 2 V. Description of the invention () Information. Such information will disappear and cause errors in reading. In order to prevent such reading If it is wrong, it is recommended to reduce the leakage current. In order to reduce this leakage current, each cell must be isolated from each other by an isolation trench (STI). Usually such areas (where the isolation trench is about to form) are formed by Defined by the layers structured by lithography. Therefore, these structures (such as trench capacitors) must be aligned during exposure. Since there is already an accuracy of exposure alignment, the location of the isolation trenches will be Relative to trench capacitors. Therefore, there are occasionally the following phenomenon: This isolation trench completely isolates the trench capacitor from the transistor. The related cells are therefore not usable, which is usually applicable to many other cells This is because all of the billion cells are separated by the same isolation trench exposure step. If this exposure alignment accuracy is not made the trench capacitor Full isolation, the electrical connection caused by this isolation trench will be limited, because part of the isolation trench has replaced the trench capacitor and conductive trench filler. This will connect the trench capacitor to the transistor When the resistance is higher, this will slowly make the memory cell unusable. The allowable alignment accuracy is therefore much smaller than the inner diameter of the isolation collar. As the density of the product gradually increases, the smallest structure size F decreases. It also reduces the accuracy of exposure alignment. However, the ratio of the smallest structure size F to the accuracy of exposure alignment is not constant, because the exposure alignment accuracy is reduced compared to the smallest structure size F. Slow. The subsequent increase in the variability of the subsequent steps of lithography relative to the existing structures will therefore also increase. The purpose of the present invention is to provide a manufacturing method for recording billions of dollars, in which this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Precautions
523910 A7 B7 3 五、發明說明（） 種在記億胞和隔離溝渠之間的非對準可降低至一種小於 曝光對準精確性之值。 依據本發明，此目的是藉由申請專利範圍第1項中之 製造方法來達成。 較佳之其它方式敘述在申請專利範圍各附屬項中。 本發明所依據之原理是此種隔離溝渠之自我對準式之 製法。此隔離溝渠之位置因此是與曝光對準精確性無關 。這是藉由使用一種沈積在溝渠中之溝渠覆蓋介電質來 達成，此種介電質在隔離溝渠製造時作為蝕刻遮罩用。 此種溝渠覆蓋介電質不是藉由微影術中對準已存在之各 結構來進行之曝光而形成，而是藉由基板上已存在之結 構來形成，在此種情況下是藉由溝渠式電容器之溝渠而 形成在所期望之位置上。因此，就形成該隔離溝渠所需 之微影術所需之微影術步驟而言只需一種很小之對準精 確性，其可容易地被達成（雖然存在著曝光對準精確性）。 光阻遮罩（其界定了隔離溝渠之區域）因此並非以對曝光 所需之最大需求而被結構化，而是能以鬆散之對準方式 被曝光。 --------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 覆及 其態 ，狀 罩種 外各 渠之 溝面 離界 隔此 種制 一 抑 成可 形此 是因 徼 〇 待渠 之溝 利離 有隔 之之 法刻 方蝕流 本已電 蓋漏 電 放 器 容 電 使 可 其 離隔下 隔種率 種此頻 一 由新 成藉更 形 C 使 是渠且 式溝長 形離延 施隔間 實之時 之刻存 利蝕儲 有已使 它各地 其蓋利 之覆有 法其可 方 ，層 之層間 明間中 發中渠 本渠溝 C 溝離降 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印制衣 523910 Α7 Β7 4 五、發明說明（) 此外，隔離溝渠中以填料填入是有利的。此種方式可 提高機槭穩定性且另外亦適合用來整平此基板之表面， 使例如字元線可在隔離溝渠填料上方延伸。 在本發明之方法之其它有利之形式中，隔離領具有一 種封罩面，其特徵是其周圍和高度，此隔離領之封罩面 之高度是相同形式的。這樣可使隔離領不會由隔離溝渠 去除。 本方法之其它步驟是：該隔離溝渠完全形成於溝渠之 外部。這樣所具有之優點是：導電性溝渠镇料（其配置 在溝渠中）不會由於隔離溝渠之形成而由溝渠中去除。 於是此溝渠之橫切面能有利地供導電性溝渠填料使用且 橫切面不會由於隔離溝渠而使其一部份變窄。 此外，此溝渠之一由隔離領所圍繞之區域中之導電性 溝渠填料是以均勻之溝渠填料寬度而形成。此種均勻之 溝渠填料寬度所具有之優點是：導電性溝渠填料不會由 隔離溝渠中去除。導電性導電填料因此具有可能之最大 橫切面，其可使電晶體以低歐姆形式連接至溝渠式電容 器。 在本發明之其它有利之形式中，此隔離溝渠在導電性 溝渠填料上方具有溝渠覆蓋介電質。由於此種溝渠覆蓋 介電質（其在形成此隔離溝渠時用作一種蝕刻遮罩），則 此種隔離溝渠能以自我對準之方式製成。 在本發明之其它有利之實施形式中，此隔離溝渠是以 隔離溝渠外罩來覆蓋。藉由此種隔離溝渠外罩，則能以 有利之方式來防止各種界面狀態（其可造成漏電流）。此 -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 装--------訂---------線 經濟部智慧財產局員工消費合作社印製 523910 A7 B7 5 五、發明說明（） 記億胞之儲存時間因此可延長，這樣可有利地使更新頻 率變小。 在本發明之其它有利之實施形式中，此隔離溝渠另外 以隔離溝渠中間層來作襯墊（Liner)。藉由此種隔離溝 渠中間層，則此記憶胞之儲存時間可有利地延長。 在其它有利之實施形式中，此溝渠覆蓋介電質含有氧 化物，氮化物或氣化氮化物，此隔離溝渠外罩含有氣化 物，氮化物或氧化氮化物，隔離溝渠中間層含有氮化物 及/或該隔離溝渠填料含有氣化物，氮化物，氧化氮化 物或多晶矽。 本發明之方法之有利之實施形式之設計方式是.·溝渠 中以導電性溝渠填料填入之後須形成一種溝渠覆蓋介電 質。此種介電質作為已自我對準之隔離溝渠蝕刻時所用 之蝕刻遮罩。 本發明之實施例顯示於各圖式中且將詳述於下。 圖式簡單説明： 第1圖 先前技藝之記億體，其具有記億胞和隔離溝 渠。 第2圖 先前技藝之記億體之另一實施例，其具有記 億胞和隔離溝渠。 第3圖 本發明第一實施例之記億體，其具有記億胞 和隔離溝渠。 第4圔 本發明第二實施例之記億體，其具有記億胞 和隔離溝渠。 第5a-5f圖 依據第3圖製造記億體，其具有記億胞和 一 7 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂--------線 523910 A7 _B7_ 五、發明說明（） 隔離溝渠時所用之本發明之方法之實施形式。 第6a-6b圖 依據本發明製造第4圖之記億體時此種 記憶體，其具有記億胞和隔離溝渠之另一實施形式。 在這些圖式中相同之參考符號表示相同或功能相同之 元件。以符號” ’ ”所表示之參考符號表示相鄰記億胞 100'之相同或功能相同之元件。 第1圖是先前技藝中一種記億體（其具有記億胞和隔 離溝渠）之第一實施形式。所示之記億胞1 0 0由一溝渠式 電容器16Q及一個電晶體1 10所構成。溝渠式電容器160 形成在基板101中。在基板101中引入一種埋入井170, 此種井170例如十摻雜物質所構成。溝渠式電容器160具 有一個溝渠10 8 (其包含上部區1ϋ 9和下部區111)。隔離 領168存在於此溝渠1D8之上部區109中。此埋入井170至 少一部份穿過此溝渠之下部區。一種埋入井1 6 5配置在 此溝渠108之一部區111周圍。井165形成此電容器之外 電極。記億胞1 〇 〇之埋入板1 6 5和相鄰記億胞1 0 G ’之埋入 板165'藉由埋入井170而在電性上互相連接。 溝渠108之一部區111和隔離領168是以介電質層164作 (請先閱讀背面之注意事項再填寫本頁) _ 裝---- 訂---------線‘ 經濟部智慧財產局員工消費合作社印製 墊 1 襯層 層 質 電 介 此 質 電 介 之 物 化 氣 由 層 些 16這 式， 渠成 溝構 成所 形疊 64堆 I 層 或 層 多 由 可 質 電 介 氮 成 S β 構 所， 2 物 ο 化Ta 氮 ， 化如 氧例10極 和，〇 渠電 物質質溝内 化電電 之 酸料 鈦瑱 U 渠 BS溝 ， 性 2 電 ao導 T 以 ， 中 介介 器 之之 容 大當 電 較適 成 數它 形 常其 其 電及 ， 介以 入 用!)填 使 可 亦 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 523910 Α7 Β7 經濟部智慧財產局員工消費合作社印製 7五、發明說明（) 電晶體1 1 〇由源極區1 η和汲極區1 1 3所構成，汲極區 113是與一種無邊緣之接觸區183相連接。電晶體11〇亦 包含一個通道117，其是由閘極112所控制。閘極112是 與字元線120相連接。無邊緣之接觸區183是與位元線185 相連接，位元線185延伸於介電質層189上方。在此種形 式中一種埋入式接觸區250存在於源極區114中。 在此種實施形式中一種穿越（Passing)字元線121在隔 離溝渠180上方延伸，此種字元線121藉由隔離溝渠180 而與導電性溝渠慎料161相隔開。此隔離溝渠180之一部 份形成在溝渠中，使溝渠108之上部區109中之導電 性溝渠瑱料161由隔離溝渠180所取代。溝渠填料寬度500 在溝渠108之上部區中因此不是定值的，而是在溝渠 108之上端處變細，這與隔離溝渠180之寬度有關。 第2圖中顯示一種記億體（其具有記億胞和隔離溝渠） 之另一實施形式，其在先前技藝中已為人所知。第2圔 之形式與第1圖之不同點是隔離溝渠180之位置，此隔離 溝渠18ϋ由於曝光對準精確性而使導電性溝渠填料161完 全與電晶體110之源極區114隔開且使記億胞100成為不 可用。 第3圔是本發明之第一實施形式。所示之記億胞1〇〇 由溝渠式電容器160及電晶體110所構成。溝渠式電容器 160形成在基板101中。在基板101中引入一種埋入井170 ，其例如由摻雜物質所構成。溝渠式電容器160形成在 基板101中。在基板101中引入一種埋入井170,此種井 170例如十摻雜物質所構成。溝渠式電容器160具有一個 (請先閱讀背面之注意事項再填寫本頁) 0 ^«裝 ----訂---------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 523910 A7 B7 經濟部智慧財產局員工消費合作社印製 8五、發明說明（） 溝渠1〇8(其包含上部區109和下部區111)。隔離領168存 在於此溝渠108之上部區1ϋ 9中。此埋入井170至少一部 份穿過此溝渠之下部區。一種埋入井165配置在此溝渠 108之一部區111周圍。井165形成此電容器之外電極。 記億胞1 0 0之埋入板1 6 5和相鄰記億胞1 ϋ 0 '之埋入板1 6 5 ’ 藉由埋入井170而在電性上互相連接。 溝渠10 8之一部區111和隔離領168是以介電質層164作 襯墊，此介電質層164形成溝渠式160之介電質。介電質 層164可由多層或層堆疊所構成，這些層由氧化物，氮 化物和氣化氮化物所構成。亦可使用介電常數較大之介 電質，例如，T a 0 2 , B S Τ (鈦酸緦鋇）以及其它適當之介 電質。 溝渠108中以導電性溝渠填料161瑱入，其形成電容器 之内電極。 電晶體1 1 Q由源極區1 1 4和汲極區1 1 3所構成，汲極區 113是與一種無邊緣之接觸區183相連接。電晶體110亦 包含一個通道11 7，其是由閘極1 1 2所控制。閛極1 1 2是 與字元線1 2 0相連接。無邊緣之接觸區1 8 3是與位元線1 8 5 相連接，位元線185延伸於介電質層189上方。 在記億胞1 〇 Q和相鄰之記億胞1 0 (Γ之間存在一種隔離 溝渠1 8 G。此隔離溝渠1 8 0由一種隔離溝渠外罩4 3 5 (其作 為隔離溝渠180之襯墊）所構成。該隔離溝渠180另外由 溝渠覆蓋介電質430(其位於溝渠108中該導電性溝渠镇 料16 1之上方）所構成。此隔離溝渠180另外又包含第二 溝渠覆蓋介電質4 3 G '(其位於溝渠1 0 ^中一種導電性溝 -1 0 - (請先閱讀背面之注意事項 寫本頁) 裝 訂---------線； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 523910 A7 B7 9 五、發明說明（） 渠填料1 6 P之上方），此種介電質4 3 0’是相鄰記億胞1 0 0 之一部份。最後，此隔離溝渠1 8 0亦包含一種隔離溝渠 填料4 4 0 (其填人該隔離溝渠180中）。 溝渠108之由隔離領168所圍繞之區域501是以導電性 溝渠填料1 6 1填入，此種填料1 6 1在該所圍繞之區域5 0 1 中具有一種均勻之溝渠瑱料寬度500。 第4圖是本發明之記億體（其具有記億胞和隔離溝渠） 之另一實施形式，其與第3圖之實施形式之不同點是該 隔離溝渠中間層4 3 6 ,其除了覆蓋該隔離溝渠外罩4 3 5外 亦覆蓋該隔離溝渠1 8 G。 第5&圖中提供此基板101，其上即將製成DRAM記億胞。 在此種形式中此基板101可輕易地以P型之摻雜物質（例 如，硼）來摻雜。在基板101中在適當之深度中形成一種 η-摻雜之埋入并170。為了對此埋入井170進行摻雜，則 可使用磷或砷作為摻雜物質。此種埋入井1 7 0例如可藉 由植入而産生，其用來使Ρ井由基板101中隔離且另外 可在記億胞100之埋入板165和相鄰記億胞100'之埋入板 165’之間形成一種導電性連接。另一方式是此種埋入井 1 7 〇可藉由磊晶生長之摻雜之矽層而形成或藉由晶體生 長（磊晶）及植入法之組合來形成。此種技術在US專利文 件5 250 829(由Bronner等人所發表）中已有描述。 一種基層堆疊形成在基板1之表面上且例如含有一種 基層氧化物層104及一種基層停止層105(其可作為拋光 用或蝕刻停止用且例如由氮化物所構成）。在基層停止 層105上方設置一種硬遮罩層，其可由TE0S或其它材料 -1 1 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線氣 經濟部智慧財產局員工消費合作社印製 523910 經濟部智慧財產局員工消費合作社印製 A7 __._B7___五、發明說明（） (例如，矽酸鹽玻璃（B S G ))所構成。另外亦可使用一 種抗反射；a ( ARC )以便改良此種微影術之解析度。 此種硬遮罩層是使用一般之微影術技術而被結構化， 以便界定一種區域，在此種區域中形成溝渠1 0 8。然後 使用此種硬遮罩層作為反應性離子蝕刻（R I Ε )用之蝕刻 遮罩，此種蝕刻可形成一種深溝渠1 0 8。 為了製成該隔離領1 6 8，此溝渠中須以一種隔離領犧 牲層填入，此犧牲層被去除直至即將形成之隔離領1 6 8 之下側為止。然後在晶圓上沈積一種介電質層，其在溝 渠1 0 8之上部區1 0 9中覆蓋此溝渠1 0 8之側壁及基板表面 。此介電質層用來形成該隔離領1 6 8且例如由氧化物所 構成。然後例如以反應性離子蝕刻U I Ε )或以C D Ε .(C h e m i c a 1 D r y E t c h )來對此介電質層進行蝕刻，以便 形成該隔離領1 6 8。 須選取反應性離子蝕刻用之化學劑，使該氧化物可選 擇性地對該隔離領犧牲層之多晶矽及硬遮罩層之氮化物 而被蝕刻。然後由此溝渠1 Q 8之下部區中去除該隔離領 犧牲層。這較佳是由C D E過程來達成，其中天然之薄氧 化物層作為C D E蝕刻停止用。 然後以η型摻雜物質（例如，砷或磷）來形成一種埋入 板1 6 5以作為電容器外部電極。此隔離領1 6 8作為摻雜遮 罩用，其可限制此溝渠1Q8之下部區1 11上之摻雜物質。 為了形成該埋入板1 6 5，則可使用一種氣相摻雜法，電 漿摻雜法或電漿浸入-離子植入法（Ρ I II )。這些技術例 如已描逑在 R a n s 〇 ni e t a 1 ·，J · Ε 1 e c t. r 〇 c h e ϊΐι i c a 1 ：· S 〇 c ·, -12- _ ___________ _ _ ___ . - -- 太紙張尺;f適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) --裝 ϋ ϋ 1 n TJ · MB MM I I am 霧 %· 523910 A7 B7 11 五、發明說明（）523910 A7 B7 3 V. Description of the invention () The misalignment between the recording cell and the isolation trench can be reduced to a value smaller than the accuracy of the exposure alignment. According to the present invention, this object is achieved by the manufacturing method in item 1 of the scope of patent application. Other preferred methods are described in the appended items of the scope of patent application. The principle on which the present invention is based is such a self-aligned method of isolating trenches. The location of this isolation trench is therefore independent of the accuracy of exposure alignment. This is achieved by using a trench-covered dielectric deposited in the trench to act as an etch mask during the isolation trench fabrication. This trench-covering dielectric is not formed by exposure to existing structures aligned in lithography, but is formed by existing structures on the substrate. In this case, the trench-type The trench of the capacitor is formed at a desired position. Therefore, only a small alignment accuracy is required for the lithography steps required to form the isolation trench, which can be easily achieved (although there is exposure alignment accuracy). The photoresist mask (which defines the area that isolates the trench) is therefore not structured with the greatest demand for exposure, but can be exposed in a loosely aligned manner. -------------- Installation -------- Order --------- line (please read the precautions on the back before filling this page) Ministry of Economy Wisdom The property bureau employee consumer cooperative prints the cover and its state, and the channels outside the canals are separated from the boundary. This system can be made into a shape. This is because of the method of waiting for the channels to be separated from the channels. Erosion current has been covered by the electric leakage of the electric discharge capacitor, so that it can be separated from the isolation rate. This frequency will be changed by the newcomer to make the shape of the channel and the trench is long. Erosion and storage has made it possible to cover the Gali in all parts of it. The layers between the layers of the middle canal, the middle canal, the canal, and the canal. The canal is separated and lowered. PCT) Printed clothing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 523910 Α7 Β7 4 5. Description of the invention () In addition, it is advantageous to fill the isolation trench with filler. This method can improve the stability of the maple and is also suitable for leveling the surface of the substrate, so that, for example, word lines can extend above the isolation trench filler. In another advantageous form of the method of the invention, the spacer collar has a cover surface which is characterized by its periphery and height, and the height of the cover surface of the spacer collar is the same. This prevents the isolation collar from being removed by the isolation trench. The other step of the method is that the isolation trench is completely formed outside the trench. This has the advantage that the conductive ditch ballast (which is placed in the ditch) will not be removed from the ditch due to the formation of the isolation ditch. Therefore, the cross section of the trench can be advantageously used for conductive trench fillers and the cross section cannot be narrowed in part by isolating the trench. In addition, one of the trenches is formed by a conductive trench fill in the area surrounded by the isolation collar with a uniform trench fill width. This uniform trench fill has the advantage that conductive trench fill is not removed from the isolation trench. The conductive conductive filler thus has the largest cross-section possible, which allows the transistor to be connected to the trench capacitor in a low ohmic form. In another advantageous form of the invention, the isolation trench has a trench covering dielectric over the conductive trench fill. Since this trench covers a dielectric (which is used as an etch mask when forming this isolation trench), this isolation trench can be made in a self-aligned manner. In another advantageous embodiment of the invention, the isolation trench is covered by an isolation trench cover. With such an isolation trench cover, various interface states (which can cause leakage current) can be prevented in an advantageous manner. This-6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ----- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 523910 A7 B7 5 V. Description of the invention () The storage time of the billion cells can therefore be extended, which can advantageously reduce the update frequency. In another advantageous embodiment of the present invention, the isolation trench is additionally lined with an isolation trench intermediate layer. By such an intermediate layer of the isolation channel, the storage time of the memory cell can be advantageously extended. In other advantageous implementation forms, the trench covering dielectric contains oxides, nitrides or vaporized nitrides, the isolation trench cover contains vapors, nitrides or oxynitrides, and the middle layer of the isolation trenches contains nitrides and / Or the isolation trench filler contains gaseous, nitride, oxynitride or polycrystalline silicon. An advantageous embodiment of the method of the present invention is designed in such a way that after the trench is filled with a conductive trench filler, a trench covering dielectric must be formed. This dielectric acts as an etch mask for etching self-aligned isolation trenches. Embodiments of the present invention are shown in the drawings and will be detailed below. The diagram is briefly explained: Figure 1 The previous technique of recording billions of bodies has billions of cells and isolation channels. Fig. 2 Another embodiment of the previous technique of recording billion cells, which has billion cells and isolation trenches. Fig. 3 A billion body according to a first embodiment of the present invention includes a billion cell and an isolation trench. (4) The billion-digit body of the second embodiment of the present invention has a billion-cell number and an isolation trench. Figures 5a-5f are manufactured in accordance with Figure 3, which has billions of cells and one 7-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back first (Fill in this page again) Assemble ---- Order -------- Line 523910 A7 _B7_ V. Description of the invention () The implementation form of the method of the present invention used to isolate the ditch. Figs. 6a-6b When the memory of Fig. 4 of Fig. 4 according to the present invention is manufactured, the memory has another embodiment of recording cells and isolation channels. The same reference symbols in these drawings denote the same or functionally equivalent elements. The reference symbol indicated by the symbol “” represents the same or the same function element of the neighboring cells 100 '. Fig. 1 is the first implementation form of a memory cell (which has a cell and a ditch) in the prior art. The illustrated billion cell 100 is composed of a trench capacitor 16Q and a transistor 110. A trench capacitor 160 is formed in the substrate 101. An embedded well 170 is introduced into the substrate 101, and such well 170 is composed of, for example, ten doped substances. The trench capacitor 160 has a trench 10 8 (which includes an upper region 119 and a lower region 111). An isolation collar 168 exists in the upper region 109 of this trench 1D8. At least a portion of the buried well 170 passes through the lower area of the trench. A buried well 165 is disposed around a portion 111 of one of the trenches 108. The well 165 forms an electrode other than this capacitor. The buried plate 165 'with a memory cell 100 and the buried plate 165' with an adjacent memory cell 10 G 'are electrically connected to each other through the buried well 170. One part of the trench 108 and the isolation collar 168 are made of a dielectric layer 164 (please read the precautions on the back before filling out this page) _ Install ---- Order --------- Line ' The Intellectual Property Bureau of the Ministry of Economic Affairs, the employees' cooperatives, printed mats, 1 the lining layer of the dielectric material, the physical material of the dielectric material is composed of 16 layers, and the trenches are formed by 64 stacks of I layers or layers. Dielectric nitrogen forms the structure of S β, 2 compounds ο convert Ta nitrogen, such as the oxygen electrode 10 poles, and the acid material titanium channel U channel BS channel, the electrical conductivity T channel, The capacity of the interposer is more suitable. It can be used in many ways. It can be used as it is!) Fill in the paper. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 523910 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7. Fifth, the invention description () Transistor 1 1 〇 is composed of a source region 1 η and a drain region 1 1 3, the drain region 113 is a kind of The contact areas 183 are connected. Transistor 110 also includes a channel 117, which is controlled by a gate 112. The gate electrode 112 is connected to the word line 120. The edgeless contact region 183 is connected to the bit line 185, which extends above the dielectric layer 189. A buried contact region 250 exists in the source region 114 in this form. In this implementation form, a passing character line 121 extends above the isolation trench 180, and this character line 121 is separated from the conductive trench 161 by the isolation trench 180. One part of the isolation trench 180 is formed in the trench, so that the conductive trench material 161 in the upper region 109 of the trench 108 is replaced by the isolation trench 180. The trench fill width 500 is therefore not constant in the area above the trench 108, but is tapered at the upper end of the trench 108, which is related to the width of the isolation trench 180. Fig. 2 shows another embodiment of a memory cell (which has cell cells and isolation channels), which has been known in the prior art. The difference between the second form and the first figure is the location of the isolation trench 180. This isolation trench 18ϋ completely separates the conductive trench filler 161 from the source region 114 of the transistor 110 due to the accuracy of the exposure alignment. Keeping 100 million cells becomes unavailable. The third embodiment is a first embodiment of the present invention. The illustrated billion cell 100 is composed of a trench capacitor 160 and a transistor 110. A trench capacitor 160 is formed in the substrate 101. An embedded well 170 is introduced into the substrate 101 and is composed of, for example, a doping substance. A trench capacitor 160 is formed in the substrate 101. An embedded well 170 is introduced into the substrate 101, and such well 170 is made of, for example, ten doped substances. The trench capacitor 160 has one (please read the precautions on the back before filling this page) 0 ^ «installation ---- ordering ------------ This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 523910 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 85. Description of the Invention () Ditch 108 (which includes the upper area 109 and the lower area 111). Isolation collar 168 resides in the area 1ϋ 9 above this trench 108. At least a portion of the buried well 170 passes through the lower area of the trench. A buried well 165 is arranged around a portion 111 of one of the trenches 108. The well 165 forms an electrode outside this capacitor. The buried plate 16 of the 100 million cells and the buried plate 1 65 of the adjacent 1 billion cells are electrically connected to each other through the buried well 170. A portion 111 of the trench 108 and the isolation collar 168 are lined with a dielectric layer 164, which forms a trench-type 160 dielectric. The dielectric layer 164 may be composed of a plurality of layers or a stack of layers. These layers are composed of oxides, nitrides, and vaporized nitrides. Dielectrics with larger dielectric constants can also be used, such as T a 0 2, B S T (barium hafnium titanate), and other suitable dielectrics. The trench 108 is penetrated with a conductive trench filler 161, which forms an inner electrode of the capacitor. The transistor 1 1 Q is composed of a source region 1 1 4 and a drain region 1 1 3. The drain region 113 is connected to an edgeless contact region 183. Transistor 110 also includes a channel 11 7 which is controlled by a gate 1 1 2. The pole 1 1 2 is connected to the character line 1 2 0. The edgeless contact region 1 8 3 is connected to the bit line 1 8 5, and the bit line 185 extends above the dielectric layer 189. There is an isolation trench 18 G between the recording cell 100Q and the adjacent recording cell 10 0 (Γ). This isolation trench 1 8 0 is covered by an isolation trench 4 3 5 (which serves as the lining of the isolation trench 180 The isolation trench 180 is further composed of a trench covering dielectric 430 (which is located above the conductive trench ballast 161 in the trench 108). The isolation trench 180 further includes a second trench covering the dielectric Quality 4 3 G '(It is located in a trench 1 0 ^ a conductive groove-1 0-(Please read the precautions on the back first to write this page) Binding --------- line; This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 523910 A7 B7 9 V. Description of the invention () Above the channel filler 1 6 P), this dielectric 4 3 0 'is adjacent to the billion cells 1 0 Part of 0. Finally, the isolation trench 1 8 0 also contains an isolation trench filler 4 4 0 (filled in the isolation trench 180). The area 501 of the trench 108 surrounded by the isolation collar 168 is conductive Trench filler 1 6 1 is filled in. This filler 1 6 1 has a uniform trench material width 500 in the surrounding area 5 0 1 FIG. 4 is another implementation form of the bilge body (which has a bilge cell and an isolation trench) according to the present invention. The difference from the implementation form of FIG. 3 is the middle layer of the isolation trench 4 3 6. The isolating trench cover 4 3 5 also covers the isolating trench 1 8 G. The substrate 101 is provided in Figure 5 & a DRAM memory cell is to be made thereon. In this form, the substrate 101 can be easily replaced with P Type dopant (eg, boron) for doping. An n-doped implant 170 is formed in the substrate 101 at an appropriate depth. In order to dope this buried well 170, phosphorus or Arsenic is used as a doping substance. Such a buried well 170 can be produced by implantation, for example, to isolate the P well from the substrate 101 and additionally, it can be embedded in the buried plate 165 and adjacent memory of the 100 million cells 100. A conductive connection is formed between the embedded cells 165 'of 100 billion cells. Another way is that such embedded wells 170 can be formed by doped silicon layers grown by epitaxy or by crystal growth (lei Crystal) and implantation methods. This technique is described in US patent document 5 250 829 (by Bronner et al. It is described in Table 1. A base layer stack is formed on the surface of the substrate 1 and contains, for example, a base oxide layer 104 and a base stop layer 105 (which can be used for polishing or etching stop and is made of, for example, nitride) A hard mask layer is provided above the base stop layer 105, which can be made of TE0S or other materials. 1 1-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first) (Please fill in this page for matters) Packing -------- Order --------- Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 523910 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __ ._B7 ___ V. Description of the invention () (for example, silicate glass (BSG)). It is also possible to use an anti-reflection; a (ARC) to improve the resolution of this lithography. This hard mask layer is structured using general lithography techniques to define an area in which trenches 108 are formed. This hard mask layer is then used as an etching mask for reactive ion etching (R I Ε). This etching can form a deep trench 108. In order to make the spacer 16 8, the trench must be filled with a spacer sacrificial layer, and the sacrificial layer is removed until the underside of the spacer 16 1 to be formed soon. A dielectric layer is then deposited on the wafer, which covers the sidewalls of the trench 108 and the surface of the substrate in the upper region 108 of the trench 108. This dielectric layer is used to form the isolation collar 168 and is made of, for example, an oxide. This dielectric layer is then etched, for example, with reactive ion etching U I E) or C D E. (C h e m i c a 1 D r y E t c h) to form the isolation collar 168. A chemical agent for reactive ion etching must be selected so that the oxide can be selectively etched on the polycrystalline silicon of the spacer sacrificial layer and the nitride of the hard mask layer. The isolation collar sacrificial layer is then removed from the lower region of the trench 1 Q 8. This is preferably achieved by a CD E process, in which a natural thin oxide layer is used as CD E etch stop. A buried plate 165 is then formed with an n-type dopant (for example, arsenic or phosphorus) to serve as an external electrode of the capacitor. The isolation collar 16 is used as a doping mask, which can limit the doping substance on the lower region 11 of the trench 1Q8. To form the buried plate 165, a vapor phase doping method, a plasma doping method or a plasma immersion-ion implantation method (PIII) may be used. These techniques have been described, for example, in R ans 〇ni eta 1 ·, J · Ε 1 ec t. R 〇che ϊΐι ica 1: · S 〇c ·, -12- _ ___________ _ _ ___.--Too much paper rule ; f Applicable to China National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on the back before filling this page)-Decoration ϋ 1 n TJ · MB MM II am fog% · 523910 A7 B7 11 V. Description of the invention ()
Band 141，N 〇 . 5 ( 1 9 9 4 ) , page 1 3 7 8 ff及 US Patent 4937205中。在使用該隔離16 8作為摻雜遮罩之情況下亦 可使用離子植入法。另一方式是使用一種摻雜之矽酸鹽 玻璃作為摻雜物質（例如，AS G)來形成此埋入板165。此 種形式例如描述在 Becker et al.，J. Electrochemical. Soc.，Band.l36，（1989)， page 3033 ff中。若使用已摻 雜之矽酸鹽玻璃來進行摻雜，則其在形成該埋入板1 6 5 之後須去除。 埋入式接觸區250藉由植入，電漿摻雜或氣相摻雜來 引入此摻雜物質而形成。 然後形成一種介電質層164，其覆蓋此基板101之表面 及溝渠108之内部。此介電質層164作為記億體之介電質 以便使電容器之電極隔開。在此種形式中此介電質層1 6 4 由氧化物，氮化物，氧化氮化物或一種層堆疊（由氧化 物層及氧化物層所構成）所構成。亦可使用介電常數較 大之材料，例如，T a 0 2或B S Τ。 沈積導電性溝渠填料1 6 1 (其可由摻雜之多晶矽或非晶 矽所構成〉以便填入溝渠1 0 8中且覆蓋此基板1 Q 1之表面。 例如可使用CVD法或其它習知之製程。然後例如使用CD E 步驟，ίί I E步驟，化學乾燥蝕刻步驟或組合式之C Μ P - E I E 步驟（CMP: Chemical Mechanical Polishing)而使導電 性溝渠瑱料1 6 1在使用適當之化學劑此種情況下被整平 且隨後使此填料1 6 1下降至溝渠1 0 8中。 第5 b圖中沈積一種溝渠覆蓋介電質4 3 0，其可由氧化 物，氮化物或氣化氮化物所構成且可藉由C Ο， L P C Ο -1 3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線j 經濟部智慧財產局員工消費合作社印製 523910 A7 B7 12五、發明說明（） (Low pressure CVD )或 PECVD ( p 1 asa Enhanced CVD)沈 積而成。例如，可利用LPCVD製程來産生TEOS，或可使 用臭氧- TE0S或高密度之電漿氧化物（HDP Oxide)另一方 式是可使用一種選擇性氣化作用（Seleox)來形成該溝渠 覆蓋介電質4 3 0。此溝渠覆蓋介電質4 3 0因此可選擇性地 對基層停止層105而生長在導電性溝渠瑱料161上。然後 層長 止生 停在 層 3 基1 於 止 停 且 平 整 質 電 介 蓋 覆 渠 溝 43此 質是 電式 介方 蓋一 覆另 渠 。 溝處 此度 將高 之 用 作 化 氧 性 擇 選 由 藉 是 這 ο 平 整 被 間 期 程成 過達 層 阻 光 板使 基後 在然 光 此 中 其 層 面阻ΗΓ中 表光:|5圖 積 沈 在 現 上 層 射 反 抗 ill 種 像 顯 且 光 曝 5 域 層區 阻些 光這 及在 ο , 1 有 5 只 除區 去些50 被這10 已在層 2 先止 首停 層 基 5 該 第除 在去 中 域 此 護是 C 保除 80所去 渠52S 溝層10 離阻層 隔光止 該被停 成未層 形其基 中;(種 進介 來蓋 30覆 It 渠 溝 及 阻 光 有 只 約 大 2 y 5 貝 層 ， 阻性 光擇 之選 有之 現限 對有 地於 性由 擇 。 選行 質 電 介 蓋 覆 渠 溝 及 -------裝·------ -訂·1丨！ — 線 (請先閱讀背面之注意事項再填寫本頁) 氣 層 基 層和 43物以 質化是 電氧於 此 中 被來 而 3 ^ S $ 刻Jtf之 二㈤相 物 第ti時 在ι·ί刻 氣έ ο Ε 0 除RI04 去之ί 被暫 可短 份由 部藉 一04 1L 之 層 物 層 渠 除溝 基去此 經濟部智慧財產局員工消費合作社印製 4 中 質圖18 電5d渠 介第溝 蓋在離 覆 隔 刻 蝕 行 進 層 阻 光 該 除 去 如 例 ο 刻 蝕 行 進 矽劑 以學 且化 此 F 對 S 來 - 驟 Β Η 步 - 體種 整此 之在 ο ο 8 2 1 5 渠層 溝阻 離光 隔此 此 〇 成像 形顯 時及 C 同光 中種曝 驟一行 步在進 I 可阻 -R是光 矽式此 在方對 用一中 合另程 適 過 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 523910 A7 B7 經濟部智慧財產局員工消費合作社印製 13五、發明說明（） 整體過程中被去除或在該隔離溝渠1 8 G蝕刻之後被去除。 第5 e圖中形成此隔離溝渠外罩4 3 5 ,以便使界面狀態 及由此所造成之漏電流變小，這例如可利用熱氧化作用 來進行，其形成一種2至15ii m厚之氧化物層。然後形成 該隔離溝渠填料4 4 G ^於是例如沈積C V D - T E 0 S，C V D臭氣-T E 0 S，L P C V D - T E 0 S，H D P氧化物或氣化氮化物作為隔離 溝渠填料4 4 0。另一方式是可由多晶矽來製成該隔離溝 渠填料4 4 0。在本實施例中此隔離溝渠填料4 4 0是由HDP 氧化物所構成。其它方式是可藉由熱氧化作用而使此種 構成該隔離溝渠填料440所用之材料被壓縮。在此種情 況下不需形成該隔離溝渠外罩4 3 5，這是因為在此種壓 縮過程中氣化可很容易地經由現有之隔離材料而擴散， 因此可使界面狀態減少以及使由此所造成之漏電流減少。 然後藉由C Μ Ρ步驟或R I Ε步驟使此隔離溝渠填料4 4 0被 整平直至基層停止層105之高度處為止。 另一方式是此隔離溝渠180中利用一種選擇性氧化過程 來進行瑱入。於是隨後不需進行整平過程或只需一種短 暫之氧化物- CMP過程（N.Elbel et al·，1989，Symposium on VLSI Technology, page 208 ff.)在此種情況下此 隔離溝渠外罩4 3 5只有在選擇性氧化-沈積之後藉由熱氧 化作用經由已沈積之Selox層而形成。 第5f圖中去除此基層停止層1Q 5。此時例如是使用熱 磷酸（Η 3 P〇4 )或HF蒸氣。此外，基層氧化物層104藉 肋於HF蒸氣或BHF而被去除，且隨後生長一種犧牲性閘 極氧化物4 4 5。 -1 5- (請先閱讀背面之注意事項再填寫本頁) 裝 訂----- 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 523910 A7 B7__ 14 五、發明說明（） 本方法用來製成第一種形式之記億體（其具有記億胞 和自我對準之隔離溝渠180)之各步驟至此結束，隨後之 各步驟是依據現有之先前技藝來製成此電晶體1 1 G ,如 ϋ S專利文件5 8 6 7 4 2 0中所述者。 第6 at圖中描述此種依據第4圖之記億體（其具有記億 胞及自我對準之隔離溝渠18Q)之其它型式之製造，其結 束於第5 d圖所示之階段。藉由熱氣化作用而形成該隔離 溝渠外層435,其用來防止界面狀態及由此而造成之漏 電流。此隔離溝渠外罩4 3 5典型上是2至15n m厚。然後 形成一種隔離溝渠中間層4 3 6 (襯墊），以便使記億胞之 儲存時間延長而使更新（refresh)頻率降低。此隔離溝 渠中間層典型方式是由氮化物或氣化氮化物所製成，這 例如可藉由CVD過程或LP CVD過程來進行。典型上是沈 積2至15ιιηι厚之隔離溝渠中間層4 3 6。此種隔離溝渠中 間層4 3 6之形成須整合在一種製程中以形成該隔離溝渠 180，使基板不必由此製程設備中去除。然後沈積此隔 離溝渠填料4 4 0，這是以第5a至5f圖中所示之各步驟來 進行。 本方法用來製成第二種形式之記億體（其具有記億胞 和隔離溝渠1 8 Q )之各步驟至此結束，隨後之各步驟是依 據現有之先前技藝來製成電晶體。 符號之說明 1 0 0，1 0 0’ ....記億胞 10 1.....基板 10 4.....基層氧化物層 105..·..基層停止層 -1 8 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---I ————丨—· I I I (請先閱讀背面之注意事項再填寫本頁) 訂--------- 經濟部智慧財產局員工消費合作社印製 523910 A7 B7_ 15 五、發明說明（） 1 0 8，1 0 8 ’ 溝渠 10 9.....上部區 110 .....電晶體 111 .....下部區 1 12.....閘極 113.....汲極區 1 1 4 .....源極區 117.....通道 120, 121·.··字元線 160.....溝渠式電容器 161，161、..導電性溝渠填料 164, 189..·.介電質層 1 6 5 , 1 6 5 f · . ·.埋入板 168.....隔離領 170.....埋入井 180.....隔離領 183.....接觸區 185.....位元線 2 5 0 .....埋入式接觸區 4 3 0 , 4 3 0 1——溝渠覆蓋介電質 4 3 5 .....隔離溝渠外罩 4 3 6 .....隔離溝渠中間層 4 4 0 .....隔離溝渠填料 5 0 1.....區域 510.....抗反射層 5 2 0 .....光阻層 —1 7 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I i n H ϋ ϋ I m ϋ I I ϋ I n I 一 δ，· I n ·ϋ 1 ϋ ϋ n I (請先閱讀背面之注意事項再填寫本頁)Band 141, No. 5 (1 994), page 1 3 7 8 ff and US Patent 4937205. In the case where the isolation 16 8 is used as a doping mask, an ion implantation method can also be used. Another way is to form the buried plate 165 using a doped silicate glass as a doping substance (for example, AS G). This form is described, for example, in Becker et al., J. Electrochemical. Soc., Band.l36, (1989), page 3033ff. If doped silicate glass is used for doping, it must be removed after forming the buried plate 165. The buried contact region 250 is formed by implanting this doping substance by implantation, plasma doping, or vapor phase doping. A dielectric layer 164 is then formed, which covers the surface of the substrate 101 and the interior of the trench 108. This dielectric layer 164 functions as a dielectric of a memory cell to separate the electrodes of the capacitor. In this form, the dielectric layer 16 is composed of an oxide, a nitride, an oxynitride, or a layer stack (consisting of an oxide layer and an oxide layer). Materials with larger dielectric constants can also be used, for example, T a 0 2 or B S T. Deposition of conductive trench filler 1 6 1 (which may be composed of doped polycrystalline or amorphous silicon) so as to fill the trench 108 and cover the surface of the substrate 1 Q 1. For example, a CVD method or other conventional processes may be used. . Then use the CD E step, the IE step, the chemical drying etching step or the combined CMP-EIE step (CMP: Chemical Mechanical Polishing) to make the conductive trench material 1 6 1 using the appropriate chemical agent. In this case, the filler is leveled and then the filler 16 1 is lowered into the trench 108. In Figure 5b, a trench is deposited covering the dielectric 4 3 0, which may be oxide, nitride or gasified nitride. It can be composed by C Ο, LPC Ο -1 3- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Installation- ------ Order --------- Line j Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 523910 A7 B7 12 V. Description of Invention () (Low pressure CVD) or PECVD (p 1 asa Enhanced CVD). For example, TEOS can be produced using the LPCVD process, or Ozone-TE0S or high-density plasma oxide (HDP Oxide) Another way is to use a selective gasification (Seleox) to form the trench covering the dielectric 4 3 0. This trench covering the dielectric 4 3 0 Therefore, it is possible to selectively stop the base layer 105 and grow on the conductive trench material 161. Then the layer length stops and the layer 3 stops. The base 1 stops and the flat dielectric cover covers the trench 43. The quality is electrical The cover is covered by another channel. The trench is now used as a choice of oxygenation. By this way, the flat layer is formed into a light-shielding plate with an interval layer so that the substrate will be exposed to light. The surface light of ΗΓ: | 5 is accumulated in the current upper layer to resist the ill image display and light exposure in the 5 domain layer area blocks some light, and there are ο, 1 there are 5 division areas to remove some 50, and these 10 are already in layer 2 First stop the first stop layer 5 The first step is to go to the middle of the field. This protection is C. Remove 80. The canal 52S. The trench layer 10. The barrier layer stops light. The stop should be stopped in an unlayered form; 30 It trenches and light blocking have a thickness of about 2 y 5 shells. There's now limited to have the option to choose the line quality of the dielectric cap overlying drainage ditch and installed · ------- --------. Order · 1 Shu! — Thread (please read the notes on the back before filling this page) The gas base and 43 objects are qualitatively the oxygen is here. 3 ^ S $ Carved by Jtf, the second phase of the phase. ίetched ο Ε 0 except RI04 to go temporarily can be borrowed by the Ministry to borrow a layer of 04 1L to remove the trenches and go to this Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative printed 4 medium quality picture 18 electricity 5d The trench cover is blocked in the etching progressing layer of the cover and the light should be removed. For example, etch the silicon agent to learn and change this. F to S-Step B Η Step-The whole thing is here ο 8 2 1 5 Channel layer can block the light. This is when the imaging is visible and C is exposed to the same light step by step. I can be blocked -R is a light silicon type. Paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 523910 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 V. Description of the invention () Removed in the whole process or in the isolation trench 1 8 G is removed after etching. This isolating trench cover 4 3 5 is formed in Fig. 5e in order to reduce the interface state and the resulting leakage current. This can be performed, for example, by thermal oxidation, which forms an oxide with a thickness of 2 to 15 μm Floor. The isolation trench filler 4 4 G is then formed, for example, C V D-TE 0 S, C V D odor-T E 0 S, L P C V D-TE 0 S, H D P oxide or vaporized nitride are deposited as the isolation trench filler 4 4 0. Alternatively, the isolation trench filler 4 4 0 can be made of polycrystalline silicon. In this embodiment, the isolation trench filler 4 4 0 is composed of HDP oxide. Alternatively, the material used to form the isolation trench filler 440 may be compressed by thermal oxidation. In this case, it is not necessary to form the isolation trench cover 4 3 5 because the gasification can be easily diffused through the existing isolation material during this compression process, so that the interface state can be reduced and thus the The resulting leakage current is reduced. Then, the isolation trench filler 4 40 is leveled by the C MP step or the R I E step to the height of the base stop layer 105. Alternatively, a selective oxidation process is used for infiltration in the isolation trench 180. No subsequent leveling process or only a short oxide-CMP process is required (N. Elbel et al., 1989, Symposium on VLSI Technology, page 208 ff.). In this case, the isolation trench cover 4 3 5 Only formed after selective oxidation-deposition by thermal oxidation through the deposited Selox layer. Figure 5f removes this base stop layer 1Q 5. In this case, for example, hot phosphoric acid (H 3 PO 4) or HF vapor is used. In addition, the base oxide layer 104 is removed by HF vapor or BHF, and a sacrificial gate oxide 4 4 5 is subsequently grown. -1 5- (Please read the precautions on the back before filling this page) Binding ----- 4 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Employees of the Intellectual Property Bureau of the Ministry of Economy Cooperative prints 523910 A7 B7__ 14 V. Description of the invention () The steps of this method to make the first form of jiyi body (which has jiyi cell and self-aligned isolation ditch 180) come to an end, followed by Each step is to make the transistor 1 1 G according to the existing prior art, as described in ϋS patent document 5 8 7 4 2 0. Fig. 6 at depicts the manufacture of other types of memorabilia based on Fig. 4 (which has memorizer cells and self-aligned isolation trenches 18Q), which ends at the stage shown in Fig. 5d. The isolation trench outer layer 435 is formed by thermal gasification, and is used to prevent the interface state and the leakage current caused thereby. This isolation trench cover 4 3 5 is typically 2 to 15 nm thick. Then an intermediate layer of isolation trench 4 3 6 (pad) is formed in order to extend the storage time of the memory cells and reduce the refresh frequency. This isolation trench interlayer is typically made of nitride or vaporized nitride, which can be performed, for example, by a CVD process or an LP CVD process. It is typically an intermediate layer of isolation trenches with a thickness of 2 to 15 m thick 4 3 6. The formation of the isolation trench intermediate layer 4 3 6 must be integrated in a process to form the isolation trench 180 so that the substrate does not have to be removed from the process equipment. This isolation ditch filler 4 4 0 is then deposited by performing the steps shown in Figures 5a to 5f. The steps of the method for making a second form of a digitizer (which has a digitizer cell and an isolation trench 18 Q) are now completed, and the subsequent steps are to make a transistor according to the existing prior art. Explanation of Symbols 1 0 0, 1 0 0 '.... Recording 100 million cells 10 1 ..... substrate 10 4 ..... base oxide layer 105 .... base stop layer-1 8- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --- I ———— 丨 —— · III (Please read the precautions on the back before filling this page) Order ----- ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 523910 A7 B7_ 15 V. Description of the invention () 1 0 8, 1 0 8 'Ditch 10 9 ..... Upper area 110 ..... Transistor 111 ..... lower area 1 12 ..... gate 113 ..... drain area 1 1 4 ..... source area 117 ..... channels 120, 121 ... Character line 160 ..... trench capacitors 161, 161, .. conductive trench fillers 164, 189 .... dielectric layers 1 6 5, 1 6 5 f... Buried board 168 ..... Isolation collar 170 ..... Buried well 180 ..... Isolation collar 183 ..... Contact area 185 ..... Bit line 2 5 0 ..... Buried Contact area 4 3 0, 4 3 0 1-trench covering dielectric 4 3 5 ..... isolation trench cover 4 3 6 ..... isolation trench middle layer 4 4 0 .... isolation Trench filler 5 0 1 ..... Area 510 ..... Anti-reflective layer 5 2 0 ..... Photoresist Layer—1 7-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) II in H ϋ ϋ I m ϋ II ϋ I n I-δ, · I n · ϋ 1 ϋ I n I (Please read the notes on the back before filling this page)