DE19944011B4 - Method for forming at least two memory cells of a semiconductor memory - Google Patents

Abstract

A method of forming at least two memory cells of a semiconductor memory (100), the method comprising the following sequence of steps:
- forming two adjacent trenches (108, 108 ') in a substrate (101);
- Forming each of an isolation collar (168, 168 ') in each case an upper region (109, 109') of the trenches (108, 108 ');
- Forming each of a dielectric layer (164, 164 ') on the surface of the respective insulating collar (168, 168') and on the surface of each of a lower portion (111, 111 ') of the trenches (108, 108');
- filling the trenches (108, 108 '), each with a conductive trench filling (161, 161');
Forming a respective dielectric (430, 430 ') on the conductive trench fillings (161, 161');
- etching an isolation trench (180) between the two trenches (108, 108 ') to isolate the trenches (108, 108') from each other, wherein the respective dielectric (430, 430 ') on the respective conductive trench filling (161, 161 ') serves as an etching mask and the isolation trench (180) self-aligned to ...

Description

The The present invention relates to a method of forming at least two memory cells of a semiconductor memory.

integrated Circuits (ICs) or chips contain capacitors for the purpose charge storage, such as a dynamic random access memory with random access (DRAM). The state of charge in the capacitor represents one data bit.

One Contains DRAM chip a matrix of memory cells arranged in the form of rows and columns are and are driven by word lines and bit lines. Reading data from the memory cells and writing of data in the memory cells, is made more suitable by the activation Word lines and bit lines accomplished.

Usually contains a DRAM memory cell connected to a capacitor transistor. The transistor contains two diffusion regions separated by a channel are controlled by a gate. Depending on the direction of the current flow one diffusion region is referred to as a drain and the other as a source. Here is the drain region with the bit line, the source region connected to the trench capacitor and the gate to the word line. By Applying appropriate voltages to the gate will make the transistor so controlled that one Current flow between the drain region and the source region through the channel and is turned off.

The charge stored in the capacitor degrades over time due to leakage currents. Before the charge has degraded to an indeterminate level below a threshold, the storage capacitor must be refreshed, so high leakage currents require a high refresh rate. Because of the refresh, these memory cells are referred to as dynamic RAM (DRAM). From the patent US 5,867,420 A When the features of the preamble of claim 1 are known, a prior art DRAM is known.

A Too little charge in the trench capacitor can affect the functionality and adversely affect the usability of the storage device. If the stored charge is too much degraded, it is no longer possible, read out the information stored in the memory cell with the connected sense amplifiers. The information is lost and there are read errors. To avoid of reading errors offers the reduction of leakage currents. to Reduction of leakage currents are the memory cells through an isolation trench (STI) from each other isolated. Usually the area in which the isolation trench is to be formed will pass through defines a structured photolithographic layer. To is the adjustment of the photo exposure to the already existing ones Structures, such as the trench capacitor. By an inherent Existing Photobright Adjustments inaccuracy there are fluctuations in the position of the isolation trench, relative to the trench capacitor. It happens occasionally, that the Isolation trench a trench capacitor completely from its transistor isolated. The relevant memory cell is thus useless, which is usually for many more memory cells applies, since all memory cells with the same Isolation trench-exposure step be isolated.

Also if the photo-aligner inaccuracies not for complete isolation the trench capacitor leads, so the electrical connection is narrowed by the isolation trench, because the isolation trench partially the trench capacitor and the conductive trench filling replaced. this leads to to heightened Connection Resistors of Trench capacitor to the transistor, which slow memory cells result, which are unusable as a result. The tolerable adjustments inaccuracy is therefore much smaller than the inner diameter of the insulation collar.

at progressive increase The integration density takes both the smallest structural dimension F, as also the photo-aligner adjustments inaccuracy. The ratio of smallest structural dimension F and photo-aligner inaccuracies do not stay constant, because the photo-aligner inaccuracies increases relative to the smallest structural dimension F. The Associated increase the relative fluctuation of subsequent photolithography steps, based on existing structures, therefore, also decreases to.

Out EP 0 715 350 A2 For example, a method is known in which two trenches for trench capacitors are covered with polysilicon. After deposition of a titanium layer and a temperature treatment, the polysilicon is partially converted into titanium silicide, thereby producing respectively electrically conductive structures. The disadvantage, however, that these structures must be removed again, for which an additional process step is required.

The Object of the present invention is therefore in the creation a manufacturing process for a memory where the misalignment between memory cells and isolation trench is reduced to a value that is smaller as the photo-aligner adjustments inaccuracy.

• – Bilden zweier benachbarter Gräben in einem Substrat;
• – Bilden je eines Isolationskragens in je einem oberen Bereich der Gräben;
• – Bilden je einer dielektrischen Schicht auf der Oberfläche des jeweiligen Isolationskragens und auf der Oberfläche je eines unteren Bereichs der Gräben;
• – Füllen der Gräben mit je einer leitenden Grabenfüllung;
• – Bilden je eines Dielektrikums auf den leitenden Grabenfüllungen;
• – Ätzen eines Isolationsgrabens zwischen den beiden Gräben, um die Gräben voneinander zu isolieren, wobei das jeweilige Dielektrikum auf der jeweiligen leitenden Grabenfüllung als Ätzmaske dient und der Isolationsgraben selbstjustiert zu den Gräben geätzt wird;
• – Füllen des Isolationsgrabens mit einem Füllmaterial bis in Höhe des Dielektrikums auf den Grabenfüllungen und
• – Bilden je eines Transistors auf je einer dem Isolationsgraben jeweils abgewandten Seite des jeweiligen Grabens.

According to the invention this object is achieved by solved by a method for forming at least two memory cells of a semiconductor memory, the method comprising the following sequence of steps:

• Forming two adjacent trenches in a substrate;
• - Forming each of an isolation collar in each case an upper region of the trenches;
• Forming a respective dielectric layer on the surface of the respective insulation collar and on the surface of each of a lower region of the trenches;
• - filling the trenches with one conductive trench filling each;
• Forming one dielectric each on the conductive trench fillings;
• - etching an isolation trench between the two trenches to isolate the trenches from each other, the respective dielectric serving as an etching mask on the respective conductive trench filling and the isolation trench being self-aligned etched to the trenches;
• - Fill the isolation trench with a filler up to the level of the dielectric on the trench fillings and
• - Form each of a transistor on each of the isolation trench each side facing away from the respective trench.

The The idea underlying the present invention is in the self-aligned production of the isolation trench. This will the position of the isolation trench independent of the photo-aligner inaccuracies. This is achieved through the use of a trench lid dielectric deposited in the trench achieved, which as an etching mask for the Production of the isolation trench serves. The trench lid dielectric, is not achieved by adjusting a photolithographic exposure formed on already existing structures, but it gets through the structures present on the substrate, in this case by the ditch, at the desired Position formed. Therefore, for the lithography step required to form the isolation trench; requires only a small adjustment accuracy, despite the photo-aligner inaccuracies can be easily adhered to. The photoresist mask covering the area of the isolation trench, therefore does not have the highest requirements can be structured on the photo-intensifier, but can with relaxed adjustment be exposed.

Preferably is provided on the side walls and on the floor of the Isolation trench for trench cladding formed an insulating layer and that one Isolation trench intermediate layer on the insulation layer and on the respective dielectric is formed.

The Isolation trench panel clothes the etched isolation trench. As a result, interface states and leakage currents prevented, which can discharge the capacitor. Through the isolation trench intermediate layer are advantageously extended storage time and the refresh rate lowered.

Preferably it is provided that each insulation collar has a lateral surface, which is characterized by a circumference and a height, wherein the height the lateral surface the insulation collar uniform is.

Preferably it is envisaged that the isolation trench formed entirely outside the trenches becomes. As a result, the conductive trench filling is not removed from the isolation trench affected; the conductive trench filling has the largest possible trench filling width on and allows thereby a low-resistance connection of the transistor to the trench capacitor.

Preferably It is envisaged that each conductive trench filling in each case in one of with the respective isolation collar enclosed area of the trenches a uniform width is formed.

Preferably is provided that the respective dielectric of oxide, nitride or oxynitride is that the Insulation layer consists of oxide, nitride or oxynitride and that the filler for the Isolation trench of oxide, nitride, oxynitride or polysilicon exists. Preferably is provided that the insulation trench intermediate layer of nitride or Oxynitride exists.

The Trench lid dielectric may be oxide, nitride, or oxynitride. the insulation trench cladding made of oxide, nitride or oxynitride, the Isolation trench intermediate layer of nitride and / or the insulation trench filling Oxide, nitride, oxynitride or polysilicon.

The Trench lid dielectric serves as an etching mask for the etching of the self-aligned Isolation trench.

embodiments The present invention is illustrated in the drawings and below explained in more detail.

It demonstrate:

1 an example of a memory with memory cells and isolation trench;

2 another example of a memory with memory cells and isolation trench;

3 an embodiment of a memory with memory cells and isolation trench according to a first embodiment of the method according to the invention;

4 a further embodiment of a memory with memory cells and insulation sheaves according to the present invention, according to a second embodiment of the method according to the invention;

5a - 5f a first embodiment of the inventive method for producing a memory with memory cells and isolation trench after 3 ;

6a . 6b a further embodiment of a memory with memory cells and isolation trench according to the present invention for producing the memory according to 4 ,

In the figures, the same reference numerals designate the same or functionally identical elements. The reference symbols labeled 'designate the same or functionally identical elements of an adjacent memory cell 100 ' ,

Regarding 1 an embodiment of the Applicant on the filing date known memory with memory cells and isolation trench is shown. The illustrated memory cell 100 consists of a trench capacitor 160 and a transistor 110 , The trench capacitor 160 is in a substrate 101 educated. In the substrate 101 is a buried tub 170 introduced, which consists for example of dopant. The trench capacitor 160 has a ditch 108 with an upper area 109 and a lower area 111 on. In the upper area 109 of the trench 108 there is an isolation collar 168 , The lower part of the trench penetrates the buried trough 170 at least partially. To the lower area 111 of the trench 108 is a buried tub 165 arranged, which forms the outer capacitor electrode. The buried plate 165 the memory cell 100 and buried plates 165 ' adjacent memory cells 100 ' be through the buried tub 170 electrically connected to each other.

The lower area 111 of the trench 108 and the isolation collar 168 are with a dielectric layer 164 clad, which the memory dielectric of the trench capacitor 160 forms. The dielectric layer 164 can be made of layers or layer stacks, which consist of oxide, nitride or oxynitride. Also, memory dielectrics having a high dielectric constant, such as tantalum oxide (TaO ₂ ), BST (barium strontium titanate), and any other suitable dielectric may be used.

The ditch 108 is with a conductive trench filling 161 filled, which forms the inner capacitor electrode.

The transistor 110 consists of a source area 114 and a drain region 113 which comes with a rimless contact 183 connected is. Furthermore, there is the transistor 110 from a channel 117 passing through a gate 112 is controlled. The gate 112 is with a wordline 120 connected. The borderless contact 183 is with a bit line 185 connected above a dielectric layer 189 runs. In the area of the source area 114 there is a buried contact in this variant 250 ,

Above an isolation trench 180 runs in this variant, a passing word line 121 (passing word line) passing through the insulation sheaves 180 from the conductive trench filling 161 is isolated. The isolation trench 180 is partially in the ditch 108 formed so that the conductive trench filling 161 in the upper area 109 of the trench 108 through the isolation trench 180 is replaced. This is the trench filling width 500 in the upper area 109 of the trench 108 not constant, but rejuvenates at the top of the ditch 108 due to the width of the isolation trench 180 ,

In 2 a further embodiment of a memory with memory cell and isolation trench is shown. In the 2 variant shown differs from that in 1 shown variant by the position of the isolation trench 180 , due to the photo-aligner inaccuracies, the conductive trench filling 161 from the source area 114 of the transistor 110 completely isolated and the memory cell 100 makes us unusable.

Regarding 3 A first embodiment of the present invention is shown. The illustrated memory cell 100 consists of a trench capacitor 160 and a transistor 110 , The trench capacitor 160 is in a substrate 101 educated. In the substrate 101 is a buried tub 170 introduced, which consists for example of dopant. The trench capacitor 160 has a ditch 108 with an upper area 109 and a lower area 111 on. In the upper area 109 of the trench 108 there is an isolation collar 168 , The lower part of the trench penetrates the buried tub 170 at least partially. To the lower area 111 of the trench 108 is a buried plate 165 arranged, which forms the outer capacitor electrode. The buried plate 165 the memory cell 100 and buried plates 165 ' adjacent memory cells 100 ' be through the buried tub 170 electrically connected to each other.

The lower part of the trench 108 and the isolation collar 168 are with a dielectric layer 164 clad, which is the storage dielectric of the trench capacitor 160 forms. The dielectric layer 164 can be made of layers or layer stacks, which consist of oxide, nitride or oxynitride. Also, memory dielectrics having a high dielectric constant, such as tantalum oxide (TaO ₂ ), BST (barium strontium titanate), and any other suitable dielectric may be used.

The ditch 108 is with a conductive trench filling 161 filled, which forms the inner capacitor electrode.

The transistor 110 consists of a source area 114 and a drain region 113 which comes with a rimless contact 183 connected is. Furthermore, there is the transistor 110 from a channel 117 passing through a gate 112 is controlled. The gate 112 is with a wordline 120 connected. The borderless contact 183 is with a bit line 185 connected above a dielectric layer 189 runs.

Between the memory cell 100 and an adjacent memory cell 100 ' there is an isolation ditch 180 , The isolation trench 180 consists of an isolation trench cladding 435 that the isolation trench 180 dressed. Furthermore, there is the isolation trench 180 from a trench lid dielectric 430 , which is above the conductive trench filling 161 in the ditch 108 located. In addition, there is the isolation trench 180 from a second trench lid dielectric 430 ' , which is above a conductive trench filling 161 ' in a ditch 108 ' is the part of the adjacent memory cell 100 ' is. Finally, there is the isolation trench 180 still from an isolation trench filling 440 , which is the isolation trench 180 fills.

The one of the isolation collar 168 enclosed area 501 of the trench 108 is with the conductive trench filling 161 filled in the enclosed area 501 a uniform trench filling width 500 having.

In 4 a further embodiment of the memory according to the invention with memory cells and isolation trench is shown, which differs from the in 3 variant shown by an isolation trench intermediate layer 436 which distinguishes the isolation trench 180 in addition to the insulation trench cladding 435 dressed.

Regarding 5a becomes the substrate 101 provided on which the DRAM memory cell is to be manufactured. In the present variant, the substrate 101 lightly doped with p-type dopants, such as boron. In the substrate 101 At an appropriate depth, an n-doped buried well will be formed 170 educated. For doping the buried tub 170 For example, phosphorus or arsenic may be used as the dopant. The buried tub 170 can be generated for example by implantation. It serves to insulate the p-well from the substrate 101 and additionally forms a conductive connection between the buried plate 165 the memory cell 100 and buried plates 165 ' adjacent memory cells 100 ' , Alternatively, the buried tub 170 be formed by epitaxially grown, doped silicon layers or by a combination of crystal growth (epitaxy) and implantation. This technique is described in US Pat. No. 5,250,829 to Bronner et al. described.

A sub-base stack is placed on the surface of the substrate 101 formed and includes, for example, a substructure oxide layer 104 and a subgrade stop layer 105 , which can be used as polish or etch stop and consists for example of nitride. Above the subgrade stop layer 105 a hard mask layer is provided; which may consist of TEOS (tetra-ethyl-ortho-silicate) or other materials, such as borosilicate glass (BSG). In addition, an anti-reflection coating (ARC) can be used to improve lithographic resolution.

The hardmask layer is patterned using conventional photolithographic techniques to define a region in which the trench 108 is to be formed. Subsequently, the hard mask layer is used as an etching mask for a reactive ion etching step (RIE, Reactice Ion Etch), which forms the deep trench 108 forms.

For the production of the isolation collar 168 the trench is filled with a Isolationskragenopferschicht, which extends to the bottom of the insulating collar to be formed 168 Will get removed. Subsequently, a dielectric layer is deposited on the wafer, which covers the substrate surface and the sidewalls of the trench 108 in its upper area 109 covered. The dielectric layer becomes the formation of the isola tion collar 168 used and consists for example of oxide. Subsequently, the dielectric layer is etched, for example, by reactive ion etching (RIE) or by CDE (Chemical Dry Etch), around the insulation collar 168 to build.

The chemical means for the reactive ion etching are chosen such that the oxide is selectively etched against the polysilicon of the insulation collar sacrificial layer and the nitride of the hard mask layer. Subsequently, the insulation collar sacrificial layer is removed from the lower region of the trench 108 away. This is preferably achieved by CDE using a thin, native oxide layer as a CDE etch stop.

Subsequently, a buried plate 165 formed with n-type dopants, such as arsenic or phosphorus as the outer capacitor electrode. The isolation collar 168 serves as a doping mask, which the dopant on the lower area 111 of the trench 108 limited. To the formation of the buried plate 165 For example, gas phase doping, plasma doping, or plasma immersion ion implantation (PIII) may be used. These techniques are described, for example, in Ransom et al., J. Electrochemical. Soc., Vol. 141, No. 5 (1994), pp. 1378 et seq., And US Patent 4,937,205. described. An ion implantation using the isolation collar 168 as doping mask is also possible. Alternatively, the buried plate 165 be formed using a doped silicate glass as a dopant, such as ASG. This variant is for example in Becker et al., J. Electrochemical. Soc., Vol. 136, (1989), p. 3033 et seq. If doped silicate glass is used for doping, it will after the formation of the buried plate 165 away.

The buried contact 250 is formed by introducing dopant by implantation, by plasma doping or by gas phase doping.

Subsequently, a dielectric layer 164 formed, which is the surface of the substrate 101 and the interior of the trench 108 covered. The dielectric layer 164 serves as a storage dielectric, for separating the capacitor electrodes. In one variant, the dielectric layer is made 164 oxide, nitride, oxynitride or a layer stack of oxide and nitride layers. Also, materials with a high dielectric constant, such as TaO ₂ or BST can be used.

The conductive trench filling 161 , which may be made of doped poly or amorphous silicon, for example, is used to fill the trench 108 and covering the surface of the substrate 101 deposited. For example, CVD (Chemical Vapor Deposition) or other known process techniques may be used. Subsequently, the conductive trench filling 161 for example, in a CDE step, in an RIE step, in a dry chemical etch step, or in a CMP combined chemical mechanical planarization (CMP) step, using appropriate chemicals, and then into the trench 108 sunk.

Regarding 5b becomes the trench lid dielectric 430 deposited, which may consist of oxide, nitride or oxynitride and by means of CVD, LPCVD (Low Pressure CVD) or PECVD (Plasma Enhanced CVD) can be deposited. For example, TEOS (tetra-ethyl-ortho-silicate) may be produced by an LPCVD process, or ozone-TEOS or high-density plasma oxide (HDP-oxide) may be used. Alternatively, selective oxidation (Selox, Selective Oxide) can be used to form the trench lid dielectric 430 be used. This is the grave lid dielectric 430 , selective to the subgrade stop layer 105 , on the leading trench filling 161 grew up. Subsequently, the trench lid dielectric 430 planarizes and closes at the level of the subgrade stop layer 105 from. Alternatively, the trench lid dielectric 430 already planarized during the growth process. This is made possible by the Selox process.

An antireflection coating will now be applied to the substrate surface 510 and a photoresist layer 520 deposited. Subsequently, the photoresist layer 520 exposed and developed so that only in the areas where the photoresist layer 520 was removed, the isolation trench 180 can be formed.

In 5c First, the substructure stop layer 105 removed in areas not covered by the photoresist layer 520 to be protected. Removing the Underground Stop Layer 105 becomes selective to the existing photoresist layer 520 and the trench lid dielectric 430 carried out. Due to the finite selectivity, there is some photoresist and also part of the trench lid dielectric 430 away. In a second etching step, the substructure oxide layer 104 removed by a short RIE oxide etch process. This is the grave lid dielectric 430 at the same rate as the substructure oxide layer 104 etched.

Regarding 5d becomes the photoresist layer 520 removed and the insulation sheaves 180 etched with a silicon RIE step. For the silicon RIE step, chemicals such as NF ₃ -HBr or SiF _{6 are} suitable.

Alternatively, the exposure and development of the photoresist may be performed in an integrated process along with the formation of the isolation trench 180 be performed. For this, the photoresist layer 520 during the integrated process or after the etching of the isolation trench 180 away.

Regarding 5e becomes the isolation trench panel 435 formed to reduce interface conditions and resulting leakage currents. This can be done for example with a thermal oxidation, which is an oxide layer of 2 to 15 nm forms. Subsequently, the isolation trench filling 440 educated. These include, for example, CVD-TEOS, CVD-ozone-TEOS, LPCVD-TEOS, HDP-oxide, or oxynitride as isolation trench filling 440 deposited. Alternatively it is possible to fill the isolation trench 440 made of polysilicon. In this embodiment, the isolation trench filling 440 made of HDP oxide. Optionally, the material from which the isolation trench filling 440 consists of being compacted by thermal oxidation. In this case, the formation of the isolation trench cladding 435 be dispensed with, since oxygen in the compression process very easily diffused through the existing insulating material and thus reduces the interface states and a resulting leakage current.

Subsequently, the isolation trench filling 440 by a CMP or RIE step up to the height of the subgrade stop layer 105 planarized.

Alternatively, the insulation sheaves 180 be filled with a Selox process. In this case, no subsequent planarization process, or only a short oxide-CMP process is necessary (N. Elbel et al., 1989, Symposium on VLSI Technology, 5.208 ff.). In this case, the isolation trench cladding becomes 435 formed only after the Selox deposition by thermal oxidation through the deposited Selox layer.

Regarding 5f becomes the substructure stop layer 105 away. For example, hot phosphoric acid (H ₃ PO ₄ or HF vapor) may be used. Furthermore, the substructure oxide layer becomes 104 with the help of HF vapor or BHF removed and then a sacrificial gate oxide 445 grew up.

Thus, the method for producing a first variant of a memory with memory cells and self-aligned insulation sheaves 180 completed and the subsequent process steps are used to the transistor 110 to produce the existing state of the art, as described for example in US Patent 5,867,420 A.

In 6a is the production of the variant of a memory with memory cells and self-aligned insulation sheaves 180 to 4 described to the process stage 5d followed. It will be the isolation trench cladding 435 formed by thermal oxidation. It serves to avoid interface states and resulting leakage currents. The isolation trench panel 435 is typically 2 to 15 nm thick. Subsequently, an isolation trench intermediate layer 436 (Liner) formed to extend the storage time of the memory cells and to lower the refresh rate. In this case, the insulation trench intermediate layer is typically made of nitride or oxynitride, which can be carried out, for example, with a CVD process or an LPCVD process. Typically, the isolation trench interlayer becomes 436 2 to 15nm thick deposited. The formation of the isolation trench intermediate layer 436 becomes in the process flow to the formation of the isolation trench 180 integrated, that the substrate does not have to be removed from the processing plant. Subsequently, the isolation trench filling 440 separated, what with the already too 5a to 5f explained process steps is performed.

Thus, the method for producing a second variant of a memory with memory cells and isolation trench 180 completed and the subsequent process steps serve to produce the transistor according to the existing state of the art.

Claims (7)

Method for forming at least two memory cells of a semiconductor memory ( 100 ), the method comprising the following sequence of steps: - forming two adjacent trenches ( 108 . 108 ' ) in a substrate ( 101 ); - forming one insulation collar each ( 168 . 168 ' ) in a respective upper area ( 109 . 109 ' ) of the trenches ( 108 . 108 ' ); Forming a dielectric layer ( 164 . 164 ' ) on the surface of the respective insulation collar ( 168 . 168 ' ) and on the surface of a lower area ( 111 . 111 ' ) of the trenches ( 108 . 108 ' ); - filling the trenches ( 108 . 108 ' ) each with a conductive trench filling ( 161 . 161 ' ); - Forming each of a dielectric ( 430 . 430 ' ) on the conductive trench fillings ( 161 . 161 ' ); - etching an isolation trench ( 180 ) between the two trenches ( 108 . 108 ' ) to the trenches ( 108 . 108 ' ) isolate each other, the respective dielectric ( 430 . 430 ' ) on the respective conductive trench filling ( 161 . 161 ' ) serves as an etching mask and the isolation trench ( 180 ) self-aligned to the trenches ( 108 . 108 ' ) is etched; - filling the isolation trench ( 180 ) with a filling material ( 440 ) up to the level of the dielectric ( 430 . 430 ' ) on the trench fillings ( 161 . 161 ' ) and - each forming a transistor ( 110 . 110 ' ) on each of the isolation trench each side remote from the respective trench ( 108 . 108 ' ). Method according to claim 1, characterized in that on the side walls and on the bottom of the isolation trench ( 180 ) for trench lining an insulation layer ( 435 ) is formed and that an isolation trench intermediate layer ( 436 ) on the insulation layer ( 435 ) and on the respective dielectric ( 430 . 430 ' ) is formed. Method according to one of claims 1 or 2, characterized in that each insulation collar ( 168 . 168 ' ) has a lateral surface which is characterized by a circumference and a height, wherein the height of the lateral surface of the insulation collar ( 168 . 168 ' ) is uniform. Method according to one of claims 1 to 3, characterized in that the isolation trench ( 180 ) completely outside the trenches ( 108 . 108 ' ) is formed. Method according to one of claims 1 to 4, characterized in that each conductive trench filling ( 161 . 161 ' ) in each case in one of the respective insulation collar ( 168 . 168 ' ) enclosed area ( 501 . 501 ' ) of the trenches ( 108 . 108 ' ) with a uniform width ( 500 ) is formed. Method according to one of claims 1 to 5, characterized in that the respective dielectric ( 430 . 430 ' ) consists of oxide, nitride or oxynitride that the insulating layer ( 435 ) consists of oxide, nitride or oxynitride and that the filling material for the isolation trench ( 440 ) consists of oxide, nitride, oxynitride or polysilicon. Method according to claim 2, characterized in that the isolation trench intermediate layer ( 436 ) consists of nitride or oxynitride.