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TW202439937A - Memory device and method of fabricating the same - Google Patents

Memory device and method of fabricating the same Download PDF

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TW202439937A
TW202439937A TW112110385A TW112110385A TW202439937A TW 202439937 A TW202439937 A TW 202439937A TW 112110385 A TW112110385 A TW 112110385A TW 112110385 A TW112110385 A TW 112110385A TW 202439937 A TW202439937 A TW 202439937A
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layer
conductive
extension portion
column
insulating
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TW112110385A
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TWI840172B (en
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洪敏峰
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旺宏電子股份有限公司
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Abstract

A memory device includes a stacked structure, a channel pillar, a plurality of conductive pillars, and a slit. The stacked structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The channel pillar extends through the stacked structure. The plurality of conductive pillars are located in the channel pillar and electrically connected with the channel pillar. The charge storage structure is located between the plurality of conductive layers and the channel pillar. The slit is located in the stacked structure. The slit includes a body part and an extension part. The body part extends through the stacked structure. The extension part is connected to the body part and located between the stacked structure and the dielectric substrate. Th memory may be applied in 3D AND flash memory.

Description

記憶體元件及其製造方法Memory device and manufacturing method thereof

本發明實施例是有關於一種半導體元件及其製造方法,且特別是有關於一種記憶體元件及其製造方法。The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory device and a manufacturing method thereof.

非揮發性記憶體元件(如,快閃記憶體)由於具有使存入的資料在斷電後也不會消失的優點,因此成為個人電腦和其他電子設備所廣泛採用的一種記憶體元件。Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure. Therefore, they have become a type of memory device widely used in personal computers and other electronic devices.

目前業界較常使用的快閃記憶體陣列包括反或閘(NOR)快閃記憶體與反及閘(NAND)快閃記憶體。由於NAND快閃記憶體的結構是使各記憶胞串接在一起,其積集度與面積利用率較NOR快閃記憶體佳,已經廣泛地應用在多種電子產品中。此外,為了進一步地提升記憶體元件的積集度,發展出一種三維NAND快閃記憶體。然而,仍存在許多與三維NAND快閃記憶體相關的挑戰。The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory.

本發明提供一種記憶體元件及其製造方法可以避免導體柱與堆疊閘極下方的導體層發生不正常橋接的問題。The present invention provides a memory element and a manufacturing method thereof, which can avoid the problem of abnormal bridging between a conductor column and a conductor layer below a stacked gate.

本發明的實施例的一種記憶體元件,包括堆疊結構、通道柱、多個導體柱以及分隔牆。所述堆疊結構,位於介電基底上,包括彼此交替堆疊的多個導體層與多個絕緣層。所述通道柱,延伸穿過所述堆疊結構。所述多個導體柱,位於所述通道柱內,且與所述通道柱電性連接。所述電荷儲存結構,位於所述多個導體層與所述通道柱之間。所述分隔牆,位於所述堆疊結構中。所述分隔牆包括:主體部與延伸部。所述主體部,延伸穿過所述堆疊結構。所述延伸部,與所述主體部連接,位於所述堆疊結構與所述介電基底之間。A memory element of an embodiment of the present invention includes a stacking structure, a channel column, a plurality of conductive columns, and a partition wall. The stacking structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers alternately stacked with each other. The channel column extends through the stacking structure. The plurality of conductive columns are located in the channel column and are electrically connected to the channel column. The charge storage structure is located between the plurality of conductive layers and the channel column. The partition wall is located in the stacking structure. The partition wall includes: a main body and an extension portion. The main body extends through the stacking structure. The extension portion is connected to the main body and is located between the stacking structure and the dielectric substrate.

本發明的實施例的一種記憶體元件的製造方法,包括以下步驟。形成第一導體層於介電基底上。形成堆疊結構於導體層上。所述堆疊結構包括彼此交替堆疊的多個中間層與多個絕緣層。形成通道柱延伸穿過所述堆疊結構與所述第一導體層。於所述通道柱內形成與所述通道柱電性連接的多個導體柱。形成分隔溝渠,延伸穿過所述堆疊結構與所述第一導體層。移除部分所述第一導體層、部分所述通道柱以及部分所述多個導體柱,以形成第一水平開口。局部地移除所述多個中間層,以形成多個第二水平開口。於所述第一水平開口以及所述多個第二水平開口中形成電荷儲存層。於所述多個第二水平開口中形成多個第二導體層。於所述分隔溝渠分隔牆的主體部,並在所述第一水平開口之中形成所述分隔牆的延伸部。A method for manufacturing a memory element according to an embodiment of the present invention comprises the following steps. A first conductive layer is formed on a dielectric substrate. A stacking structure is formed on the conductive layer. The stacking structure comprises a plurality of intermediate layers and a plurality of insulating layers alternately stacked with each other. A channel column is formed to extend through the stacking structure and the first conductive layer. A plurality of conductive columns electrically connected to the channel column are formed in the channel column. A separation trench is formed to extend through the stacking structure and the first conductive layer. A portion of the first conductive layer, a portion of the channel column, and a portion of the plurality of conductive columns are removed to form a first horizontal opening. The plurality of intermediate layers are partially removed to form a plurality of second horizontal openings. A charge storage layer is formed in the first horizontal opening and the plurality of second horizontal openings. A plurality of second conductive layers are formed in the plurality of second horizontal openings. An extension portion of the partition wall is formed in the main body of the partition trench and in the first horizontal opening.

基於上述,本發明實施例之記憶體元件將原本設置在堆疊結構下方的導體層移除,再重新形成絕緣層可以避免導體柱與堆疊閘極下方的導體層發生不正常橋接的問題。Based on the above, the memory element of the embodiment of the present invention removes the conductive layer originally disposed under the stacked structure and then re-forms the insulating layer to avoid the problem of abnormal bridging between the conductive pillar and the conductive layer under the stacked gate.

圖1A示出根據一些實施例的3D AND快閃記憶體陣列的電路圖。圖1B示出圖1A中部分的記憶體陣列的局部三維視圖。圖1C與圖1D示出圖1B的切線I-I’的剖面圖。圖1E示出圖1B、圖1C與圖1D的切線II-II’的上視圖。FIG1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG1B shows a partial three-dimensional view of a portion of the memory array in FIG1A. FIG1C and FIG1D show cross-sectional views of the cut line I-I' of FIG1B. FIG1E shows a top view of the cut line II-II' of FIG1B, FIG1C, and FIG1D.

圖1A為包括配置成列及行的垂直AND記憶體陣列10的2個區塊BLOCK (i)與BLOCK (i+1)的示意圖。區塊BLOCK (i)中包括記憶體陣列A (i)。記憶體陣列A (i)的一列(例如是第m+1列)是具有共同字元線(例如WL (i) m+1)的AND記憶單元20集合。記憶體陣列A (i)的每一列(例如是第m+1列)的AND記憶單元20對應於共同字元線(例如WL (i) m+1),且耦接至不同的源極柱(例如SP (i) n與SP (i) n+1)與汲極柱(例如DP (i) n與DP (i) n+1),從而使得AND記憶單元20沿共同字元線(例如WL (i) m+1)邏輯地配置成一列。 FIG1A is a schematic diagram of two blocks BLOCK (i) and BLOCK (i+1) of a vertical AND memory array 10 arranged in rows and columns. Block BLOCK (i) includes a memory array A (i) . A column (e.g., the m+1th column) of the memory array A (i) is a set of AND memory cells 20 having a common word line (e.g., WL (i) m+1 ). The AND memory cells 20 in each column (e.g., the m+1th column) of the memory array A (i) correspond to a common word line (e.g., WL (i) m+1 ) and are coupled to different source poles (e.g., SP (i) n and SP (i) n+1 ) and drain poles (e.g., DP (i) n and DP (i) n+1 ), so that the AND memory cells 20 are logically arranged in a row along the common word line (e.g., WL (i) m+1 ).

記憶體陣列A (i)的一行(例如是第n行)是具有共同源極柱(例如SP (i) n)與共同汲極柱(例如DP (i) n)的AND記憶單元20集合。記憶體陣列A (i)的每一行(例如是第n行)的AND記憶單元20對應於不同字元線(例如WL (i) m+1與WL (i) m),且耦接至共同的源極柱(例如SP (i) n)與共同的汲極柱(例如DP (i) n)。因此,記憶體陣列A (i)的AND記憶單元20沿共同源極柱(例如SP (i) n)與共同汲極柱(例如DP (i) n)邏輯地配置成一行。在實體佈局中,根據所應用的製造方法,行或列可經扭曲,以蜂巢式模式或其他方式配置,以用於高密度或其他原因。 A row (e.g., the nth row) of the memory array A (i) is a set of AND memory cells 20 having a common source column (e.g., SP (i) n ) and a common drain column (e.g., DP (i) n ). The AND memory cells 20 of each row (e.g., the nth row) of the memory array A (i) correspond to different word lines (e.g., WL (i) m+1 and WL (i) m ) and are coupled to a common source column (e.g., SP (i) n ) and a common drain column (e.g., DP (i) n ). Therefore, the AND memory cells 20 of the memory array A (i) are logically arranged in a row along the common source column (e.g., SP (i) n ) and the common drain column (e.g., DP (i) n ). In the physical layout, depending on the manufacturing method applied, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

在圖1A中,在區塊BLOCK (i)中,記憶體陣列A (i)的第n行的AND記憶單元20共用共同的源極柱(例如SP (i) n)與共同的汲極柱(例如DP (i) n)。第n+1行的AND記憶單元20共用共同的源極柱(例如SP (i) n+1)與共同的汲極柱(例如DP (i) n+1)。 In FIG. 1A , in block BLOCK (i) , the AND memory cells 20 in the nth row of the memory array A (i) share a common source column (e.g., SP (i) n ) and a common drain column (e.g., DP (i) n ). The AND memory cells 20 in the n+1th row share a common source column (e.g., SP (i) n+1 ) and a common drain column (e.g., DP (i) n+1 ).

共同的源極柱(例如SP (i) n)耦接至共同的源極線(例如SL n);共同的汲極柱(例如DP (i) n)耦接至共同的位元線(例如BL n)。共同的源極柱(例如SP (i) n+1)耦接至共同的源極線(例如SL n+1);共同的汲極柱(例如DP (i) n+1)耦接至共同的位元線(例如BL n+1)。 A common source column (e.g., SP (i) n ) is coupled to a common source line (e.g., SL n ); a common drain column (e.g., DP (i) n ) is coupled to a common bit line (e.g., BL n ). A common source column (e.g., SP (i) n+1 ) is coupled to a common source line (e.g., SL n+1 ); a common drain column (e.g., DP (i) n+1 ) is coupled to a common bit line (e.g., BL n+1 ).

相似地,區塊BLOCK (i+1)包括記憶體陣列A (i+1),其與在區塊BLOCK (i)中的記憶體陣列A (i)相似。記憶體陣列A (i+1)的一列(例如是第m+1列)是具有共同字元線(例如WL (i+1) m+1)的AND記憶單元20集合。記憶體陣列A (i+1)的每一列(例如是第m+1列)的AND記憶單元20對應於共同字元線(例如WL (i+1) m+1),且耦接至不同的源極柱(例如SP (i+1) n與SP (i+1) n+1)與汲極柱(例如DP (i+1) n與DP (i+1) n+1)。記憶體陣列A (i+1)的一行(例如是第n行)是具有共同源極柱(例如SP (i+1) n)與共同汲極柱(例如DP (i+1) n)的AND記憶單元20集合。記憶體陣列A (i+1)的每一行(例如是第n行)的AND記憶單元20對應於不同字元線(例如WL (i+1) m+1與WL (i+1) m),且耦接至共同的源極柱(例如SP (i+1) n)與共同的汲極柱(例如DP (i+1) n)。因此,記憶體陣列A (i+1)的AND記憶單元20沿共同源極柱(例如SP (i+1) n)與共同汲極柱(例如DP (i+1) n)邏輯地配置成一行。 Similarly, block BLOCK (i+1) includes a memory array A (i+1) that is similar to the memory array A (i) in block BLOCK (i) . A row (e.g., the m+1th row) of the memory array A (i+1) is a set of AND memory cells 20 having a common word line (e.g., WL (i+1) m+1 ). Each row (e.g., the m+1th row) of the memory array A (i+1) corresponds to the common word line (e.g., WL (i+1) m+1 ) and is coupled to different source poles (e.g., SP (i+1) n and SP (i+1) n+1 ) and drain poles (e.g., DP (i+1) n and DP (i+1) n+1 ). A row (e.g., the nth row) of the memory array A (i+1) is a set of AND memory cells 20 having a common source pole (e.g., SP (i+1) n ) and a common drain pole (e.g., DP (i+1) n ). The AND memory cells 20 of each row (e.g., the nth row) of the memory array A (i+1) correspond to different word lines (e.g., WL (i+1) m+1 and WL (i+1) m ) and are coupled to a common source pole (e.g., SP (i+1) n ) and a common drain pole (e.g., DP (i+1) n ). Therefore, the AND memory cells 20 of the memory array A (i+1) are logically arranged in a row along a common source pole (eg, SP (i+1) n ) and a common drain pole (eg, DP (i+1) n ).

區塊BLOCK (i+1)與區塊BLOCK (i)共用源極線(例如是SL n與SL n+1)與位元線(例如BL n與BL n+1)。因此,源極線SL n與位元線BL n耦接至區塊BLOCK (i)的AND記憶體陣列A (i)中的第n行AND記憶單元20,且耦接至區塊BLOCK (i+1)中的AND記憶體陣列A (i+1)中的第n行AND記憶單元20。同樣,源極線SL n+1與位元線BL n+1耦接至區塊BLOCK (i)的AND記憶體陣列A (i)中的第n+1行AND記憶單元20,且耦接至區塊BLOCK (i+1)中的AND記憶體陣列A (i+1)中的第n+1行AND記憶單元20。 Block BLOCK (i+1) and block BLOCK (i) share a source line (e.g., SL n and SL n+1 ) and a bit line (e.g., BL n and BL n+1 ). Therefore, source line SL n and bit line BL n are coupled to the n-th row AND memory cell 20 in AND memory array A (i) of block BLOCK (i) , and are coupled to the n-th row AND memory cell 20 in AND memory array A (i+1) of block BLOCK (i +1) . Similarly, source line SLn+1 and bit line BLn +1 are coupled to the n+1th row AND memory cell 20 in AND memory array A (i) of block BLOCK (i) , and are coupled to the n+1th row AND memory cell 20 in AND memory array A (i+1) in block BLOCK (i+1) .

請參照圖1B至圖1D,記憶體陣列10可安置於半導體晶粒的內連線結構上,諸如,安置於在半導體基底上形成的一或多個主動元件(例如電晶體)上方。因此,介電基底(或稱為介電層)50例如是形成於矽基板上的金屬內連線結構上方的介電層,例如氧化矽層。記憶體陣列10可包括堆疊結構52、多個通道柱16、多個第一導體柱(又可稱為源極柱)32a與多個第二導體柱(又可稱為汲極柱)32b和多個電荷儲存結構40。1B to 1D , the memory array 10 may be disposed on the interconnect structure of a semiconductor die, for example, disposed on one or more active devices (such as transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate (or dielectric layer) 50 is, for example, a dielectric layer formed on a metal interconnect structure on a silicon substrate, such as a silicon oxide layer. The memory array 10 may include a stacked structure 52, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a and a plurality of second conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.

請參照圖1B,堆疊結構52形成在介電基底50上。堆疊結構52包括在介電基底50的表面50s上垂直堆疊的多個閘極層(又稱為字元線或導體層)38與多層的絕緣層54。在第三方向Z上,這些閘極層38藉由設置在其彼此之間的絕緣層54電性隔離。閘極層38在與介電基底50的表面平行的方向上延伸。階梯區(未示出)的閘極層38可具有階梯結構(未示出)。因此,下部的閘極層38比上部閘極層38長,且下部的閘極層38的末端橫向延伸出上部閘極層38的末端。用於連接閘極層38的接觸窗(未示出)可著陸於閘極層38的末端,藉以將各層閘極層38連接至各個導線。1B , a stacked structure 52 is formed on a dielectric substrate 50. The stacked structure 52 includes a plurality of gate layers (also referred to as word lines or conductor layers) 38 vertically stacked on a surface 50s of the dielectric substrate 50 and a plurality of insulating layers 54. In a third direction Z, these gate layers 38 are electrically isolated by the insulating layers 54 disposed therebetween. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layer 38 of the step region (not shown) may have a step structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contacts (not shown) for connecting the gate layers 38 may be landed at the ends of the gate layers 38, thereby connecting each gate layer 38 to each wire.

請參照圖1B至圖1D,記憶體陣列10還包括多個通道柱16、絕緣柱28、多個第一導體柱32a與多個第二導體柱32b,形成於延伸穿過堆疊結構52的垂直通道孔(未示出)之中。通道柱16連續延伸穿過堆疊結構52。在一些實施例中,通道柱16於上視角度來看可具有環形的輪廓。通道柱16的材料可以是半導體,例如是未摻雜的多晶矽。在此例中,第一導體柱32a做為源極柱;第二導體柱32b做為汲極柱。第一導體柱32a與第二導體柱32b以及絕緣柱28各自在垂直於閘極層38的表面(即XY平面)的方向(即第三方向Z)上延伸。第一導體柱32a與第二導體柱32b藉由絕緣柱28分隔,且被絕緣填充層24環繞。第一導體柱32a與第二導體柱32b電性連接該通道柱16。第一導體柱32a與第二導體柱32b包括摻雜的多晶矽或金屬材料。絕緣柱28例如是氮化矽或是氧化矽,絕緣填充層24例如是氧化矽。1B to 1D , the memory array 10 further includes a plurality of channel pillars 16, an insulating pillar 28, a plurality of first conductive pillars 32a, and a plurality of second conductive pillars 32b, which are formed in a vertical channel hole (not shown) extending through the stacked structure 52. The channel pillars 16 extend continuously through the stacked structure 52. In some embodiments, the channel pillars 16 may have an annular profile when viewed from above. The material of the channel pillars 16 may be a semiconductor, such as undoped polysilicon. In this example, the first conductive pillars 32a serve as source pillars; and the second conductive pillars 32b serve as drain pillars. The first conductive pillar 32a, the second conductive pillar 32b and the insulating pillar 28 each extend in a direction (i.e., a third direction Z) perpendicular to the surface (i.e., the XY plane) of the gate layer 38. The first conductive pillar 32a and the second conductive pillar 32b are separated by the insulating pillar 28 and surrounded by the insulating filling layer 24. The first conductive pillar 32a and the second conductive pillar 32b are electrically connected to the channel pillar 16. The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating pillar 28 is, for example, silicon nitride or silicon oxide, and the insulating filling layer 24 is, for example, silicon oxide.

請參照圖1C與圖1D,電荷儲存結構40設置於通道柱16與多個閘極層(或稱導體層)38之間。電荷儲存結構40可以包括穿隧層(或稱為能隙工程穿隧氧化層)14、電荷儲存層12以及阻擋層36。電荷儲存層12位於穿隧層14與阻擋層36之間。在一些實施例中,穿隧層14以及阻擋層36包括氧化矽。電荷儲存層12包括氮化矽,或其他包括可以捕捉以電荷的材料。在一些實施例中,如圖1C所示,電荷儲存結構40的一部分(穿隧層14與電荷儲存層12)在垂直於閘極層38的方向(即第三方向Z)上連續延伸,而電荷儲存結構40的另一部分(阻擋層36)環繞於閘極層38的周圍。在另一些實施例中,如圖1D所示,電荷儲存結構40(穿隧層14、電荷儲存層12與阻擋層36)環繞於閘極層38的周圍。1C and 1D , the charge storage structure 40 is disposed between the channel pillar 16 and a plurality of gate layers (or conductor layers) 38. The charge storage structure 40 may include a tunneling layer (or a gap-engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14 and the blocking layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can capture charges. In some embodiments, as shown in FIG1C , a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the third direction Z), and another portion of the charge storage structure 40 (the blocking layer 36) surrounds the gate layer 38. In other embodiments, as shown in FIG1D , the charge storage structure 40 (the tunneling layer 14, the charge storage layer 12, and the blocking layer 36) surrounds the gate layer 38.

請參照圖1E,電荷儲存結構40、通道柱16以及源極柱32a與汲極柱32b被閘極層38環繞,並且界定出記憶單元20。記憶單元20可藉由不同的操作方法進行1位元操作或2位元操作。舉例來說,在對源極柱32a與汲極柱32b施加電壓時,由於源極柱32a與汲極柱32b與通道柱16連接,因此電子可沿著通道柱16傳送並儲存在整個電荷儲存結構40中,如此可對記憶單元20進行1位元的操作。此外,對於利用福勒-諾德漢穿隧(Fowler-Nordheim tunneling)的操作來說,可使電子或是電洞被捕捉在源極柱32a與汲極柱32b之間的電荷儲存結構40中。對於源極側注入(source side injection)、通道熱電子(channel-hot-electron)注入或帶對帶穿隧熱載子(band-to-band tunneling hot carrier)注入的操作來說,可使電子或電洞被局部地捕捉在鄰近兩個源極柱32a與汲極柱32b中的一者的電荷儲存結構40中,如此可對記憶單元20進行單位晶胞(SLC,1位元)或多位晶胞(MLC,大於或等於2位元)的操作。1E, the charge storage structure 40, the channel pillar 16, and the source pillar 32a and the drain pillar 32b are surrounded by the gate layer 38 and define the memory cell 20. The memory cell 20 can perform 1-bit operation or 2-bit operation by different operation methods. For example, when a voltage is applied to the source pillar 32a and the drain pillar 32b, since the source pillar 32a and the drain pillar 32b are connected to the channel pillar 16, electrons can be transmitted along the channel pillar 16 and stored in the entire charge storage structure 40, so that the memory cell 20 can be operated with 1 bit. In addition, for the operation using Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source pillar 32a and the drain pillar 32b. For the operation using source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons or holes can be locally trapped in the charge storage structure 40 of one of the two adjacent source pillars 32a and drain pillars 32b, so that the memory cell 20 can be operated in a single-bit cell (SLC, 1 bit) or a multi-bit cell (MLC, greater than or equal to 2 bits).

在進行操作時,將電壓施加至所選擇的字元線(閘極層)38,例如施加高於對應記憶單元20的相應起始電壓(V th)時,與所選擇的字元線38相交的通道柱16的通道區被導通,而允許電流從位元線BL n或BL n+1(示於圖1B)進入汲極柱32b,並經由導通的通道區流至源極柱32a(例如,在由箭頭60所指示的方向上),最後流到源極線SL n或SL n+1(示於圖1B)。 During operation, when a voltage is applied to the selected word line (gate layer) 38, for example, when a voltage higher than the corresponding starting voltage ( Vth ) of the corresponding memory cell 20 is applied, the channel region of the channel pillar 16 intersecting the selected word line 38 is turned on, allowing current to enter the drain pillar 32b from the bit line BLn or BLn +1 (shown in FIG. 1B), and flow through the turned-on channel region to the source pillar 32a (for example, in the direction indicated by the arrow 60), and finally flow to the source line SLn or SLn +1 (shown in FIG. 1B).

在一些實施例中,在堆疊結構52與介電基底50基底之間還設置有導體層,以做為蝕刻垂直通道孔的停止層,並且此導體層將接地以使得字元線無法控制的通道可以被正常關閉。然而,由於製程的因素,垂直通道孔的側壁通常具有傾斜的輪廓,使得垂直通道孔呈錐形。在形成源極柱(導體柱)32a與汲極柱(導體柱)32b的孔時,導體層側壁上的介電層很可能在進行蝕刻的過程或是在清洗的過程中被耗盡或被移除,使得導體層的側壁被裸露於孔之中,導致後續形成的源極柱(導體柱)32a與汲極柱(導體柱)32b與導體層發生不正常的橋接。In some embodiments, a conductive layer is further disposed between the stacked structure 52 and the dielectric substrate 50 to serve as a stop layer for etching the vertical channel hole, and the conductive layer is grounded so that the channel that cannot be controlled by the word line can be normally closed. However, due to process factors, the sidewall of the vertical channel hole usually has an inclined profile, making the vertical channel hole conical. When forming the holes of the source column (conductor column) 32a and the drain column (conductor column) 32b, the dielectric layer on the side wall of the conductive layer is likely to be consumed or removed during the etching process or the cleaning process, so that the side wall of the conductive layer is exposed in the hole, causing the subsequently formed source column (conductor column) 32a and the drain column (conductor column) 32b to have abnormal bridging with the conductive layer.

本發明實施例提出的記憶體元件藉由後續的製程將原本設置在堆疊結構下方的導體層移除,再重新形成絕緣層可以避免導體柱與堆疊結構下方的導體層發生不正常橋接的問題。The memory device provided in the embodiment of the present invention removes the conductive layer originally disposed under the stacking structure in a subsequent manufacturing process, and then re-forms the insulating layer to avoid the problem of abnormal bridging between the conductive pillar and the conductive layer under the stacking structure.

圖2A至圖2K是依照本發明實施例的一種記憶體元件的製造流程的上視圖。圖3A至圖3K是圖2A至圖2K的線x-x’的剖面圖。圖3I’至圖3K’是圖2I至圖2K的線y-y’的剖面圖。圖2A至圖2G是圖3A至圖3G的線I-I’的上視圖。圖2H至圖2K是圖3H至圖3K’的線II-II’的上視圖。Fig. 2A to Fig. 2K are top views of a manufacturing process of a memory element according to an embodiment of the present invention. Fig. 3A to Fig. 3K are cross-sectional views along line x-x' of Fig. 2A to Fig. 2K. Fig. 3I' to Fig. 3K' are cross-sectional views along line y-y' of Fig. 2I to Fig. 2K. Fig. 2A to Fig. 2G are top views along line I-I' of Fig. 3A to Fig. 3G. Fig. 2H to Fig. 2K are top views along line II-II' of Fig. 3H to Fig. 3K'.

參照圖2A與圖3A,提供介電基底100。介電基底100例如是具有形成於矽基板上的金屬內連線結構的介電層,例如氧化矽層。介電基底100中具有停止層92。停止層92例如是圖案化的多晶矽層。於介電基底100上形成導體層94。導體層94的材料例如是多晶矽。於導體層94上形成堆疊結構102。堆疊結構102又可稱為絕緣堆疊結構102。在本實施例中,堆疊結構102由依序交錯堆疊於介電基底100上的絕緣層104與中間層106所構成。在其他實施例中,中間層106與絕緣層104以相反順序交錯堆疊於介電基底100上。此外,在本實施例中,堆疊結構102的最上層為絕緣層104。最下層絕緣層104 1的厚度t1大於多個中間層106之間的絕緣層104 2的厚度t2。絕緣層104例如為氧化矽層。中間層106例如為氮化矽層。在本實施例中,堆疊結構102具有4層絕緣層104與3層中間層106,但本發明不限於此。在其他實施例中,可視實際需求來形成更多的絕緣層104與中間層106。之後,將堆疊結構102圖案化,以形成階梯結構(未示出)。進行微影與蝕刻製程,於堆疊結構102中形成多個開孔108(或稱為垂直通道孔VC)。然而,在圖2A與圖2B中僅示出單一個開孔108。開孔108的底面暴露出導體層94,而未暴露出介電基底100。 Referring to FIG. 2A and FIG. 3A , a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer having a metal interconnect structure formed on a silicon substrate, such as a silicon oxide layer. The dielectric substrate 100 has a stop layer 92. The stop layer 92 is, for example, a patterned polysilicon layer. A conductor layer 94 is formed on the dielectric substrate 100. The material of the conductor layer 94 is, for example, polysilicon. A stacking structure 102 is formed on the conductor layer 94. The stacking structure 102 can also be referred to as an insulating stacking structure 102. In this embodiment, the stacking structure 102 is composed of insulating layers 104 and intermediate layers 106 stacked in sequence and staggered on the dielectric substrate 100. In other embodiments, the intermediate layers 106 and the insulating layers 104 are alternately stacked on the dielectric substrate 100 in the opposite order. In addition, in this embodiment, the top layer of the stacked structure 102 is the insulating layer 104. The thickness t1 of the bottom insulating layer 104 1 is greater than the thickness t2 of the insulating layer 104 2 between the plurality of intermediate layers 106. The insulating layer 104 is, for example, a silicon oxide layer. The intermediate layer 106 is, for example, a silicon nitride layer. In this embodiment, the stacked structure 102 has four insulating layers 104 and three intermediate layers 106, but the present invention is not limited thereto. In other embodiments, more insulating layers 104 and intermediate layers 106 may be formed according to actual needs. Afterwards, the stacked structure 102 is patterned to form a step structure (not shown). A lithography and etching process is performed to form a plurality of openings 108 (or vertical channel holes VC) in the stacked structure 102. However, only a single opening 108 is shown in FIG. 2A and FIG. 2B. The bottom surface of the opening 108 exposes the conductive layer 94, but does not expose the dielectric substrate 100.

參照圖2B與圖3B,繼續進行蝕刻製程,以加深開孔108的深度,使得開孔108的底部延伸至介電基底100中。在本實施例中,以上視角度來看,開孔108具有圓形的形狀,但本發明不限於此。在其他實施例中,開孔108可具有其他形狀的形狀,例如多邊形(未示出)。2B and 3B, the etching process is continued to deepen the depth of the opening 108 so that the bottom of the opening 108 extends into the dielectric substrate 100. In the present embodiment, the opening 108 has a circular shape when viewed from above, but the present invention is not limited thereto. In other embodiments, the opening 108 may have other shapes, such as a polygon (not shown).

參照圖2C與圖3C,進行熱氧化製程,以使得開孔108所裸露的中間層106的側壁的表面被氧化而形成保護層110。保護層110的材料例如是氧化矽。2C and 3C , a thermal oxidation process is performed to oxidize the surface of the sidewall of the middle layer 106 exposed by the opening 108 to form a protective layer 110. The material of the protective layer 110 is, for example, silicon oxide.

參照圖2D與圖3D,在開孔108的側壁形成通道柱116。通道柱116的材料可為半導體材料,例如未摻雜多晶矽。通道柱116的形成方法例如是在堆疊結構102上以及開孔108之中形成通道材料。之後,進行回蝕製程,以局部移除通道材料,形成通道柱116。通道柱116的上視圖例如為環形,且在其延伸方向上(例如垂直介電基底100的方向上)可為連續的。也就是說,通道柱116在其延伸方向上為整體的,並未分成多個不相連的部分。在一些實施例中,通道柱116於上視角度來看可具有圓形,但本發明不限於此。在其他實施例中,通道柱116以上視角度來看也可具有其他形狀(例如多邊形)的形狀。2D and 3D , a channel column 116 is formed on the side wall of the opening 108. The material of the channel column 116 may be a semiconductor material, such as undoped polysilicon. The method of forming the channel column 116 is, for example, to form a channel material on the stacked structure 102 and in the opening 108. Thereafter, an etching back process is performed to partially remove the channel material to form the channel column 116. The top view of the channel column 116 is, for example, annular, and may be continuous in its extension direction (for example, in a direction perpendicular to the dielectric substrate 100). That is, the channel column 116 is integral in its extension direction and is not divided into a plurality of unconnected parts. In some embodiments, the channel column 116 may have a circular shape when viewed from a top view, but the present invention is not limited thereto. In other embodiments, the channel column 116 may also have other shapes (such as a polygon) when viewed from above.

參照圖2E與圖3E,在堆疊結構102上方以及開孔108中形成絕緣填充層124。絕緣填充層124的材料例如是氧化矽。在絕緣填充層124填充開孔108時,在尚未完全填滿開孔108的中心而留下孔洞之際,填入不同於絕緣填充層124的絕緣材料,例如是氮化矽,將開孔108完全封口。在經由乾蝕刻或濕蝕刻製程將絕緣材料回蝕至絕緣填充層124的表面裸露出來,留在開孔108正中心的絕緣材料形成絕緣柱128。Referring to FIG. 2E and FIG. 3E , an insulating filling layer 124 is formed above the stacked structure 102 and in the opening 108. The material of the insulating filling layer 124 is, for example, silicon oxide. When the insulating filling layer 124 fills the opening 108, before the center of the opening 108 is completely filled and a hole is left, an insulating material different from the insulating filling layer 124, such as silicon nitride, is filled to completely seal the opening 108. The insulating material is etched back to expose the surface of the insulating filling layer 124 through a dry etching or wet etching process, and the insulating material left in the center of the opening 108 forms an insulating column 128.

參照圖2F與圖3F,進行圖案化製程,以在絕緣填充層124中形成孔130a與130b。孔130a與130b從絕緣填充層124的頂面延伸至介電基底100。圖案化製程所定義的孔的圖案的形狀可以與絕緣柱128的形狀相切。圖案化製程所定義的孔的圖案的形狀也可超出絕緣柱128的形狀。由於絕緣柱128的蝕刻速率小於絕緣填充層124的蝕刻速率,因此,絕緣柱128幾乎不會遭受蝕刻的破壞而保留下來。在孔130a與130b中形成第一導體柱132a與第二導體柱132b。第一導體柱132a與第二導體柱132b可分別做為源極柱與汲極柱,且分別與通道柱116電性連接。第一導體柱132a與第二導體柱132b可以是在絕緣填充層124上以及孔130a與130b中形成導體層,然後再經由回蝕刻而形成。第一導體柱132a與第二導體柱132b例如是摻雜的多晶矽。2F and 3F, a patterning process is performed to form holes 130a and 130b in the insulating filling layer 124. The holes 130a and 130b extend from the top surface of the insulating filling layer 124 to the dielectric substrate 100. The shape of the hole pattern defined by the patterning process may be tangent to the shape of the insulating pillar 128. The shape of the hole pattern defined by the patterning process may also exceed the shape of the insulating pillar 128. Since the etching rate of the insulating pillar 128 is less than the etching rate of the insulating filling layer 124, the insulating pillar 128 is hardly damaged by etching and remains. A first conductive pillar 132a and a second conductive pillar 132b are formed in the holes 130a and 130b. The first conductive pillar 132a and the second conductive pillar 132b can be used as a source pillar and a drain pillar, respectively, and are electrically connected to the channel pillar 116, respectively. The first conductive pillar 132a and the second conductive pillar 132b can be formed by forming a conductive layer on the insulating filling layer 124 and in the holes 130a and 130b, and then etching back. The first conductive pillar 132a and the second conductive pillar 132b are, for example, doped polysilicon.

參照圖2G與圖3G,在絕緣填充層124、第一導體柱132a與第二導體柱132b以及絕緣柱128上形成介電層125。介電層125的材料包括氧化矽、氮化矽、氮氧化矽、或其組合。接著,進行圖案化製程,以形成多個分隔溝渠133。分隔溝渠133沿X方向延伸,使堆疊結構102以及導體層94分割成多個區塊。分隔溝渠133從介電層125向下穿過堆疊結構102,而且還延伸至導體層94。分隔溝渠133的底部可以裸露出介電基底100,或是裸露出部分的導體層94(未示出)。2G and 3G , a dielectric layer 125 is formed on the insulating filling layer 124, the first and second conductive pillars 132a and 132b, and the insulating pillar 128. The material of the dielectric layer 125 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Then, a patterning process is performed to form a plurality of separation trenches 133. The separation trenches 133 extend along the X direction to divide the stacking structure 102 and the conductive layer 94 into a plurality of blocks. The separation trenches 133 pass downward from the dielectric layer 125 through the stacking structure 102 and also extend to the conductive layer 94. The bottom of the separation trenches 133 may expose the dielectric substrate 100, or expose a portion of the conductive layer 94 (not shown).

參照圖2H與圖3H,進行蝕刻製程,例如濕式蝕刻製程,以將導體層94以及在導體層94側壁的保護層110移除,以形成水平開口OP1。水平開口OP1裸露出通道柱116的外側壁。2H and 3H , an etching process, such as a wet etching process, is performed to remove the conductive layer 94 and the protective layer 110 on the sidewall of the conductive layer 94 to form a horizontal opening OP1 . The horizontal opening OP1 exposes the outer sidewall of the channel pillar 116 .

參照圖2I、圖3I與圖3I’,進行蝕刻製程,例如濕式蝕刻製程,以將部分的通道柱116、部分的第一導體柱132a以及部分的第二導體柱132b移除,以形成水平開口OP2。水平開口OP2裸露出絕緣填充層124。在進行蝕刻製程時,先進行主蝕刻製程,之後,進行過度蝕刻製程,以移除更多的通道柱116、第一導體柱132a以及第二導體柱132b,以使得水平開口OP2具有凹槽R1與R2。凹槽R1向上延伸至最底層的絕緣層104的頂面與底面之間,裸露出剩餘的通道柱116、第一導體柱132a與第二導體柱132b的底面。第一導體柱132a與第二導體柱132b的底面位於最下層的絕緣層104 1的頂面與底面之間。凹槽R2向下延伸至介電基底100之中,裸露出剩餘的第一導體柱132a’與第二導體柱132b’。 Referring to FIG. 2I , FIG. 3I , and FIG. 3I ′, an etching process, such as a wet etching process, is performed to remove a portion of the channel column 116, a portion of the first conductive column 132a, and a portion of the second conductive column 132b to form a horizontal opening OP2. The horizontal opening OP2 exposes the insulating filling layer 124. When performing the etching process, a main etching process is performed first, and then an over-etching process is performed to remove more channel columns 116, the first conductive column 132a, and the second conductive column 132b, so that the horizontal opening OP2 has grooves R1 and R2. The groove R1 extends upward to between the top and bottom surfaces of the bottommost insulating layer 104, exposing the bottom surfaces of the remaining channel columns 116, the first conductive column 132a, and the second conductive column 132b. The bottom surfaces of the first conductive pillar 132a and the second conductive pillar 132b are located between the top surface and the bottom surface of the bottommost insulating layer 1041. The groove R2 extends downward into the dielectric substrate 100, exposing the remaining first conductive pillar 132a' and the second conductive pillar 132b'.

參照圖2J、圖3J與圖3J’,進行閘極取代製程。首先,進行蝕刻製程,例如濕式蝕刻製程,以將部分的多層中間層106移除,以形成多個水平開口134。多個水平開口134裸露出保護層110。在進行蝕刻的過程中,由於保護層110與中間層106的材料不同,因此,保護層110可以做為蝕刻停止層,以保護通道柱116。Referring to FIG. 2J , FIG. 3J and FIG. 3J ′, a gate replacement process is performed. First, an etching process, such as a wet etching process, is performed to remove a portion of the multi-layered middle layer 106 to form a plurality of horizontal openings 134. The plurality of horizontal openings 134 expose the protective layer 110. During the etching process, since the protective layer 110 and the middle layer 106 are made of different materials, the protective layer 110 can be used as an etching stop layer to protect the channel pillars 116.

參照圖2K、圖3K與圖3K’,於多個水平開口134中形成穿隧層114、電荷儲存層112、阻擋層136、阻障層137以及導體層138。穿隧層114以及電荷儲存層112還形成在水平開口OP2之中。穿隧層114、電荷儲存層112、阻擋層136、阻障層137以及導體層138的形成方法例如是於多個分隔溝渠133、多個水平開口134以及OP2中形成穿隧材料、電荷儲存材料、阻擋材料、阻障材料以及導體材料。之後,進行回蝕刻製程,移除在多個分隔溝渠133以及水平開口OP2之中的導體材料、阻障材料以及阻擋材料,以在水平開口134之中形成導體層138、阻擋層136以及阻障層137。2K, 3K and 3K', a tunneling layer 114, a charge storage layer 112, a blocking layer 136, a barrier layer 137 and a conductor layer 138 are formed in a plurality of horizontal openings 134. The tunneling layer 114 and the charge storage layer 112 are also formed in the horizontal opening OP2. The method of forming the tunneling layer 114, the charge storage layer 112, the blocking layer 136, the barrier layer 137 and the conductor layer 138 is, for example, to form a tunneling material, a charge storage material, a blocking material, a barrier material and a conductor material in a plurality of separation trenches 133, a plurality of horizontal openings 134 and OP2. Thereafter, an etching back process is performed to remove the conductive material, barrier material and blocking material in the plurality of separation trenches 133 and the horizontal opening OP2 to form a conductive layer 138, a blocking layer 136 and a barrier layer 137 in the horizontal opening 134.

接著,進行另一個蝕刻製程,以移除在多個分隔溝渠133之中的電荷儲存材料以及穿隧材料,以在水平開口134以及OP2之中形成電荷儲存層112以及穿隧層114。至此,形成閘極堆疊結構150。閘極堆疊結構150,設置於介電基底100上,且包括多層閘極層138與多層絕緣層104彼此交互堆疊。Next, another etching process is performed to remove the charge storage material and the tunneling material in the plurality of separation trenches 133, so as to form the charge storage layer 112 and the tunneling layer 114 in the horizontal opening 134 and OP2. Thus, the gate stack structure 150 is formed. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes a plurality of gate layers 138 and a plurality of insulating layers 104 alternately stacked with each other.

其後,在多個分隔溝渠133之中形成分隔牆SLIT。分隔牆SLIT的形成方法包括在閘極堆疊結構150上以及分隔溝渠133中填入絕緣材料,然後經由回蝕刻製程或是平坦化製程移除閘極堆疊結構150上多餘的絕緣材料。絕緣材料例如氧化矽是或是氮化矽。在其他實施例中,分隔牆SLIT可以包括導體層與包覆蓋導體層外側壁的絕緣襯層。在另一些實施例中,分隔牆SLIT也可以包括絕緣層且絕緣層中具有氣隙。Thereafter, a separation wall SLIT is formed in the plurality of separation trenches 133. The method for forming the separation wall SLIT includes filling an insulating material on the gate stack structure 150 and in the separation trench 133, and then removing excess insulating material on the gate stack structure 150 by an etching back process or a planarization process. The insulating material is, for example, silicon oxide or silicon nitride. In other embodiments, the separation wall SLIT may include a conductive layer and an insulating liner covering the outer side wall of the conductive layer. In other embodiments, the separation wall SLIT may also include an insulating layer and an air gap in the insulating layer.

在本發明的實施例中,分隔牆SLIT包括主體部P1與延伸部P2。主體部P1,在第三方向Z延伸,穿過堆疊結構150,分隔相鄰區塊的導體層138。延伸部P2,與主體部P1連接,位於堆疊結構150與介電基底100之間。延伸部P2被穿隧層114以及電荷儲存層112包覆。延伸部P2與第一導體柱132a以及第二導體柱132b之間隔著穿隧層114以及電荷儲存層112。延伸部P2與剩餘的第一導體柱132a1以及剩餘的第二導體柱132b1之間隔著穿隧層114以及電荷儲存層112。In an embodiment of the present invention, the partition wall SLIT includes a main body P1 and an extension P2. The main body P1 extends in the third direction Z, passes through the stacking structure 150, and separates the conductive layer 138 of adjacent blocks. The extension P2 is connected to the main body P1 and is located between the stacking structure 150 and the dielectric substrate 100. The extension P2 is covered by the tunneling layer 114 and the charge storage layer 112. The tunneling layer 114 and the charge storage layer 112 are between the extension P2 and the first conductive pillar 132a and the second conductive pillar 132b. The tunneling layer 114 and the charge storage layer 112 are located between the extension portion P2 and the remaining first conductive pillar 132a1 and the remaining second conductive pillar 132b1.

在第一方向X上的延伸部P2的高度H1大於在第二方向Y上的延伸部P2的高度H2。延伸部P2包括第一突部Q1、第二突部Q2以及中間部Q3。中間部Q3在第一突部Q1與第二突部Q2之間,且與其二者連接。第一突部Q1和第二突部Q2與第一導體柱132a與第二導體柱132b以及剩餘的第一導體柱132a1以及剩餘的第二導體柱132b1嵌合。第一突部Q1與第二突部Q2朝相反方向延伸。第一突部Q1,向通道柱116延伸。第一突部Q1的頂面位於最下層的絕緣層104 1的頂面與底面之間。第二突部Q2,向介電基底100延伸。 The height H1 of the extension portion P2 in the first direction X is greater than the height H2 of the extension portion P2 in the second direction Y. The extension portion P2 includes a first protrusion Q1, a second protrusion Q2, and a middle portion Q3. The middle portion Q3 is between the first protrusion Q1 and the second protrusion Q2, and is connected to both of them. The first protrusion Q1 and the second protrusion Q2 are engaged with the first conductive pillar 132a and the second conductive pillar 132b and the remaining first conductive pillar 132a1 and the remaining second conductive pillar 132b1. The first protrusion Q1 and the second protrusion Q2 extend in opposite directions. The first protrusion Q1 extends toward the channel pillar 116. The top surface of the first protrusion Q1 is located between the top surface and the bottom surface of the lowest insulating layer 1041. The second protrusion Q2 extends toward the dielectric substrate 100.

在第一平面XZ上的延伸部P2的剖面例如是呈橫置的T型,如圖3K所示。在第二平面YZ上的延伸部P2的剖面例如是呈矩形,如圖3K’所示。延伸部P2的上視圖呈半圓形或半橢圓形,如圖2K所示。在第一方向X上延伸部P2與絕緣柱128之間的第一距離d1小於在第二方向Y上的延伸部P2與絕緣柱128之間的第二距離d2。最下層絕緣層104 1的厚度t1大於多個導體層138之間的絕緣層104 2的厚度t2。 The cross section of the extension portion P2 on the first plane XZ is, for example, a horizontal T-shape, as shown in FIG3K. The cross section of the extension portion P2 on the second plane YZ is, for example, a rectangle, as shown in FIG3K'. The top view of the extension portion P2 is semicircular or semi-elliptical, as shown in FIG2K. The first distance d1 between the extension portion P2 and the insulating column 128 in the first direction X is smaller than the second distance d2 between the extension portion P2 and the insulating column 128 in the second direction Y. The thickness t1 of the bottommost insulating layer 104 1 is greater than the thickness t2 of the insulating layer 104 2 between the plurality of conductive layers 138.

在以上的實施例中,堆疊結構102下方具有單一的導體層94。然而,本發明不以此為限,在其他的實施例中,堆疊結構102下方可以設置多層的導體層94a、94b,並以絕緣層104分隔開,其製程如圖4A至圖4D所示。In the above embodiment, a single conductive layer 94 is provided under the stacked structure 102. However, the present invention is not limited thereto, and in other embodiments, multiple conductive layers 94a, 94b may be provided under the stacked structure 102 and separated by an insulating layer 104, and the manufacturing process is shown in FIGS. 4A to 4D.

圖4A至圖4D是依照本發明另一實施例的一種記憶體元件的製造流程的剖視圖。4A to 4D are cross-sectional views of a manufacturing process of a memory device according to another embodiment of the present invention.

參照圖4A,在介電基底100上形成導體層94a、絕緣層93以及導體層94b。導體層94a、94b例如是半導體材料。絕緣層93的材料例如氧化矽。接著,在導體層94b上形成堆疊結構102。4A, a conductive layer 94a, an insulating layer 93, and a conductive layer 94b are formed on a dielectric substrate 100. The conductive layers 94a and 94b are, for example, semiconductor materials. The material of the insulating layer 93 is, for example, silicon oxide. Then, a stacking structure 102 is formed on the conductive layer 94b.

參照圖4B,依照以上所述的方法形成絕緣填充層124、絕緣柱128、第一導體柱132a、第二導體柱132b以及介電層125。4B, an insulating filling layer 124, an insulating column 128, a first conductive column 132a, a second conductive column 132b, and a dielectric layer 125 are formed according to the method described above.

參照圖4C,進行圖案化製程,以形成多個分隔溝渠133。接著,進行蝕刻製程,以移除保護層110、導體層94a與94b、部分的通道柱116、部分的第一導體柱132a以及部分的第二導體柱132b,以形成水平開口OP3以及OP4,並在水平開口OP3以及OP4之間留下剩餘的第一導體柱132a2以及剩餘的第二導體柱132b2,在水平開口OP4下方留下剩餘的第一導體柱132a1以及剩餘的第二導體柱132b1。4C , a patterning process is performed to form a plurality of separation trenches 133. Then, an etching process is performed to remove the protective layer 110, the conductive layers 94a and 94b, a portion of the channel pillar 116, a portion of the first conductive pillar 132a, and a portion of the second conductive pillar 132b to form horizontal openings OP3 and OP4, and to leave the remaining first conductive pillar 132a2 and the remaining second conductive pillar 132b2 between the horizontal openings OP3 and OP4, and to leave the remaining first conductive pillar 132a1 and the remaining second conductive pillar 132b1 below the horizontal opening OP4.

參照圖4D,依照上述方法進行閘極取代製程,以將多層中間層106取代為穿隧層114、電荷儲存層112、阻擋層136、阻障層137以及導體層138。同樣地,穿隧層114以及電荷儲存層112還形成在水平開口OP3與OP4之中。之後,在多個分隔溝渠133之中填入在分隔溝渠133中形成分隔牆SLIT。4D, a gate replacement process is performed according to the above method to replace the multi-layer intermediate layer 106 with a tunneling layer 114, a charge storage layer 112, a blocking layer 136, a barrier layer 137 and a conductive layer 138. Similarly, the tunneling layer 114 and the charge storage layer 112 are also formed in the horizontal openings OP3 and OP4. Afterwards, a plurality of separation trenches 133 are filled to form a separation wall SLIT in the separation trenches 133.

在本實施例中,分隔牆SLIT包括主體部P1與延伸部P2。主體部P1,在第三方向Z延伸,穿過堆疊結構150,分隔相鄰區塊的導體層138。延伸部P2包括第一部G2與第二部G3。第一部G2與第二部G3位於堆疊結構150與介電基底100之間,與主體部P1連接。第一部G2位於第二部G3上方。第一部G2與第二部G3藉由絕緣層93、剩餘的第一導體柱132a2以及剩餘的第二導體柱132b2彼此分離。In this embodiment, the partition wall SLIT includes a main portion P1 and an extension portion P2. The main portion P1 extends in the third direction Z, passes through the stacking structure 150, and separates the conductive layer 138 of adjacent blocks. The extension portion P2 includes a first portion G2 and a second portion G3. The first portion G2 and the second portion G3 are located between the stacking structure 150 and the dielectric substrate 100, and are connected to the main portion P1. The first portion G2 is located above the second portion G3. The first portion G2 and the second portion G3 are separated from each other by the insulating layer 93, the remaining first conductive pillar 132a2, and the remaining second conductive pillar 132b2.

第一部G2與第二部G3的剖面例如是呈橫置的T型。第一部G2與第二部G3可以各自別包括第一突部S1、第二突部S2以及中間部S3。中間部S3在第一突部S1與第二突部S2之間,且與其二者連接。第一突部S1,向通道柱116延伸。第一突部S1的頂面位於最下層的絕緣層104 1的頂面與底面之間。第二突部S2,向介電基底100延伸。 The cross-section of the first part G2 and the second part G3 is, for example, a horizontal T-shape. The first part G2 and the second part G3 may each include a first protrusion S1, a second protrusion S2, and a middle part S3. The middle part S3 is between the first protrusion S1 and the second protrusion S2 and is connected to both of them. The first protrusion S1 extends toward the channel column 116. The top surface of the first protrusion S1 is located between the top surface and the bottom surface of the lowest insulating layer 1041. The second protrusion S2 extends toward the dielectric substrate 100.

圖5A至圖5B是依照本發明又一實施例的一種記憶體元件的製造流程的剖視圖。5A and 5B are cross-sectional views of a manufacturing process of a memory device according to another embodiment of the present invention.

參照圖5A,在以上圖4C中,若未剩餘第一導體柱132a2以及第二導體柱132b2,絕緣層93被留在介電基底100的情況,將形成水平開口OP5,如圖5A所示。5A, in FIG. 4C above, if the first conductive pillar 132a2 and the second conductive pillar 132b2 are not left, and the insulating layer 93 is left on the dielectric substrate 100, a horizontal opening OP5 will be formed, as shown in FIG. 5A.

參照圖5B,依照上述方法,直至形成分隔牆SLIT。分隔牆SLIT包括主體部P1與延伸部P2。主體部P1,在第三方向Z延伸,穿過堆疊結構150。延伸部P2,與主體部P1連接,位於堆疊結構150與介電基底100之間。延伸部P2的剖面例如是呈橫置的T型。延伸部P2包括第一突部M1、第二突部M2以及中間部M3。中間部M3在第一突部M1與第二突部M2之間,且與其二者連接。第一突部M1,向通道柱116延伸。第一突部M1的頂面位於最下層的絕緣層104 1的頂面與底面之間。第二突部M2,向介電基底100延伸。 Referring to FIG. 5B , the above method is followed until a separation wall SLIT is formed. The separation wall SLIT includes a main portion P1 and an extension portion P2. The main portion P1 extends in the third direction Z and passes through the stacking structure 150. The extension portion P2 is connected to the main portion P1 and is located between the stacking structure 150 and the dielectric substrate 100. The cross-section of the extension portion P2 is, for example, a horizontal T-shape. The extension portion P2 includes a first protrusion M1, a second protrusion M2, and a middle portion M3. The middle portion M3 is between the first protrusion M1 and the second protrusion M2, and is connected to both of them. The first protrusion M1 extends toward the channel column 116. The top surface of the first protrusion M1 is located between the top surface and the bottom surface of the lowest insulating layer 104 1. The second protrusion M2 extends toward the dielectric substrate 100.

綜上所述,本發明實施例之記憶體元件將原本設置在堆疊結構下方的導體層移除,再重新形成絕緣層可以避免導體柱與堆疊閘極下方的導體層發生不正常橋接的問題。In summary, the memory device of the embodiment of the present invention removes the conductive layer originally disposed under the stacked structure and then re-forms the insulating layer to avoid the problem of abnormal bridging between the conductive pillar and the conductive layer under the stacked gate.

10、A (i)、A (i+1):記憶體陣列 12、112:電荷儲存層 14、114:穿隧層 16、116:通道柱 20:記憶單元 24、124:絕緣填充層 28、128:絕緣柱 32a:第一導體柱/源極柱 32b:第二導體柱/汲極柱 36、136:阻擋層 38:閘極層 38:字元線 40:電荷儲存結構 50、100:介電基底 50s:表面 54、93、104、104 1、104 2:絕緣層 60:箭頭 92:停止層 94、94a、94b、138:導體層 52、102、150:堆疊結構 106:中間層 108:開孔 110:保護層 125:介電層 130a、130b:孔 132a、132a1、132a2、132a’:第一導體柱 132b、132b1、132b2、132b’:第二導體柱 133:分隔溝渠 134、OP1、OP2、OP3、OP4:水平開口 137:阻障層 138:多層閘極層 BLOCK (i)、BLOCK (i+1):區塊 BL n、BL n+1:位元線 SP ( i ) n、SP (i) n+1、SP ( i+1 ) n、SP (i+1) n+1:源極柱 DP (i) n、DP i ) n+1、DP i+1) n、DP (i+1) n+1:源極柱 G2:第一部 G3:第二部 H1、H2:高度 M1、Q1、S1:第一突部 M2、Q2、S2:第二突部 M3、Q3、S3:中間部 P1:主體部 P2:延伸部 R1、R2:凹槽 SLIT:分隔牆 VC:垂直通道孔 X:第一方向 Y:第二方向 Z:第三方向 d1:第一距離 d2:第二距離 t1、t2:厚度 I-I’、II-II’、x-x’、y-y’:線 10, A (i) , A (i+1) : memory array 12, 112: charge storage layer 14, 114: tunneling layer 16, 116: channel pillar 20: memory cell 24, 124: insulating filling layer 28, 128: insulating pillar 32a: first conductor pillar/source pillar 32b: second conductor pillar/drain pillar 36, 136: blocking layer 38: gate layer 38: word line 40: charge storage structure 50, 100: dielectric substrate 50s: surface 54, 93, 104, 104 1 , 104 2 : Insulation layer 60: Arrow 92: Stop layer 94, 94a, 94b, 138: Conductor layer 52, 102, 150: Stacked structure 106: Intermediate layer 108: Opening 110: Protective layer 125: Dielectric layer 130a, 130b: Holes 132a, 132a1, 132a2, 132a': First conductor pillars 132b, 132b1, 132b2, 132b': Second conductor pillar 133: Separation trenches 134, OP1, OP2, OP3, OP4: Horizontal opening 137: Barrier layer 138: Multi-layer gate layer BLOCK (i) , BLOCK (i+1) : Blocks BLn , BLn +1 : bit lines SP ( i ) n , SP ( i ) n+1 , SP ( i+1 ) n , SP ( i+1) n+1 : source pillars DP ( i ) n , DP i ) n+1 , DP i+1) n , DP ( i+1) n+1 : source pillars G2 : first part G3 : second part H1 , H2 : heights M1 , Q1 , S1 : first protrusions M2 , Q2 , S2 : second protrusions M3 , Q3 , S3 : middle part P1 : main part P2 : extensions R1 , R2 : grooves SLIT : partition wall VC : vertical channel hole X : first direction Y : second direction Z : third direction d1 : first distance d2 : second distance t1 , t2 : thicknesses I-I' , II-II' , x-x' , y-y' : line

圖1A示出根據一些實施例的3D AND快閃記憶體陣列的電路圖。 圖1B示出圖1A中部分的記憶體陣列的局部三維視圖。 圖1C與圖1D示出圖1B的切線I-I’的剖面圖。 圖1E示出圖1B、圖1C、圖1D的切線II-II’的上視圖。 圖2A至圖2K是依照本發明實施例的一種記憶體元件的製造流程的上視圖。 圖3A至圖3K’是圖2A至圖2K的線x-x’以及y-y’的剖面圖。 圖4A至圖4D是依照本發明另一實施例的一種記憶體元件的製造流程的剖視圖。 圖5A至圖5B是依照本發明又一實施例的一種記憶體元件的製造流程的剖視圖。 FIG. 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A. FIG. 1C and FIG. 1D show a cross-sectional view of the cut line I-I’ of FIG. 1B. FIG. 1E shows a top view of the cut line II-II’ of FIG. 1B, FIG. 1C, and FIG. 1D. FIG. 2A to FIG. 2K are top views of a manufacturing process of a memory element according to an embodiment of the present invention. FIG. 3A to FIG. 3K’ are cross-sectional views of lines x-x’ and y-y’ of FIG. 2A to FIG. 2K. FIG. 4A to FIG. 4D are cross-sectional views of a manufacturing process of a memory element according to another embodiment of the present invention. Figures 5A to 5B are cross-sectional views of a manufacturing process of a memory element according to another embodiment of the present invention.

133:分隔溝渠 133: Separation channel

125:介電層 125: Dielectric layer

124:絕緣填充層 124: Insulation filling layer

104、1041、1042:絕緣層 104, 104 1 , 104 2 : Insulation layer

OP2:水平開口 OP2: Horizontal opening

R1、R2:凹槽 R1, R2: Groove

92:停止層 92: Stop layer

II-II’、x-x’:線 II-II’, x-x’: line

132a、132a’:第一導體柱 132a, 132a’: first conductor column

132b、132b’:第二導體柱 132b, 132b’: second conductor column

128:絕緣柱 128: Insulation Pillar

116:通道柱 116: Channel column

110:保護層 110: Protective layer

134:水平開口 134: Horizontal opening

100:介電基底 100: Dielectric substrate

Claims (12)

一種記憶體元件,包括: 堆疊結構,位於介電基底上,其中所述堆疊結構包括彼此交替堆疊的多個導體層與多個絕緣層; 通道柱,延伸穿過所述堆疊結構; 多個導體柱,位於所述通道柱內,且與所述通道柱電性連接; 電荷儲存結構,位於所述多個導體層與所述通道柱之間; 分隔牆,位於所述堆疊結構中,其中所述分隔牆包括: 主體部,延伸穿過所述堆疊結構;以及 延伸部,與所述主體部連接,位於所述堆疊結構與所述介電基底之間。 A memory element comprises: A stacking structure located on a dielectric substrate, wherein the stacking structure comprises a plurality of conductive layers and a plurality of insulating layers alternately stacked with each other; A channel column extending through the stacking structure; A plurality of conductive columns located in the channel column and electrically connected to the channel column; A charge storage structure located between the plurality of conductive layers and the channel column; A partition wall located in the stacking structure, wherein the partition wall comprises: A main body extending through the stacking structure; and An extension portion connected to the main body and located between the stacking structure and the dielectric substrate. 如請求項1所述的記憶體元件,其中所述電荷儲存結構還包覆所述延伸部。A memory device as described in claim 1, wherein the charge storage structure also covers the extension portion. 如請求項1所述的記憶體元件,其中所述延伸部還延伸至所述通道柱以及所述多個導體柱下方。A memory element as described in claim 1, wherein the extension portion also extends below the channel column and the multiple conductive columns. 如請求項1所述的記憶體元件,其中在第一方向上的所述延伸部的長度大於在第二方向上的所述延伸部的長度。A memory element as described in claim 1, wherein the length of the extension portion in the first direction is greater than the length of the extension portion in the second direction. 如請求項1所述的記憶體元件,其中所述延伸部包括第一突部,向所述通道柱延伸。A memory device as described in claim 1, wherein the extension portion includes a first protrusion extending toward the channel column. 如請求項1所述的記憶體元件,其中所述延伸部包括第二突部,向所述介電基底延伸。A memory element as described in claim 1, wherein the extension portion includes a second protrusion extending toward the dielectric substrate. 如請求項1所述的記憶體元件,其中在第一平面上的所述延伸部的剖面呈橫置的T型,在第二平面上的所述延伸部的剖面呈矩形。A memory element as described in claim 1, wherein the cross-section of the extension portion on the first plane is a horizontal T-shape, and the cross-section of the extension portion on the second plane is a rectangle. 如請求項1所述的記憶體元件,其中所述多個絕緣層的最下層絕緣層的厚度大於所述多個導體層之間的絕緣層的厚度。A memory device as described in claim 1, wherein the thickness of the lowest insulating layer of the plurality of insulating layers is greater than the thickness of the insulating layers between the plurality of conductive layers. 如請求項1所述的記憶體元件,其中所述延伸部包括第一部與第二部,所述第一部位於所述第二部上方且彼此分離。A memory element as described in claim 1, wherein the extension portion includes a first portion and a second portion, the first portion is located above the second portion and separated from each other. 一種記憶體元件的製造方法,包括: 形成第一導體層於介電基底上; 形成堆疊結構於所述第一導體層上,其中所述堆疊結構包括彼此交替堆疊的多個中間層與多個絕緣層; 形成通道柱延伸穿過所述堆疊結構與所述第一導體層; 於所述通道柱內形成與所述通道柱電性連接的多個導體柱; 形成分隔溝渠,延伸穿過所述堆疊結構與所述第一導體層; 移除部分所述第一導體層、部分所述通道柱以及部分所述多個導體柱,以形成第一水平開口; 局部地移除所述多個中間層,以形成多個第二水平開口; 於所述第一水平開口以及所述多個第二水平開口中形成電荷儲存層; 於所述多個第二水平開口中形成多個第二導體層;以及 於所述分隔溝渠中形成分隔牆的主體部,並在所述第一水平開口之中形成所述分隔牆的延伸部。 A method for manufacturing a memory element, comprising: forming a first conductive layer on a dielectric substrate; forming a stacking structure on the first conductive layer, wherein the stacking structure comprises a plurality of intermediate layers and a plurality of insulating layers stacked alternately with each other; forming a channel column extending through the stacking structure and the first conductive layer; forming a plurality of conductive columns electrically connected to the channel column in the channel column; forming a separation trench extending through the stacking structure and the first conductive layer; removing a portion of the first conductive layer, a portion of the channel column and a portion of the plurality of conductive columns to form a first horizontal opening; partially removing the plurality of intermediate layers to form a plurality of second horizontal openings; forming a charge storage layer in the first horizontal opening and the plurality of second horizontal openings; Forming a plurality of second conductive layers in the plurality of second horizontal openings; and Forming a main body of a partition wall in the partition trench, and forming an extension of the partition wall in the first horizontal opening. 如請求項10所述的記憶體元件的製造方法,更包括形成絕緣柱,於所述通道柱中,分隔所述多個導體柱,其中在第一方向上所述延伸部與所述絕緣柱之間的第一距離小於在第二方向上的所述延伸部與所述絕緣柱之間的第二距離。The method for manufacturing a memory element as described in claim 10 further includes forming an insulating column in the channel column to separate the multiple conductive columns, wherein a first distance between the extension portion and the insulating column in a first direction is smaller than a second distance between the extension portion and the insulating column in a second direction. 如請求項10所述的記憶體元件的製造方法,其中在第一平面上的所述延伸部的剖面呈橫置的T型,在第二平面上的所述延伸部的剖面呈矩形。A method for manufacturing a memory element as described in claim 10, wherein the cross-section of the extension portion on the first plane is a horizontal T-shape, and the cross-section of the extension portion on the second plane is a rectangle.
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