TW202439937A - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes a stacked structure, a channel pillar, a plurality of conductive pillars, and a slit. The stacked structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The channel pillar extends through the stacked structure. The plurality of conductive pillars are located in the channel pillar and electrically connected with the channel pillar. The charge storage structure is located between the plurality of conductive layers and the channel pillar. The slit is located in the stacked structure. The slit includes a body part and an extension part. The body part extends through the stacked structure. The extension part is connected to the body part and located between the stacked structure and the dielectric substrate. Th memory may be applied in 3D AND flash memory.

Description

Memory device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory device and a manufacturing method thereof.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure. Therefore, they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory.

The present invention provides a memory element and a manufacturing method thereof, which can avoid the problem of abnormal bridging between a conductor column and a conductor layer below a stacked gate.

A memory element of an embodiment of the present invention includes a stacking structure, a channel column, a plurality of conductive columns, and a partition wall. The stacking structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers alternately stacked with each other. The channel column extends through the stacking structure. The plurality of conductive columns are located in the channel column and are electrically connected to the channel column. The charge storage structure is located between the plurality of conductive layers and the channel column. The partition wall is located in the stacking structure. The partition wall includes: a main body and an extension portion. The main body extends through the stacking structure. The extension portion is connected to the main body and is located between the stacking structure and the dielectric substrate.

A method for manufacturing a memory element according to an embodiment of the present invention comprises the following steps. A first conductive layer is formed on a dielectric substrate. A stacking structure is formed on the conductive layer. The stacking structure comprises a plurality of intermediate layers and a plurality of insulating layers alternately stacked with each other. A channel column is formed to extend through the stacking structure and the first conductive layer. A plurality of conductive columns electrically connected to the channel column are formed in the channel column. A separation trench is formed to extend through the stacking structure and the first conductive layer. A portion of the first conductive layer, a portion of the channel column, and a portion of the plurality of conductive columns are removed to form a first horizontal opening. The plurality of intermediate layers are partially removed to form a plurality of second horizontal openings. A charge storage layer is formed in the first horizontal opening and the plurality of second horizontal openings. A plurality of second conductive layers are formed in the plurality of second horizontal openings. An extension portion of the partition wall is formed in the main body of the partition trench and in the first horizontal opening.

Based on the above, the memory element of the embodiment of the present invention removes the conductive layer originally disposed under the stacked structure and then re-forms the insulating layer to avoid the problem of abnormal bridging between the conductive pillar and the conductive layer under the stacked gate.

FIG1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG1B shows a partial three-dimensional view of a portion of the memory array in FIG1A. FIG1C and FIG1D show cross-sectional views of the cut line I-I' of FIG1B. FIG1E shows a top view of the cut line II-II' of FIG1B, FIG1C, and FIG1D.

FIG1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ of a vertical AND memory array 10 arranged in rows and columns. Block BLOCK ⁽ⁱ⁾ includes a memory array A ⁽ⁱ⁾ . A column (e.g., the m+1th column) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 in each column (e.g., the m+1th column) of the memory array A ⁽ⁱ⁾ correspond to a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ) and are coupled to different source poles (e.g., SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cells 20 are logically arranged in a row along the common word line (e.g., WL ⁽ⁱ⁾ _m+1 ).

A row (e.g., the nth row) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells 20 of each row (e.g., the nth row) of the memory array A ⁽ⁱ⁾ correspond to different word lines (e.g., WL ⁽ⁱ⁾ _m+1 and WL ⁽ⁱ⁾ _m ) and are coupled to a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁾ are logically arranged in a row along the common source column (e.g., SP ⁽ⁱ⁾ _n ) and the common drain column (e.g., DP ⁽ⁱ⁾ _n ). In the physical layout, depending on the manufacturing method applied, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

In FIG. 1A , in block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of the memory array A ⁽ⁱ⁾ share a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells 20 in the n+1th row share a common source column (e.g., SP ⁽ⁱ⁾ _n+1 ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n+1 ).

A common source column (e.g., SP ⁽ⁱ⁾ _n ) is coupled to a common source line (e.g., SL _n ); a common drain column (e.g., DP ⁽ⁱ⁾ _n ) is coupled to a common bit line (e.g., BL _n ). A common source column (e.g., SP ⁽ⁱ⁾ _n+1 ) is coupled to a common source line (e.g., SL _n+1 ); a common drain column (e.g., DP ⁽ⁱ⁾ _n+1 ) is coupled to a common bit line (e.g., BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes a memory array A ⁽ⁱ⁺¹⁾ that is similar to the memory array A ⁽ⁱ⁾ in block BLOCK ⁽ⁱ⁾ . A row (e.g., the m+1th row) of the memory array A ⁽ⁱ⁺¹⁾ is a set of AND memory cells 20 having a common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ). Each row (e.g., the m+1th row) of the memory array A ⁽ⁱ⁺¹⁾ corresponds to the common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ) and is coupled to different source poles (e.g., SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (e.g., the nth row) of the memory array A ⁽ⁱ⁺¹⁾ is a set of AND memory cells 20 having a common source pole (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁺¹⁾ _n ). The AND memory cells 20 of each row (e.g., the nth row) of the memory array A ⁽ⁱ⁺¹⁾ correspond to different word lines (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 and WL ⁽ⁱ⁺¹⁾ _m ) and are coupled to a common source pole (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁺¹⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁺¹⁾ are logically arranged in a row along a common source pole (eg, SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (eg, DP ⁽ⁱ⁺¹⁾ _n ).

Block BLOCK ⁽ⁱ⁺¹⁾ and block BLOCK ⁽ⁱ⁾ share a source line (e.g., SL _n and SL _n+1 ) and a bit line (e.g., BL _n and BL _n+1 ). Therefore, source line SL _n and bit line BL _n are coupled to the n-th row AND memory cell 20 in AND memory array A ⁽ⁱ⁾ of block BLOCK ⁽ⁱ⁾ , and are coupled to the n-th row AND memory cell 20 in AND memory array A ⁽ⁱ⁺¹⁾ of block BLOCK (i ⁺¹⁾ . Similarly, source line _SLn+1 and bit line BLn ₊₁ are coupled to the n+1th row AND memory cell 20 in AND memory array A ⁽ⁱ⁾ of block BLOCK ⁽ⁱ⁾ , and are coupled to the n+1th row AND memory cell 20 in AND memory array A ⁽ⁱ⁺¹⁾ in block BLOCK ⁽ⁱ⁺¹⁾ .

1B to 1D , the memory array 10 may be disposed on the interconnect structure of a semiconductor die, for example, disposed on one or more active devices (such as transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate (or dielectric layer) 50 is, for example, a dielectric layer formed on a metal interconnect structure on a silicon substrate, such as a silicon oxide layer. The memory array 10 may include a stacked structure 52, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a and a plurality of second conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.

1B , a stacked structure 52 is formed on a dielectric substrate 50. The stacked structure 52 includes a plurality of gate layers (also referred to as word lines or conductor layers) 38 vertically stacked on a surface 50s of the dielectric substrate 50 and a plurality of insulating layers 54. In a third direction Z, these gate layers 38 are electrically isolated by the insulating layers 54 disposed therebetween. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layer 38 of the step region (not shown) may have a step structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contacts (not shown) for connecting the gate layers 38 may be landed at the ends of the gate layers 38, thereby connecting each gate layer 38 to each wire.

1B to 1D , the memory array 10 further includes a plurality of channel pillars 16, an insulating pillar 28, a plurality of first conductive pillars 32a, and a plurality of second conductive pillars 32b, which are formed in a vertical channel hole (not shown) extending through the stacked structure 52. The channel pillars 16 extend continuously through the stacked structure 52. In some embodiments, the channel pillars 16 may have an annular profile when viewed from above. The material of the channel pillars 16 may be a semiconductor, such as undoped polysilicon. In this example, the first conductive pillars 32a serve as source pillars; and the second conductive pillars 32b serve as drain pillars. The first conductive pillar 32a, the second conductive pillar 32b and the insulating pillar 28 each extend in a direction (i.e., a third direction Z) perpendicular to the surface (i.e., the XY plane) of the gate layer 38. The first conductive pillar 32a and the second conductive pillar 32b are separated by the insulating pillar 28 and surrounded by the insulating filling layer 24. The first conductive pillar 32a and the second conductive pillar 32b are electrically connected to the channel pillar 16. The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating pillar 28 is, for example, silicon nitride or silicon oxide, and the insulating filling layer 24 is, for example, silicon oxide.

1C and 1D , the charge storage structure 40 is disposed between the channel pillar 16 and a plurality of gate layers (or conductor layers) 38. The charge storage structure 40 may include a tunneling layer (or a gap-engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14 and the blocking layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can capture charges. In some embodiments, as shown in FIG1C , a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the third direction Z), and another portion of the charge storage structure 40 (the blocking layer 36) surrounds the gate layer 38. In other embodiments, as shown in FIG1D , the charge storage structure 40 (the tunneling layer 14, the charge storage layer 12, and the blocking layer 36) surrounds the gate layer 38.

1E, the charge storage structure 40, the channel pillar 16, and the source pillar 32a and the drain pillar 32b are surrounded by the gate layer 38 and define the memory cell 20. The memory cell 20 can perform 1-bit operation or 2-bit operation by different operation methods. For example, when a voltage is applied to the source pillar 32a and the drain pillar 32b, since the source pillar 32a and the drain pillar 32b are connected to the channel pillar 16, electrons can be transmitted along the channel pillar 16 and stored in the entire charge storage structure 40, so that the memory cell 20 can be operated with 1 bit. In addition, for the operation using Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source pillar 32a and the drain pillar 32b. For the operation using source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons or holes can be locally trapped in the charge storage structure 40 of one of the two adjacent source pillars 32a and drain pillars 32b, so that the memory cell 20 can be operated in a single-bit cell (SLC, 1 bit) or a multi-bit cell (MLC, greater than or equal to 2 bits).

During operation, when a voltage is applied to the selected word line (gate layer) 38, for example, when a voltage higher than the corresponding starting voltage ( _Vth ) of the corresponding memory cell 20 is applied, the channel region of the channel pillar 16 intersecting the selected word line 38 is turned on, allowing current to enter the drain pillar 32b from the bit line _BLn or BLn ₊₁ (shown in FIG. 1B), and flow through the turned-on channel region to the source pillar 32a (for example, in the direction indicated by the arrow 60), and finally flow to the source line _SLn or SLn ₊₁ (shown in FIG. 1B).

In some embodiments, a conductive layer is further disposed between the stacked structure 52 and the dielectric substrate 50 to serve as a stop layer for etching the vertical channel hole, and the conductive layer is grounded so that the channel that cannot be controlled by the word line can be normally closed. However, due to process factors, the sidewall of the vertical channel hole usually has an inclined profile, making the vertical channel hole conical. When forming the holes of the source column (conductor column) 32a and the drain column (conductor column) 32b, the dielectric layer on the side wall of the conductive layer is likely to be consumed or removed during the etching process or the cleaning process, so that the side wall of the conductive layer is exposed in the hole, causing the subsequently formed source column (conductor column) 32a and the drain column (conductor column) 32b to have abnormal bridging with the conductive layer.

The memory device provided in the embodiment of the present invention removes the conductive layer originally disposed under the stacking structure in a subsequent manufacturing process, and then re-forms the insulating layer to avoid the problem of abnormal bridging between the conductive pillar and the conductive layer under the stacking structure.

Fig. 2A to Fig. 2K are top views of a manufacturing process of a memory element according to an embodiment of the present invention. Fig. 3A to Fig. 3K are cross-sectional views along line x-x' of Fig. 2A to Fig. 2K. Fig. 3I' to Fig. 3K' are cross-sectional views along line y-y' of Fig. 2I to Fig. 2K. Fig. 2A to Fig. 2G are top views along line I-I' of Fig. 3A to Fig. 3G. Fig. 2H to Fig. 2K are top views along line II-II' of Fig. 3H to Fig. 3K'.

Referring to FIG. 2A and FIG. 3A , a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer having a metal interconnect structure formed on a silicon substrate, such as a silicon oxide layer. The dielectric substrate 100 has a stop layer 92. The stop layer 92 is, for example, a patterned polysilicon layer. A conductor layer 94 is formed on the dielectric substrate 100. The material of the conductor layer 94 is, for example, polysilicon. A stacking structure 102 is formed on the conductor layer 94. The stacking structure 102 can also be referred to as an insulating stacking structure 102. In this embodiment, the stacking structure 102 is composed of insulating layers 104 and intermediate layers 106 stacked in sequence and staggered on the dielectric substrate 100. In other embodiments, the intermediate layers 106 and the insulating layers 104 are alternately stacked on the dielectric substrate 100 in the opposite order. In addition, in this embodiment, the top layer of the stacked structure 102 is the insulating layer 104. The thickness t1 of the bottom insulating layer 104 ₁ is greater than the thickness t2 of the insulating layer 104 ₂ between the plurality of intermediate layers 106. The insulating layer 104 is, for example, a silicon oxide layer. The intermediate layer 106 is, for example, a silicon nitride layer. In this embodiment, the stacked structure 102 has four insulating layers 104 and three intermediate layers 106, but the present invention is not limited thereto. In other embodiments, more insulating layers 104 and intermediate layers 106 may be formed according to actual needs. Afterwards, the stacked structure 102 is patterned to form a step structure (not shown). A lithography and etching process is performed to form a plurality of openings 108 (or vertical channel holes VC) in the stacked structure 102. However, only a single opening 108 is shown in FIG. 2A and FIG. 2B. The bottom surface of the opening 108 exposes the conductive layer 94, but does not expose the dielectric substrate 100.

2B and 3B, the etching process is continued to deepen the depth of the opening 108 so that the bottom of the opening 108 extends into the dielectric substrate 100. In the present embodiment, the opening 108 has a circular shape when viewed from above, but the present invention is not limited thereto. In other embodiments, the opening 108 may have other shapes, such as a polygon (not shown).

2C and 3C , a thermal oxidation process is performed to oxidize the surface of the sidewall of the middle layer 106 exposed by the opening 108 to form a protective layer 110. The material of the protective layer 110 is, for example, silicon oxide.

2D and 3D , a channel column 116 is formed on the side wall of the opening 108. The material of the channel column 116 may be a semiconductor material, such as undoped polysilicon. The method of forming the channel column 116 is, for example, to form a channel material on the stacked structure 102 and in the opening 108. Thereafter, an etching back process is performed to partially remove the channel material to form the channel column 116. The top view of the channel column 116 is, for example, annular, and may be continuous in its extension direction (for example, in a direction perpendicular to the dielectric substrate 100). That is, the channel column 116 is integral in its extension direction and is not divided into a plurality of unconnected parts. In some embodiments, the channel column 116 may have a circular shape when viewed from a top view, but the present invention is not limited thereto. In other embodiments, the channel column 116 may also have other shapes (such as a polygon) when viewed from above.

Referring to FIG. 2E and FIG. 3E , an insulating filling layer 124 is formed above the stacked structure 102 and in the opening 108. The material of the insulating filling layer 124 is, for example, silicon oxide. When the insulating filling layer 124 fills the opening 108, before the center of the opening 108 is completely filled and a hole is left, an insulating material different from the insulating filling layer 124, such as silicon nitride, is filled to completely seal the opening 108. The insulating material is etched back to expose the surface of the insulating filling layer 124 through a dry etching or wet etching process, and the insulating material left in the center of the opening 108 forms an insulating column 128.

2F and 3F, a patterning process is performed to form holes 130a and 130b in the insulating filling layer 124. The holes 130a and 130b extend from the top surface of the insulating filling layer 124 to the dielectric substrate 100. The shape of the hole pattern defined by the patterning process may be tangent to the shape of the insulating pillar 128. The shape of the hole pattern defined by the patterning process may also exceed the shape of the insulating pillar 128. Since the etching rate of the insulating pillar 128 is less than the etching rate of the insulating filling layer 124, the insulating pillar 128 is hardly damaged by etching and remains. A first conductive pillar 132a and a second conductive pillar 132b are formed in the holes 130a and 130b. The first conductive pillar 132a and the second conductive pillar 132b can be used as a source pillar and a drain pillar, respectively, and are electrically connected to the channel pillar 116, respectively. The first conductive pillar 132a and the second conductive pillar 132b can be formed by forming a conductive layer on the insulating filling layer 124 and in the holes 130a and 130b, and then etching back. The first conductive pillar 132a and the second conductive pillar 132b are, for example, doped polysilicon.

2G and 3G , a dielectric layer 125 is formed on the insulating filling layer 124, the first and second conductive pillars 132a and 132b, and the insulating pillar 128. The material of the dielectric layer 125 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Then, a patterning process is performed to form a plurality of separation trenches 133. The separation trenches 133 extend along the X direction to divide the stacking structure 102 and the conductive layer 94 into a plurality of blocks. The separation trenches 133 pass downward from the dielectric layer 125 through the stacking structure 102 and also extend to the conductive layer 94. The bottom of the separation trenches 133 may expose the dielectric substrate 100, or expose a portion of the conductive layer 94 (not shown).

2H and 3H , an etching process, such as a wet etching process, is performed to remove the conductive layer 94 and the protective layer 110 on the sidewall of the conductive layer 94 to form a horizontal opening OP1 . The horizontal opening OP1 exposes the outer sidewall of the channel pillar 116 .

Referring to FIG. 2I , FIG. 3I , and FIG. 3I ′, an etching process, such as a wet etching process, is performed to remove a portion of the channel column 116, a portion of the first conductive column 132a, and a portion of the second conductive column 132b to form a horizontal opening OP2. The horizontal opening OP2 exposes the insulating filling layer 124. When performing the etching process, a main etching process is performed first, and then an over-etching process is performed to remove more channel columns 116, the first conductive column 132a, and the second conductive column 132b, so that the horizontal opening OP2 has grooves R1 and R2. The groove R1 extends upward to between the top and bottom surfaces of the bottommost insulating layer 104, exposing the bottom surfaces of the remaining channel columns 116, the first conductive column 132a, and the second conductive column 132b. The bottom surfaces of the first conductive pillar 132a and the second conductive pillar 132b are located between the top surface and the bottom surface of the bottommost insulating layer _1041. The groove R2 extends downward into the dielectric substrate 100, exposing the remaining first conductive pillar 132a' and the second conductive pillar 132b'.

Referring to FIG. 2J , FIG. 3J and FIG. 3J ′, a gate replacement process is performed. First, an etching process, such as a wet etching process, is performed to remove a portion of the multi-layered middle layer 106 to form a plurality of horizontal openings 134. The plurality of horizontal openings 134 expose the protective layer 110. During the etching process, since the protective layer 110 and the middle layer 106 are made of different materials, the protective layer 110 can be used as an etching stop layer to protect the channel pillars 116.

2K, 3K and 3K', a tunneling layer 114, a charge storage layer 112, a blocking layer 136, a barrier layer 137 and a conductor layer 138 are formed in a plurality of horizontal openings 134. The tunneling layer 114 and the charge storage layer 112 are also formed in the horizontal opening OP2. The method of forming the tunneling layer 114, the charge storage layer 112, the blocking layer 136, the barrier layer 137 and the conductor layer 138 is, for example, to form a tunneling material, a charge storage material, a blocking material, a barrier material and a conductor material in a plurality of separation trenches 133, a plurality of horizontal openings 134 and OP2. Thereafter, an etching back process is performed to remove the conductive material, barrier material and blocking material in the plurality of separation trenches 133 and the horizontal opening OP2 to form a conductive layer 138, a blocking layer 136 and a barrier layer 137 in the horizontal opening 134.

Next, another etching process is performed to remove the charge storage material and the tunneling material in the plurality of separation trenches 133, so as to form the charge storage layer 112 and the tunneling layer 114 in the horizontal opening 134 and OP2. Thus, the gate stack structure 150 is formed. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes a plurality of gate layers 138 and a plurality of insulating layers 104 alternately stacked with each other.

Thereafter, a separation wall SLIT is formed in the plurality of separation trenches 133. The method for forming the separation wall SLIT includes filling an insulating material on the gate stack structure 150 and in the separation trench 133, and then removing excess insulating material on the gate stack structure 150 by an etching back process or a planarization process. The insulating material is, for example, silicon oxide or silicon nitride. In other embodiments, the separation wall SLIT may include a conductive layer and an insulating liner covering the outer side wall of the conductive layer. In other embodiments, the separation wall SLIT may also include an insulating layer and an air gap in the insulating layer.

In an embodiment of the present invention, the partition wall SLIT includes a main body P1 and an extension P2. The main body P1 extends in the third direction Z, passes through the stacking structure 150, and separates the conductive layer 138 of adjacent blocks. The extension P2 is connected to the main body P1 and is located between the stacking structure 150 and the dielectric substrate 100. The extension P2 is covered by the tunneling layer 114 and the charge storage layer 112. The tunneling layer 114 and the charge storage layer 112 are between the extension P2 and the first conductive pillar 132a and the second conductive pillar 132b. The tunneling layer 114 and the charge storage layer 112 are located between the extension portion P2 and the remaining first conductive pillar 132a1 and the remaining second conductive pillar 132b1.

The height H1 of the extension portion P2 in the first direction X is greater than the height H2 of the extension portion P2 in the second direction Y. The extension portion P2 includes a first protrusion Q1, a second protrusion Q2, and a middle portion Q3. The middle portion Q3 is between the first protrusion Q1 and the second protrusion Q2, and is connected to both of them. The first protrusion Q1 and the second protrusion Q2 are engaged with the first conductive pillar 132a and the second conductive pillar 132b and the remaining first conductive pillar 132a1 and the remaining second conductive pillar 132b1. The first protrusion Q1 and the second protrusion Q2 extend in opposite directions. The first protrusion Q1 extends toward the channel pillar 116. The top surface of the first protrusion Q1 is located between the top surface and the bottom surface of the lowest insulating layer _1041. The second protrusion Q2 extends toward the dielectric substrate 100.

The cross section of the extension portion P2 on the first plane XZ is, for example, a horizontal T-shape, as shown in FIG3K. The cross section of the extension portion P2 on the second plane YZ is, for example, a rectangle, as shown in FIG3K'. The top view of the extension portion P2 is semicircular or semi-elliptical, as shown in FIG2K. The first distance d1 between the extension portion P2 and the insulating column 128 in the first direction X is smaller than the second distance d2 between the extension portion P2 and the insulating column 128 in the second direction Y. The thickness t1 of the bottommost insulating layer 104 ₁ is greater than the thickness t2 of the insulating layer 104 ₂ between the plurality of conductive layers 138.

In the above embodiment, a single conductive layer 94 is provided under the stacked structure 102. However, the present invention is not limited thereto, and in other embodiments, multiple conductive layers 94a, 94b may be provided under the stacked structure 102 and separated by an insulating layer 104, and the manufacturing process is shown in FIGS. 4A to 4D.

4A to 4D are cross-sectional views of a manufacturing process of a memory device according to another embodiment of the present invention.

4A, a conductive layer 94a, an insulating layer 93, and a conductive layer 94b are formed on a dielectric substrate 100. The conductive layers 94a and 94b are, for example, semiconductor materials. The material of the insulating layer 93 is, for example, silicon oxide. Then, a stacking structure 102 is formed on the conductive layer 94b.

4B, an insulating filling layer 124, an insulating column 128, a first conductive column 132a, a second conductive column 132b, and a dielectric layer 125 are formed according to the method described above.

4C , a patterning process is performed to form a plurality of separation trenches 133. Then, an etching process is performed to remove the protective layer 110, the conductive layers 94a and 94b, a portion of the channel pillar 116, a portion of the first conductive pillar 132a, and a portion of the second conductive pillar 132b to form horizontal openings OP3 and OP4, and to leave the remaining first conductive pillar 132a2 and the remaining second conductive pillar 132b2 between the horizontal openings OP3 and OP4, and to leave the remaining first conductive pillar 132a1 and the remaining second conductive pillar 132b1 below the horizontal opening OP4.

4D, a gate replacement process is performed according to the above method to replace the multi-layer intermediate layer 106 with a tunneling layer 114, a charge storage layer 112, a blocking layer 136, a barrier layer 137 and a conductive layer 138. Similarly, the tunneling layer 114 and the charge storage layer 112 are also formed in the horizontal openings OP3 and OP4. Afterwards, a plurality of separation trenches 133 are filled to form a separation wall SLIT in the separation trenches 133.

In this embodiment, the partition wall SLIT includes a main portion P1 and an extension portion P2. The main portion P1 extends in the third direction Z, passes through the stacking structure 150, and separates the conductive layer 138 of adjacent blocks. The extension portion P2 includes a first portion G2 and a second portion G3. The first portion G2 and the second portion G3 are located between the stacking structure 150 and the dielectric substrate 100, and are connected to the main portion P1. The first portion G2 is located above the second portion G3. The first portion G2 and the second portion G3 are separated from each other by the insulating layer 93, the remaining first conductive pillar 132a2, and the remaining second conductive pillar 132b2.

The cross-section of the first part G2 and the second part G3 is, for example, a horizontal T-shape. The first part G2 and the second part G3 may each include a first protrusion S1, a second protrusion S2, and a middle part S3. The middle part S3 is between the first protrusion S1 and the second protrusion S2 and is connected to both of them. The first protrusion S1 extends toward the channel column 116. The top surface of the first protrusion S1 is located between the top surface and the bottom surface of the lowest insulating layer _1041. The second protrusion S2 extends toward the dielectric substrate 100.

5A and 5B are cross-sectional views of a manufacturing process of a memory device according to another embodiment of the present invention.

5A, in FIG. 4C above, if the first conductive pillar 132a2 and the second conductive pillar 132b2 are not left, and the insulating layer 93 is left on the dielectric substrate 100, a horizontal opening OP5 will be formed, as shown in FIG. 5A.

Referring to FIG. 5B , the above method is followed until a separation wall SLIT is formed. The separation wall SLIT includes a main portion P1 and an extension portion P2. The main portion P1 extends in the third direction Z and passes through the stacking structure 150. The extension portion P2 is connected to the main portion P1 and is located between the stacking structure 150 and the dielectric substrate 100. The cross-section of the extension portion P2 is, for example, a horizontal T-shape. The extension portion P2 includes a first protrusion M1, a second protrusion M2, and a middle portion M3. The middle portion M3 is between the first protrusion M1 and the second protrusion M2, and is connected to both of them. The first protrusion M1 extends toward the channel column 116. The top surface of the first protrusion M1 is located between the top surface and the bottom surface of the lowest insulating layer 104 _1. The second protrusion M2 extends toward the dielectric substrate 100.

In summary, the memory device of the embodiment of the present invention removes the conductive layer originally disposed under the stacked structure and then re-forms the insulating layer to avoid the problem of abnormal bridging between the conductive pillar and the conductive layer under the stacked gate.

10, A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array 12, 112: charge storage layer 14, 114: tunneling layer 16, 116: channel pillar 20: memory cell 24, 124: insulating filling layer 28, 128: insulating pillar 32a: first conductor pillar/source pillar 32b: second conductor pillar/drain pillar 36, 136: blocking layer 38: gate layer 38: word line 40: charge storage structure 50, 100: dielectric substrate 50s: surface 54, 93, 104, 104 ₁ , 104 ₂ : Insulation layer 60: Arrow 92: Stop layer 94, 94a, 94b, 138: Conductor layer 52, 102, 150: Stacked structure 106: Intermediate layer 108: Opening 110: Protective layer 125: Dielectric layer 130a, 130b: Holes 132a, 132a1, 132a2, 132a': First conductor pillars 132b, 132b1, 132b2, 132b': Second conductor pillar 133: Separation trenches 134, OP1, OP2, OP3, OP4: Horizontal opening 137: Barrier layer 138: Multi-layer gate layer BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : Blocks _BLn , BLn ₊₁ : bit lines SP ^{( i )} _n , SP ^{( i )} _n+1 , SP ^{( i+1 )} _n , SP ^{( i+1)} _n+1 : source pillars DP ^{( i )} _n , DP ^{i )} _n+1 , DP ⁱ⁺¹⁾ _n , DP ^{( i+1)} _n+1 : source pillars G2 : first part G3 : second part H1 , H2 : heights M1 , Q1 , S1 : first protrusions M2 , Q2 , S2 : second protrusions M3 , Q3 , S3 : middle part P1 : main part P2 : extensions R1 , R2 : grooves SLIT : partition wall VC : vertical channel hole X : first direction Y : second direction Z : third direction d1 : first distance d2 : second distance t1 , t2 : thicknesses I-I' , II-II' , x-x' , y-y' : line

FIG. 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A. FIG. 1C and FIG. 1D show a cross-sectional view of the cut line I-I’ of FIG. 1B. FIG. 1E shows a top view of the cut line II-II’ of FIG. 1B, FIG. 1C, and FIG. 1D. FIG. 2A to FIG. 2K are top views of a manufacturing process of a memory element according to an embodiment of the present invention. FIG. 3A to FIG. 3K’ are cross-sectional views of lines x-x’ and y-y’ of FIG. 2A to FIG. 2K. FIG. 4A to FIG. 4D are cross-sectional views of a manufacturing process of a memory element according to another embodiment of the present invention. Figures 5A to 5B are cross-sectional views of a manufacturing process of a memory element according to another embodiment of the present invention.

133: Separation channel

125: Dielectric layer

124: Insulation filling layer

104, 104 ₁ , 104 ₂ : Insulation layer

OP2: Horizontal opening

R1, R2: Groove

92: Stop layer

II-II’, x-x’: line

132a, 132a’: first conductor column

132b, 132b’: second conductor column

128: Insulation Pillar

116: Channel column

110: Protective layer

134: Horizontal opening

100: Dielectric substrate

Claims (12)

A memory element comprises: A stacking structure located on a dielectric substrate, wherein the stacking structure comprises a plurality of conductive layers and a plurality of insulating layers alternately stacked with each other; A channel column extending through the stacking structure; A plurality of conductive columns located in the channel column and electrically connected to the channel column; A charge storage structure located between the plurality of conductive layers and the channel column; A partition wall located in the stacking structure, wherein the partition wall comprises: A main body extending through the stacking structure; and An extension portion connected to the main body and located between the stacking structure and the dielectric substrate. A memory device as described in claim 1, wherein the charge storage structure also covers the extension portion. A memory element as described in claim 1, wherein the extension portion also extends below the channel column and the multiple conductive columns. A memory element as described in claim 1, wherein the length of the extension portion in the first direction is greater than the length of the extension portion in the second direction. A memory device as described in claim 1, wherein the extension portion includes a first protrusion extending toward the channel column. A memory element as described in claim 1, wherein the extension portion includes a second protrusion extending toward the dielectric substrate. A memory element as described in claim 1, wherein the cross-section of the extension portion on the first plane is a horizontal T-shape, and the cross-section of the extension portion on the second plane is a rectangle. A memory device as described in claim 1, wherein the thickness of the lowest insulating layer of the plurality of insulating layers is greater than the thickness of the insulating layers between the plurality of conductive layers. A memory element as described in claim 1, wherein the extension portion includes a first portion and a second portion, the first portion is located above the second portion and separated from each other. A method for manufacturing a memory element, comprising: forming a first conductive layer on a dielectric substrate; forming a stacking structure on the first conductive layer, wherein the stacking structure comprises a plurality of intermediate layers and a plurality of insulating layers stacked alternately with each other; forming a channel column extending through the stacking structure and the first conductive layer; forming a plurality of conductive columns electrically connected to the channel column in the channel column; forming a separation trench extending through the stacking structure and the first conductive layer; removing a portion of the first conductive layer, a portion of the channel column and a portion of the plurality of conductive columns to form a first horizontal opening; partially removing the plurality of intermediate layers to form a plurality of second horizontal openings; forming a charge storage layer in the first horizontal opening and the plurality of second horizontal openings; Forming a plurality of second conductive layers in the plurality of second horizontal openings; and Forming a main body of a partition wall in the partition trench, and forming an extension of the partition wall in the first horizontal opening. The method for manufacturing a memory element as described in claim 10 further includes forming an insulating column in the channel column to separate the multiple conductive columns, wherein a first distance between the extension portion and the insulating column in a first direction is smaller than a second distance between the extension portion and the insulating column in a second direction. A method for manufacturing a memory element as described in claim 10, wherein the cross-section of the extension portion on the first plane is a horizontal T-shape, and the cross-section of the extension portion on the second plane is a rectangle.

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