TWI805228B - 3d and flash memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes a dielectric substrate, a conductive layer, a gate stack structure, a plurality of ring-shaped slits and a plurality of inner slits. The conductive layer is located on the dielectric substrate. The gate stack structure is located on a first part of the conductive layer. The dielectric layer is located on the gate stack structure and a second part of the conductive layer. The plurality of ring-shaped slits extends through the dielectric layer, the gate stack structure and the conductive layer to define a plurality of tiles. The plurality of inner slits are arranged in the ring-shaped slits to define a plurality of blocks in each ring-shaped slit. A height of the plurality of inner slits is the same as a height of the plurality of ring-shaped slits.

Description

Three-dimensional AND flash memory device and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a flash memory element and its manufacturing method.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The 3D memory commonly used in the industry currently includes Negative OR (NOR) memory and Negative AND (NAND) memory. In addition, another type of three-dimensional memory is AND memory, which can be applied in a multi-dimensional memory array and has high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become a current trend. However, there are still many challenges associated with 3D memory elements.

A memory device according to an embodiment of the present invention includes: a dielectric substrate, a conductor layer, a gate stack structure, a plurality of annular partition walls, and a plurality of inner partition walls. A conductor layer is located on the dielectric substrate. The gate stack structure is located on the conductor layer. The dielectric layer is located on the gate stack structure. A plurality of annular partition walls define a plurality of block elements for the dielectric layer, the gate stack structure and the conductor layer. Each inner partition wall is arranged in the plurality of annular partition walls, and each block unit defines a plurality of blocks. The plurality of inner partition walls have the same height as the plurality of annular partition walls.

A memory element according to an embodiment of the present invention includes: a substrate, an interconnection structure, a conductor layer, a gate stack structure, a dielectric layer, and a separation structure. The substrate includes an array area, a step area and an edge area, wherein the edge area surrounds the step area, and the step area surrounds the array area. The interconnection structure is located on the base of the array area and the step area. The conductor layer is located on the interconnect structure of the array area, the step area and the edge area. The gate stack structure is located on the conductor layer of the array area and the step area, wherein the gate stack structure in the step area has a step structure. The dielectric layer is located on the conductor layer in the edge area and the stepped structure in the stepped area. The separation structure extends through the array region and the gate stack structure of the step region, the step structure of the gate stack structure and the conductor layer to define block elements, and in the block Multiple blocks are formed in the meta.

A method for manufacturing a memory device according to an embodiment of the present invention includes: providing a dielectric substrate. A blanket conductor layer is formed to cover the dielectric substrate. A gate stack structure is formed on the blanket conductor layer. A plurality of via holes are formed in the gate stack structure, wherein the via holes expose the blanket conductor layer. A channel column is formed in each channel hole. A charge storage structure is formed between the channel pillar and the plurality of gate conductor layers of the gate stack structure. A dielectric layer is formed on the gate stack structure and the blanket conductor layer. A plurality of separation structures are formed extending through the dielectric layer, the gate stack structure and the blanket conductor layer to define a plurality of blocks, and each block defines a plurality of blocks.

Based on the above, in the embodiment of the present invention, the conductor layer under the stacked structure is patterned when the Slit structure is formed. Therefore, during the dry etching (for example, plasma etching) for forming the channel opening, this The conductor layer can be used as a conduction path for charges to reduce the arc effect and avoid damage to various material layers and components on the substrate due to plasma bombardment, thus improving the yield rate of the process.

Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A . FIG. 1C and FIG. 1D show cross-sectional views of the line I-I' in FIG. 1B. Fig. 1E shows a top view of the line II-II' of Fig. 1B, Fig. 1C and Fig. 1D.

FIG. 1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ including vertical AND memory arrays 10 arranged in columns and rows. Block BLOCK ⁽ⁱ⁾ includes memory array A ⁽ⁱ⁾ . A column (eg column m+1) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A ⁽ⁱ⁾ correspond to a common word line (eg WL ⁽ⁱ⁾ _m+1 ), and are coupled to different source columns (such as SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (such as DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cell 20 is along a common word line (such as WL ⁽ⁱ⁾ _m+1 ) are logically arranged into a column.

A row (eg row n) of the memory array A ^{( i )} is a set of AND memory cells 20 having a common source column (eg SP ^{( i )} _n ) and a common drain column (eg DP ^{( i )} _n ). The AND memory cells 20 of each row (eg row n) of the memory array A ⁽ⁱ⁾ correspond to different word lines (eg WL ^{( i )} _m+1 and WL ^{( i )} _m ), and are coupled to a common source posts (eg SP ^{( i )} _n ) and common drain posts (eg DP ^{( i )} _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁾ are logically arranged in a row along a common source column (eg, SP ^{( i )} _n ) and a common drain column (eg, DP ^{( i )} _n ). In a physical layout, the rows or columns may be distorted, arranged in a honeycomb pattern or otherwise, for high density or for other reasons, depending on the fabrication method applied.

In FIG. 1A, in the block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of the memory array A ⁽ⁱ⁾ share a common source column (for example, SP ^{( i )} _n ) and a common drain column. (e.g. DP ^{( i )} _n ). The AND memory cells 20 in row n+1 share a common source column (eg SP ⁽ⁱ⁾ _n+1 ) and a common drain column (eg DP ^{( i )} _n+1 ).

A common source post (eg SP ^{( i )} _n ) is coupled to a common source line (eg SL _n ); a common drain post (eg DP ^{( i )} _n ) is coupled to a common bit line ( eg _BLn ). A common source post (eg SP ^{( i )} _n+1 ) is coupled to a common source line (eg SL _n+1 ); a common drain post (eg DP ^{( i )} _n+1 ) is coupled to a common bit line (eg BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes memory array A ⁽ⁱ⁺¹⁾ which is similar to memory array A ^{(i) in block BLOCK (i) .} A column (eg column ^{m+1) of the memory array A (i} +1) is a set of AND memory cells 20 having a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ). The AND memory cells 20 of each column (eg column m+1) of the memory array A ⁽ⁱ +1) correspond to a common word line (eg WL ⁽ⁱ⁺¹⁾ _m+1 ), and are coupled to different source columns (eg SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain columns (eg DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (for example, row n) of memory array A ^{( i+1 )} has a common source column (for example, SP ^{( i+1 )} _n ) and a common drain column (for example, DP ^{( i+1 )} _n ) AND memory cells 20 sets. The AND memory cells 20 of each row (for example, row n) of the memory array A ⁽ⁱ⁺¹ ) correspond to different word lines (for example, WL ^{( i+1 )} _m+1 and WL ^{( i+1 )} _m ) , and are coupled to a common source post (eg SP ^{( i+1 )} _n ) and a common drain post (eg DP ^{( i+1 )} _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁺¹⁾ are logically configured along a common source column (eg SP ^{( i+1 )} _n ) and a common drain column (eg DP ^{( i+1 )} _n ) one line.

The block BLOCK ⁽ⁱ⁺¹⁾ and the block BLOCK ⁽ⁱ⁾ share source lines (such as SL _n and SL _n+1 ) and bit lines (such as BL _n and BL _n+1 ). Therefore, the source line SL _n and the bit line BL _n are coupled to the nth row of AND memory cells 20 in the AND memory array A (i) of the block BLOCK ^{( i)} , and are coupled to the block BLOCK ^{(i +1)} in the AND memory cell 20 in the nth row of the AND memory array A ⁽ⁱ⁺¹⁾ . Similarly, the source line SL _n+1 and the bit line BL _n+1 are coupled to the n+1th row of AND memory cells 20 in the AND memory array A ⁽ⁱ⁾ of the block BLOCK ⁽ⁱ ), and are coupled to To the AND memory unit 20 in the n+1th row of the AND memory array A ^{( i+1) in the block BLOCK (i} +1).

Referring to FIG. 1B to FIG. 1D , the memory array 10 can be disposed on the interconnection structure of the semiconductor die, such as disposed on one or more active devices (such as transistors) formed on the semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the metal interconnect structure on the silicon substrate. The memory array 10 may include a gate stack structure 52, a plurality of channel pillars 16, a plurality of first conductive pillars (also called source pillars) 32a, and a plurality of second conductive pillars (also called drain pillars). 32b and a plurality of charge storage structures 40.

Referring to FIG. 1B , the gate stack structure 52 is formed on the dielectric substrate 50 in the array region (not shown) and the step region (not shown). The gate stack structure 52 includes a plurality of gate layers (also referred to as word lines) 38 and multiple layers of insulating layers 54 vertically stacked on the surface 50 s of the dielectric substrate 50 . In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. The gate layer 38 extends in a direction parallel to the surface of the dielectric substrate 50 . The gate layer 38 of the stepped region may have a stepped structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38 , and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38 . Contact windows (not shown) for connecting to the gate layer 38 may be landed at the ends of the gate layer 38 so as to connect each gate layer 38 to each wire.

Please refer to FIG. 1B to FIG. 1D , the memory array 10 further includes a plurality of channel columns 16 . The channel pillar 16 continuously extends through the gate stack 52 and extends to the conductor layer 53 between the substrate 100 and the gate stack 52 . The material of the conductive layer 53 may include doped polysilicon. For example, the material of the conductive layer 53 may include P-type doped polysilicon. In some embodiments, the channel post 16 may have a ring-shaped profile when viewed from above. The material of the channel pillar 16 can be semiconductor, such as undoped polysilicon.

Referring to FIG. 1B to FIG. 1D , the memory array 10 further includes insulating columns 28 , a plurality of first conductive columns 32 a and a plurality of second conductive columns 32 b. In this example, the first conductive post 32a is used as a source post; the second conductive post 32b is used as a drain post. The first conductive pillar 32 a , the second conductive pillar 32 b and the insulating pillar 28 each extend in a direction (ie, a Z direction) perpendicular to a surface of the gate layer 38 (ie, an XY plane). The first conductive post 32 a and the second conductive post 32 b are separated by the insulating post 28 and surrounded by the insulating filling layer 24 . The first conductive post 32 a and the second conductive post 32 b are electrically connected to the channel post 16 . The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating pillar 28 is, for example, silicon nitride or silicon oxide, and the insulating filling layer 24 is, for example, silicon oxide.

Referring to FIG. 1C and FIG. 1D , the charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38 . The charge storage structure 40 may include a tunneling layer (or called a bandgap engineered tunnel oxide layer) 14 , a charge storage layer 12 and a blocking layer 36 . The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36 . In some embodiments, the tunneling layer 14 and the barrier layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can trap charges. In some embodiments, as shown in FIG. 1C , a part of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12 ) extends continuously in a direction perpendicular to the gate layer 38 (ie, the Z direction), and the charge storage Another portion of structure 40 (barrier layer 36 ) surrounds gate layer 38 . In other embodiments, as shown in FIG. 1D , the charge storage structure 40 (the tunneling layer 14 , the charge storage layer 12 and the blocking layer 36 ) surrounds the gate layer 38 .

Referring to FIG. 1E , the charge storage structure 40 , the channel column 16 , the source column 32 a and the drain column 32 b are surrounded by the gate layer 38 and define the memory cell 20 . The memory unit 20 can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column 32a and the drain column 32b, since the source column 32a and the drain column 32b are connected to the channel column 16, electrons can be transmitted along the channel column 16 and stored in the entire charge storage In the structure 40, a 1-bit operation can be performed on the memory unit 20 in this way. In addition, for the operation utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and the drain post 32b. . For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons can be Or the holes are locally trapped in the charge storage structure 40 adjacent to one of the two source posts 32a and drain posts 32b, so that the unit cell (SLC, 1 bit) or multiple Bit cell (MLC, greater than or equal to 2 bits) operations.

In operation, a voltage is applied to a selected word line (gate layer) 38 , such as when a corresponding threshold voltage (V _th ) higher than that of the corresponding memory cell 20 is applied, intersecting the selected word line 38 The channel region of the channel column 16 is turned on, allowing current to enter the drain column 32b from the bit line BL _n or BL _n+1 (shown in FIG. 1B ) and flow to the source column 32a (eg , in the direction indicated by the arrow 60 ), finally flows to the source line SL _n or SL _n+1 (shown in FIG. 1B ).

FIG. 2A shows a top view of a memory die according to an embodiment of the invention. FIG. 2B shows a top view of a partial area of FIG. 2A.

Please refer to FIG. 2A and FIG. 2B , the memory chip MC- 1 is, for example, an AND memory element. The memory chip MC-1 may include a region C1 and a region C2. Region C1 may include a plurality of tiles T separated from each other. The block elements T can be arranged in an array with multiple rows and multiple columns. In FIG. 2A , the block element array is formed by 7 rows and 8 columns, however, the embodiment of the present invention is not limited thereto. Each block T in area C1 has multiple memory arrays. The region C2 includes peripheral circuits, such as complementary metal oxide semiconductor devices (CMOS), disposed on the periphery of the block array.

Please refer to FIG. 2A and FIG. 2B , the memory chip MC- 1 further includes multiple sets of separation structures SLT. Each set of partition structures SLT includes a first partition wall SLT1 and a plurality of second partition walls SLT2.

The first partition wall SLT1 surrounds the periphery of the plurality of second partition walls SLT2, and the plurality of second partition walls SLT2 are formed inside the first partition wall SLT1. Therefore, the first partition wall SLT1 can also be called an outer partition wall SLT1, and the second partition wall SLT2 can also be called an inner partition wall SLT2. The top view of the first partition wall SLT1 may be circular, therefore, the first partition wall SLT1 may also be called a circular wall. The second partition wall SLT2 is a long strip extending in the X direction, therefore, the second partition wall SLT2 can also be called a long wall.

The plurality of first partition walls SLT1 define a plurality of blocks T separated from each other. Each block T may include an array area AR, a step area SR and an edge area ER. The stepped area SR is around the array area AR. The edge region ER is around the step region SR. The first partition wall SLT1 separates the two tiles T from each other. A plurality of second partition walls SLT2 are formed in the blocks T, and each block T defines a plurality of blocks B. FIG. 2B includes three blocks B1 , B2 and B3 , however, the embodiment of the present invention is not limited thereto.

The first partition wall SLT1 includes two first partitions P1 and two second partitions P2 connected to each other at ends. The first partition P1 extends in the X direction and is formed in the array region AR, the stepped region SR and the edge region ER. The plurality of second partitions P2 extend in the Y direction and are formed in the edge region ER. In some embodiments, the X direction is also called the first direction, the Y direction is also called the second direction, and the Z direction is also called the third direction.

Referring to FIG. 2B , a plurality of first partition walls SLT1 are separated from each other, and can be arranged in an array of rows and columns to define a block array composed of a plurality of blocks.

Please refer to FIG. 2B . In the embodiment of the present invention, before forming the separation structure SLT, the conductor layer 103 below the gate stack structure GSK is kept unpatterned and blanket-covered on the dielectric substrate 50, which can be used to form channels. The openings are used as discharge paths during the etching process. Therefore, the three-dimensional memory device according to the embodiment of the present invention does not need to additionally provide a discharge circuit in the interconnection structure below the gate stack structure GSK.

3A to 3F show top views of a manufacturing process of a memory device according to an embodiment of the present invention. 4A to 4F show cross-sectional views of the manufacturing process of a memory device according to an embodiment of the present invention.

Referring to FIG. 3A and FIG. 4A , a substrate 90 is provided. The substrate 90 includes an array region AR, a stepped region SR and an edge region ER. The substrate 90 may include a semiconductor substrate, such as a silicon substrate. The substrate 90 may include components such as active elements (such as PMOS, NMOS, CMOS, JFET, BJT, or diodes) or passive elements. An interconnection structure 92 is formed on the array region AR and the step region SR of the substrate 90 . The interconnect structure 92 may include components such as an interlayer dielectric layer, a contact window, a wire, an interlayer dielectric layer, and a via window. The material of the interlayer dielectric layer and the interlayer dielectric layer is, for example, a silicon oxide layer. Next, a dielectric layer 100 is formed on the interconnect structure 92 . The material of the dielectric layer 100 is silicon oxide, for example. In some embodiments, the dielectric layer 100 may also be referred to as a dielectric substrate 100 .

Next, please continue to refer to FIG. 3A and FIG. 4A , a blanket conductive layer 103 is formed on the dielectric layer 100 in the array region AR and the step region SR. The conductor layer 103 also extends to the edge region ER. The conductive layer 103 is, for example, a grounded P-type doped polysilicon layer. The conductive layer 103 can also be called a dummy gate, which can be used to close the leakage path.

Referring to FIG. 3B and FIG. 4B , a stack structure SK1 is formed on the conductor layer 103 . The stack structure SK1 can also be called an insulating stack structure SK1. In this embodiment, the stack structure SK1 is composed of insulating layers 104 and intermediate layers 106 stacked on the conductive layer 103 in sequence. In other embodiments, the stack structure SK1 may be formed by the intermediate layer 106 and the insulating layer 104 that are sequentially stacked on the conductive layer 103 . In addition, in this embodiment, the uppermost layer of the stack structure SK1 is the insulating layer 104 . The material of the insulating layer 104 is, for example, silicon oxide. The material of the middle layer 106 is, for example, silicon nitride. The intermediate layer 106 can be used as a sacrificial layer, which is partially removed in subsequent processes. In this embodiment, the stack structure SK1 has 5 layers of insulating layers 104 and 4 layers of intermediate layers 106 , but the invention is not limited thereto. In other embodiments, more insulating layers 104 and more intermediate layers 106 can be formed according to actual needs.

Referring to FIG. 3B , the stacked structure SK1 is patterned to form a stepped structure SC in the stepped region SR, and part of the stacked structure SK1 in the edge region ER is removed to expose the surface 90 s of the substrate 90 . For simplicity, the stair structure SC is not shown in FIG. 4B.

Referring to FIG. 3C and FIG. 4C , a dielectric layer 105 is formed on the substrate 90 to cover the stepped structure SC. The material of the dielectric layer 105 is, for example, silicon oxide. The method for forming the dielectric layer 105 is, for example, to form a dielectric material layer to fill the capping step structure SC. Afterwards, a planarization process is performed by, for example, a chemical mechanical polishing process.

Afterwards, a mask layer HM1 is formed on the dielectric layer 105 . The hard mask layer HM1 is, for example, a carbon-containing layer. The hard mask layer HM1 covers the array region AR, the step region SR and the edge region ER, and is electrically connected to the surface 90s of the substrate 90 and the sidewall 103s of the conductor layer 103 in the edge region ER. That is, the conductor layer 103 can be electrically connected to the substrate 90 via the hard mask layer HM1 .

Then, the hard mask layer HM1 is patterned (such as lithography and etching process). Next, an etching process is performed by using the hard mask layer HM1 as a mask to form a plurality of openings VC in the stack structure SK1 . The opening VC exposes the conductor layer 103 . The etching process can be a dry etching process, a wet etching process or a combination thereof. The dry etching process is, for example, a plasma etching process. Since the conductive layer 103 covers the substrate 90 in a blanket manner, the conductive layer 103 can be used as a conduction path for charges during the plasma etching process, and the charges are guided to the substrate 90 through the hard mask layer HM1. Therefore, the arc effect can be reduced, and various material layers and components on the substrate 90 can be prevented from being damaged by plasma bombardment.

In this embodiment, the opening VC does not extend through the conductive layer 103 . In this embodiment, from the above perspective, the opening VC has a circular outline, but the invention is not limited thereto. In other embodiments, the opening VC may have other shaped contours, such as a polygon (not shown).

Referring to FIG. 3D and FIG. 4D , the hard mask layer HM1 is removed. The tunneling material and channel material of the charge storage structure 140 are formed in the opening VC. Next, an etch-back process is performed to locally remove the channel material and the tunneling material to form the channel pillar 116 and the tunneling layer 114 .

The tunneling layer 114 and the channel pillar 116 may extend through the stack structure SK1 and not extend through the conductor layer 103 , but is not limited thereto. The upper view of the channel column 116 is, for example, ring-shaped, and may be continuous in its extending direction (eg, in a direction perpendicular to the surface 90 s of the base 90 ). That is to say, the channel column 116 is integral in its extending direction, and is not divided into a plurality of disconnected parts. In some embodiments, the channel post 116 may have a circular profile when viewed from above, but the invention is not limited thereto. In other embodiments, the channel column 116 may also have other shapes (such as polygonal) contours from the above perspective.

An insulating filling material is filled on the stack structure SK1 and in the opening VC. The insulating filling material is, for example, low temperature silicon oxide. The insulating filling material filled into the opening VC forms the insulating filling layer 124 and leaves a circular void in the center of the insulating filling layer 124 . Then, an anisotropic etching process is performed to enlarge the circular pores to form holes 109 . A layer of insulating material is formed on the insulating fill layer 124 and in the hole 109 . Then, an anisotropic etching process is performed to remove part of the insulating material layer to form insulating pillars 128 in the holes 109 . The material of the insulating pillar 128 is different from that of the insulating filling layer 124 . The material of the insulating pillar 128 is, for example, silicon nitride.

Referring to FIG. 3E and FIG. 4E , a patterning process, such as lithography and etching process, is performed to form holes 130 a and 130 b in the insulating filling layer 124 . During the etching process, the conductive layer 103 can be used as an etching stop layer. Therefore, the formed holes 130 a and 130 b extend from the stack structure SK1 to the exposed conductor layer 103 . The contour of the hole pattern defined by the patterning process may be tangent to the contour of the insulating pillar 128 . The contour of the pattern of holes defined by the patterning process may also extend beyond the contour of the insulating posts 128 (not shown).

Then, a cap insulating layer 115 is formed on the stacked structure SK1. The material of the top insulating layer 115 is, for example, a silicon oxide layer.

Referring to FIG. 3E and FIG. 4E , afterward, a wafer bevel engineering process is performed to remove part of the top insulating layer 115 of the edge region ER, so that the surface 90s of the substrate 90 is exposed. Next, a hard mask layer HM2 is formed on the cap insulating layer 115 . The hard mask layer HM2 is, for example, a carbon-containing layer. The hard mask layer HM2 covers the array region AR, the step region SR and the top insulating layer 115 of the edge region ER, and is electrically connected to the surface 90s of the substrate 90 and the sidewall 103s of the conductor layer 103 in the edge region ER.

The hard mask layer HM2 is patterned (such as lithography and etching processes), and the hard mask layer HM2 is patterned. Next, an etching process is performed by using the hard mask layer HM2 as a mask to pattern the stack structure SK1 and the conductor layer 103 to form separation trenches 133 . During the etching process, the dielectric layer 100 or the conductive layer 103 can be used as an etching stop layer, so that the separation trench 133 exposes the dielectric layer 100 or the conductive layer 103 . The etching process may be a dry etching process, such as a plasma etching process. Since the hard mask layer HM2 is a carbon-containing layer, the conductive layer 103 can be used as a conduction path for charges during the plasma etching, and the charges are guided to the substrate 90 through the hard mask layer HM2 to reduce the arc effect and avoid Various material layers and components on the substrate 90 are damaged by the plasma bombardment.

Each separation trench 133 includes a first separation trench 133 ₁ and a plurality of second separation trenches 133 ₂ . The first separation trench 133 ₁ surrounds the periphery of the plurality of second separation trenches 133 ₂ , and the plurality of second separation trenches 133 ₂ are inside the first separation trench 133 ₁ . Therefore, the first separation trench 133 ₁ can also be called an outer separation trench, and the second separation trench 133 ₂ can also be called an inner separation trench. The first separation trench ₁₃₃₁ may be an annular separation trench. The first separation trench 133 ₁ patterns the stack structure SK1 and the conductor layer 103 into a plurality of blocks T (eg T1 , T2 , T2 , T4 ). The plurality of second separation trenches 133 ₂ divides each block T into a plurality of blocks B (eg, B1, B2, B3).

Referring to FIG. 3F and FIG. 4F , the hard mask layer HM2 is removed. Afterwards, a replacement process is performed on the multi-layer intermediate layer 106 . First, an etching process, such as a wet etching process, is performed to remove part of the multi-layer intermediate layer 106 . The etchant (such as hot phosphoric acid) used in the etching process is injected into the separation trench 133 , and then the contacted part of the multi-layer intermediate layer 106 is removed to form a plurality of horizontal openings 134 .

A multilayer charge storage layer 112 , a multilayer barrier layer 136 , and a multilayer gate layer 138 are formed in the plurality of horizontal openings 134 . The charge storage layer 112 is, for example, silicon nitride. The barrier layer 136 is, for example, a material with a high dielectric constant greater than or equal to 7, such as aluminum oxide (Al ₁ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxide , lanthanide oxides, or combinations thereof. The gate layer 138 is, for example, tungsten. In some embodiments, before forming the multilayer gate layer 138 , a barrier layer 137 is also formed. The material of the barrier layer 137 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

The formation method of the charge storage layer 112, the barrier layer 136, the barrier layer 137 and the gate layer 138 is, for example, sequentially forming the storage material, the barrier material, the barrier material and the conductor material in the separation trench 133 and the horizontal opening 134, and then , and then perform an etch-back process to remove the storage material, barrier material, barrier material, and conductor material in the plurality of separation trenches 133, so as to form the charge storage layer 112, the barrier layer 136, and the barrier layer in the plurality of horizontal openings 134. 137 and gate layer 138. The tunneling layer 114 , the charge storage layer 112 , and the blocking layer 136 are collectively referred to as the charge storage structure 140 . So far, the gate stack structure GSK is formed. The gate stack structure GSK is disposed on the dielectric substrate 100 and includes multiple gate layers 138 and multiple insulating layers 104 stacked alternately.

Referring to FIG. 3F and FIG. 4F , the separation structure SLT is formed in the separation trench 133 . That is, the first partition wall SLT1 is formed in the partition trench ₁₃₃₁ , and the second partition wall SLT2 is formed in the partition trench ₁₃₃₂ . The first partition wall SLT1 has the same height as the second partition wall SLT2. The height of the first partition wall SLT1 and the second partition wall SLT2 is greater than the height of the conductor layer 103 and greater than the height of the gate stack structure GSK. The separation structure SLT can be single-layer or multi-layer, as shown in FIG. 5A to FIG. 5C .

Referring to FIG. 3F , FIG. 4F and FIG. 5A , in some embodiments, the formation method of the separation structure SLT is as follows. An insulating liner and conductor materials are filled on the gate stack structure GSK and in the separation trench 133 . Insulating liner such as silicon oxide. The conductive material is, for example, polysilicon. Then, the excess insulating liner material and conductive material on the gate stack structure GSK and the edge region ER are removed through an etch-back process or a planarization process, so as to form the liner layer 142 and the conductive layer 144 . Afterwards, a dielectric material is formed on the substrate 90 , and then an etch-back process or a planarization process may be performed to planarize the dielectric material to form the dielectric layer 146 . The liner layer 142 , the conductive layer 144 and a part of the dielectric layer 146 form a separation structure SLT, as shown in FIG. 5A .

In some embodiments, the separation structure SLT may also be completely filled with insulating material 142' without any conductive material, as shown in FIG. 5B . In some other embodiments, the separation structure SLT may also be a liner 142 , and the liner 142 covers an air gap AG without any conductive material, as shown in FIG. 5C .

6A to 6D show perspective views and cross-sectional views of respective partial areas 99A, 99B, 99C, 99D in FIG. 3F.

Please refer to FIG. 3F and FIG. 6A. In the area 99A of FIG. 3F, the first partition P1 of the first partition wall SLT1 connects the gate stack structure GSK of the block T1 to the gate between the block T1 and the block T2. The pole stack structure GSK' is separated. The edges of the conductive layer 103 are aligned with the edges of the gate stack GSK and the gate stack GSK'.

Please refer to FIG. 6B, in the area 99B of FIG. 3F, the first partition P1 of the first partition wall SLT1 separates the ladder structure SC of the block T3 from the ladder structure SC' between the block T3 and the block T4 open. The conductive layer 103 extends from the stepped region SR to the edge region ER. The first partial surface 103S1 of the conductor layer 103 in the step region SR is covered by the step structure SC of the block T3 and the step structure SC' between the block T3 and the block T4, and the step structures SC and SC' are covered by a dielectric layer 105 covered. The surface 103S2 of the conductor layer 103 (second portion) in the edge region ER is covered with the dielectric layer 105 . The sidewalls of the conductor layer 103 are in contact with the sidewalls SW1 of the first partition P1 of the first partition wall SLT1 .

Referring to FIG. 3F and FIG. 6C , in the area 99C of FIG. 3F , the second partition portion P2 of the first partition wall SLT1 is located on the edge region ER of the block T1 . Moreover, the sidewalls of the second partition portion P2 of the first partition wall SLT1 are in contact with the sidewalls 103 s of the conductive layer 103 and the sidewalls 105 s of the dielectric layer 105 covering the stepped structure SC and the conductive layer 103 .

Referring to FIG. 3F and FIG. 6D , in the area 99D in FIG. 3F , there are two second partitions P2 of the first partition wall SLT1 between adjacent blocks T1 and T3 . The two second partitions P2 pass through the dielectric layer 105 and the conductive layer 103 on the edge region ER. Moreover, the outer sidewall SW2 of the second partition portion P2 of the first partition wall SLT1 is in contact with the sidewall 103s1 of the conductive layer 103 and the sidewall 105s1 of the dielectric layer 105 covering the stepped structure SC and the conductive layer 103 . The inner sidewall SW3 of the second partition portion P2 of the first partition wall SLT1 is in contact with the sidewall 103s2 of the conductor layer 103 and the sidewall 105s2 of the dielectric layer 105 covering the conductor layer 103 .

FIG. 7A shows a top view of multiple blocks of a memory device according to another embodiment of the present invention. FIG. 7B shows a top view of multiple blocks of a memory device according to yet another embodiment of the present invention. 6E and 6F show perspective and cross-sectional views of partial areas 99E and 99F in FIGS. 7A and 7B .

Referring to FIG. 7A , in some embodiments, at least one dummy partition wall DSLT may be further included between two adjacent blocks T1 and T3 and between blocks T2 and T4 . A dummy partition wall DSLT may be formed between adjacent two second partition parts P2. The dummy partition wall DSLT and the second partition part P2 may be formed at the same time.

Please refer to FIG. 7B , in some embodiments, the first partition P11 of the first partition wall SLT1 extends from the array region AR to the step region SR and the edge region ER, and passes through the gate stack structure GSK, the step structure SC, the interposer The electrical layer 105 and the conductor layer 103 (as shown in FIG. 6E ). The first partition portion P12 of the first partition wall SLT1 is disposed in the edge region ER around the stepped structure SC and extends through the dielectric layer 105 and the conductor layer 103 in the edge region ER, as shown in FIG. 6F .

In addition to being used in 3D AND flash memory, the present invention can also be used in 3D NOR flash memory and 3D NAND flash memory. The structure of the 3D NOR flash memory can be shown in FIG. 2A. The chip MC-2 of the 3D NAND flash memory can be shown in FIG. 8 .

Based on the above, in the embodiment of the present invention, the conductor layer located under the stack structure is patterned when the separation trench is formed. Therefore, during the dry etching (for example, plasma etching) for forming channel openings in the stack structure, The conductor layer can be used as a conduction path for charges to reduce the arc effect and avoid damage to various material layers and components on the substrate due to plasma bombardment. Therefore, the method of the embodiment of the present invention can improve the yield of the process.

10. A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array 12: charge storage layer 14, 114: tunneling layer 15, 56, 156: separation layer 16, 116: channel column 20: memory unit 24, 124 : insulating filling layer 28, 128: insulating pillar 32a: source pole/conductor pillar 32b: drain pole/conductor pillar 36, 136: barrier layer 38, 138: gate layer/word line 40, 140: charge storage structure 50, 100: dielectric substrate 52, GSK, GSK': gate stack structure 54, 101, 104: insulating layer 60: arrow 90: substrate 90s: surface 92: interconnection structure 102: stop layer 103: conductor layer 103S1 , 103S2: surface 105: dielectric layer 106: intermediate layer 108: opening 109: hole 110: protective layer 112: charge storage layer 115: top cover insulating layer 130a, 130b: hole 132a, 132b: conductor post 133, 133 ₁ , 133 ₂ : separation trench 134: horizontal opening 137: barrier layer 142: lining layer 142': insulating material 144: conductor layer 146: dielectric layer AG: air gap B, B1, B2, B3: block BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : sub-block BL _n , BL _n+1 : bit line C1, C2: area SP ^{( i )} _n , SP ⁽ⁱ⁾ _n+1 , SP ^{( i+1 )} _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source column DP ⁽ⁱ⁾ _n , DP ⁱ⁾ _n+1 , DP ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : source column SK1: Stacked structure WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : word line X, Y, Z: direction I-I', II -II': tangent line MC-1, MC-2: wafer 99A, 99B, 99C, 99D, 99E, 99F: region 103s1, 103s2, 105s, 105s1, 105s2, SW1, SW2, SW3: sidewall SLT: partition structure SLT1, SLT2: partition wall T, T1, T2, T3, T4: block element ER: edge area SR: step area AR: array area P1: first partition P2: second partition

FIG. 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments of the present invention. FIG. 1B shows a partial three-dimensional view of part of the memory array in FIG. 1A. FIG. 1C and FIG. 1D show cross-sectional views of the line I-I' in FIG. 1B. Fig. 1E shows a top view of the line II-II' of Fig. 1B, Fig. 1C, Fig. 1D. FIG. 2A shows a top view of a memory die according to an embodiment of the invention. FIG. 2B shows a top view of a partial area of FIG. 2A. 3A to 3F show top views of a manufacturing process of a memory device according to an embodiment of the present invention. 4A to 4F illustrate cross-sectional views of a manufacturing process of a memory device according to an embodiment of the present invention. 5A to 5C illustrate schematic cross-sectional views of various partition structures according to embodiments of the present invention. 6A to 6F show perspective views and cross-sectional views of respective partial areas in FIG. 3F and FIG. 7B . FIG. 7A shows a top view of multiple blocks of a memory device according to another embodiment of the present invention. FIG. 7B shows a top view of multiple blocks of a memory device according to yet another embodiment of the present invention. FIG. 8 shows a top view of a memory chip according to another embodiment of the present invention.

99D: area

103: conductor layer

103s1, 103s2, 105s1, 105s2, SW2, SW3: side wall

105: Dielectric layer

SLT1: The first dividing wall

P2: Second Partition

SR: step area

ER: marginal region

T1, T2: block element

Claims (18)

A memory element, comprising: a dielectric substrate; a conductor layer located on the dielectric substrate; a gate stack structure located on the first part of the conductor layer; a dielectric layer located on the gate stack structure and the second On the conductive layer of two parts; a plurality of annular partition walls continuously extending through the dielectric layer, the gate stack structure and the conductive layer to define a plurality of block elements; and a plurality of inner partitions a wall disposed within each of the plurality of annular partition walls, extending continuously through the dielectric layer, the gate stack structure, and the conductor layer, wherein the plurality of inner partition walls define each block A plurality of blocks; wherein the plurality of internal partition walls and the plurality of annular partition walls have the same height. The memory device according to claim 1, wherein the plurality of annular partition walls are arranged in an array. The memory device according to claim 1 further includes: at least one dummy partition wall disposed between two adjacent annular partition walls. The memory device according to claim 1, wherein the height of the inner partition wall and the plurality of annular partition walls is greater than the height of the conductor layer, and greater than the height of the gate stack structure. A memory element, comprising: a substrate including an array area, a step area and an edge area, wherein the edge area surrounds The stepped area, and the stepped area surrounds the array area; the interconnection structure is located on the base of the array area and the stepped area; a conductor layer is located in the array area, the stepped area region and the interconnection structure of the edge region; a gate stack structure located on the conductor layer of the array region and the step region, wherein the gate stack structure in the step region having a stepped structure; a dielectric layer located on the conductor layer of the edge region and the stepped structure of the stepped region; and a separation structure continuously extending through the gate stack structure of the array region and the stepped region , the ladder structure and the conductor layer to define a block and form a plurality of blocks in the block. The memory device according to claim 5, wherein the sidewalls of the separation structure are in contact with the sidewalls of the conductive layer and the dielectric layer. The memory device according to claim 5, wherein the separation structure includes: an outer separation wall, the gate stack structure and the conductor layer extending continuously through the array region and the step region, to define the block element; and a plurality of inner partition walls, arranged in the outer partition walls, extending in a first direction and continuously passing through the gate stack structure and the conductor layer of the array region, to define out of the multiple blocks. The memory element as claimed in item 5, wherein the outer partition wall comprises: a plurality of first partitions extending in the first direction, wherein at least one of the plurality of first partitions continuously passes through the gate stack structure in the array region and the stepped region, the dielectric layer and the conductive layer; and a plurality of second partitions extending in a second direction and continuously passing through the dielectric layer and the conductive layer in the edge region. The memory device according to claim 8, wherein each of the plurality of first partitions passes through the gate stack structure in the array area and the stepped area, the dielectric layer, and the conductor layer. The memory device according to claim 8, wherein another one of the plurality of first partitions is disposed on the periphery of the stepped structure, and continuously extends through the dielectric layer and the edge region in the edge region. the conductor layer. The memory device according to claim 5, further comprising: at least one dummy partition extending in the second direction, disposed beside the second partition and extending through the dielectric layer of the edge region with the conductor layer. A method for manufacturing a memory element, comprising: providing a dielectric substrate; forming a blanket conductor layer to cover the dielectric substrate; forming a gate stack structure on the blanket conductor layer; forming a plurality of A channel opening is in the gate stack structure, wherein the channel opening exposes the blanket conductor layer; a channel column is formed in each channel opening; forming a charge storage structure between the channel column and a plurality of gate conductor layers of the gate stack structure; forming a dielectric layer on the gate stack structure and the blanket conductor layer; and forming multiple A separation structure continuously extends through the dielectric layer, the gate stack structure and the blanket conductor layer to define a plurality of blocks, and each block defines a plurality of blocks. The method for manufacturing a memory element according to claim 12, wherein forming the plurality of partition structures includes: forming a plurality of first partition walls extending through the dielectric layer, the gate stack structure and the a blanket conductor layer defining the plurality of blocks; and forming a plurality of second partition walls extending through the dielectric layer, the gate stack structure, and the blanket conductor layer to define the plurality of blocks; Each of the blocks defines the plurality of blocks. The method for manufacturing a memory element according to claim 13, wherein forming the plurality of separation structures includes: forming a plurality of first separation trenches and a plurality of second separation trenches, extending through the dielectric layer, the a gate stack structure and the blanket conductor layer; and filling an insulating material in the plurality of first separation trenches and the plurality of separation trenches. The method of manufacturing a memory device as claimed in claim 14, wherein the insulating material fills up the plurality of first separation trenches and the plurality of second separation trenches. The method for manufacturing a memory device according to claim 14, wherein the insulating material does not fill the plurality of first separation trenches and the plurality of second separation trenches, and has air gaps located in the insulating material . The method for manufacturing a memory device according to claim 14, wherein the insulating material includes a liner covering the sidewalls of the plurality of annular separation trenches and the inner separation trenches, and forming the plurality of separation structures further includes An empty space between the conductive material and the liner is formed. The method for manufacturing a memory device according to claim 12, wherein the method for forming the plurality of channel openings includes performing plasma etching, and using the blanket conductor layer as a discharge path.

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