Nothing Special   »   [go: up one dir, main page]

TW202412246A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TW202412246A
TW202412246A TW111133425A TW111133425A TW202412246A TW 202412246 A TW202412246 A TW 202412246A TW 111133425 A TW111133425 A TW 111133425A TW 111133425 A TW111133425 A TW 111133425A TW 202412246 A TW202412246 A TW 202412246A
Authority
TW
Taiwan
Prior art keywords
grid structure
electrode pads
electronic package
electronic
circuit
Prior art date
Application number
TW111133425A
Other languages
English (en)
Other versions
TWI815639B (zh
Inventor
林河全
賴佳助
莊明翰
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111133425A priority Critical patent/TWI815639B/zh
Priority to CN202211115371.5A priority patent/CN117690912A/zh
Priority to US18/056,078 priority patent/US20240079301A1/en
Application granted granted Critical
Publication of TWI815639B publication Critical patent/TWI815639B/zh
Publication of TW202412246A publication Critical patent/TW202412246A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種電子封裝件，其係於線路結構與電子元件之間配置網格結構，以增加電流之分流路徑，使該電子元件作為電源接點之電極墊，其電流可經由該網格結構而通過該線路結構之導電片進行傳遞，故能減少電源損耗，使該電子元件之電壓降符合需求。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種提升可靠性之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足電子封裝件微型化(miniaturization)的封裝需求，係發展出嵌埋型封裝的技術。
圖1係為習知半導體封裝件1之剖面示意圖。如圖1所示，將半導體元件12嵌埋於一封裝層13中。接著，形成一線路結構14於該封裝層13與該半導體元件12之作用面12a上，令該線路結構14電性連接該半導體元件12之電極墊120。之後，形成一絕緣保護層15於該線路結構14上，且該絕緣保護層15外露該線路結構14之部分表面，以供結合如銲球之導電元件16。
惟，習知半導體封裝件1中，該線路結構14之線路係採用銅材，故當該線路結構14朝薄化設計而使其線路之厚度極薄時，該半導體元件12之電極墊120於連接該線路結構14之線路後，作為電源之電極墊120將損耗極大，使其電壓降(IR drop)不符合需求。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：線路結構，係定義有相對之第一側與第二側，其中，該線路結構於其第一側係配置導電片及與該導電片相互間隔之線路層；一電子元件，係設於該線路結構之第一側，其中，該電子元件係具有複數電極墊，以令該複數電極墊之至少一者電性連接該線路層；以及網格結構，係設於該電子元件與該線路結構之第一側之間，且令該網格結構電性連接該導電片與該複數電極墊之至少另一者，其中，該網格結構係具有複數相互交錯之條狀體，以於對應該複數電極墊處形成複數網孔。
本發明亦提供一種電子封裝件之製法，係包括：提供一線路結構，該線路結構係定義有相對之第一側與第二側，且該線路結構於其第一側係配置導電片及與該導電片相互間隔之線路層；將一具有複數電極墊之電子元件設於該線路結構之第一側，以令該複數電極墊之至少一者電性連接該線路層；以及將網格結構設於該電子元件與該線路結構之第一側之間，以令該網格結構電性連接該導電片與該複數電極墊之至少另一者，其中，該網格結構係具有複數相互交錯之條狀體，以於對應該複數電極墊處形成複數網孔。
前述之電子封裝件及其製法中，該複數電極墊之至少一者作為訊號接點，而該複數電極墊之至少另一者作為電源接點。
前述之電子封裝件及其製法中，該複數電極墊上係形成有導電凸塊，以令其中一部分該導電凸塊電性連接該線路層，而另一部分該導電凸塊電性 連接該導電片。進一步，可於該電子元件上配置該網格結構與一保護層，使該保護層覆蓋該網格結構、該複數電極墊與複數該導電凸塊。例如，該網格結構與該導電凸塊係共平面。或者，該條狀體之寬度係大於該導電凸塊之端面的最大直徑。
前述之電子封裝件及其製法中，該條狀體之寬度係至少為10微米。
前述之電子封裝件及其製法中，該網格結構係為金屬網格。
前述之電子封裝件及其製法中，復包括：將網格結構設於該電子元件上；藉由封裝層包覆該電子元件與該網格結構，以令該電子元件嵌埋於該封裝層中；以及形成該線路結構於該封裝層上。
前述之電子封裝件及其製法中，復包括：將該網格結構設於該線路結構上；將該電子元件以覆晶方式設於該線路結構與該網格結構上；以及於該電子元件與該線路結構之間形成封裝層，以令該封裝層包覆該網格結構。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該網格結構設於該電子元件與該線路結構之間，以增加電流之分流路徑，故相較於習知技術，本發明之電子封裝件中，作為電源接點之電極墊之電流可經由該網格結構與該導電凸塊所構成之導電區域而通過該導電片以傳遞至該線路結構之第二側，因而能減少電源損耗，使該電子元件之電壓降(IR drop)符合需求。
1:半導體封裝件
12:半導體元件
12a,22a:作用面
120,220,220a:電極墊
13,23,33:封裝層
14,24:線路結構
15:絕緣保護層
16,25:導電元件
2,3:電子封裝件
20:承載件
200:離形層
21:網格結構
21a:條狀體
210:網孔
22:電子元件
22b:非作用面
221,221a:導電凸塊
222:保護層
24a:第一側
24b:第二側
240:介電層
241:線路層
242:電性接觸墊
243:導電片
d:寬度
r:最大直徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2D係為本發明之電子封裝件之第一實施例之製法之剖視示意圖。
圖3A至圖3B係為本發明之電子封裝件之第二實施例之製法之剖視示意圖。
圖4係為本發明之電子封裝件之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2D係為本發明之電子封裝件2之第一實施例之製法的剖面示意圖。於本實施例中，該電子封裝件係採用晶圓級封裝(Wafer Level Packaging)規格。
如圖2A所示，提供一具有離形層200之承載件20，且將一設有網格結構21之電子元件22設於該離形層200上。
於本實施例中，該承載件20例如為半導體材質(如矽或玻璃)之板體，其上形成有該離形層200。
再者，該電子元件22係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件22係為主動元件，其具有相對之作用面22a及非作用面22b，並以其非作用面22b設置於該離形層200上，且該作用面22a具有複數電極墊220,220a，以於該電極墊220,220a上形成如銅柱或錫球之導電凸塊221,221a，並於該作用面22a上設有該網格結構21與一保護層222，使該保護層222覆蓋該網格結構21、該些電極墊220,220a與該些導電凸塊221,221a，其中，部分該電極墊220作為電源接點，而部分電極墊220a作為訊號接點。
進一步，該導電凸塊221,221a與該網格結構21可外露於該保護層222。例如，該保護層222係為非導電膜(Non-Conductive Film，簡稱NCF)，可藉由整平製程，如蝕刻或研磨方式，移除該保護層222之部分材質，以令該導電凸塊221,221a之端面、該網格結構21之上表面與該保護層222之上表面齊平。
又，該網格結構21係為金屬網格，其具有複數相互交錯之條狀體21a，以於對應該電極墊220a處形成網孔210(如圖4所示之彎曲溝狀)，使連接該訊號接點(電極墊220a)之導電凸塊221a位於該網孔210中，而連接該電源接點(電極墊220)之導電凸塊221係連接該網格結構21之條狀體21a(如圖4所示)，並使該保護層222填充該網孔210剩餘空間。例如，可藉由電鍍製程，同時製作該網格結構21與該些導電凸塊221,221a，使該網格結構21與該些導電凸塊221,221a係等高，即兩者共平面。然而，於其它實施例中，該些導電凸塊221,221a亦可高於該網格結構21，使該些導電凸塊221,221a凸出該網格結構21。
另外，該網格結構21之條狀體21a之寬度d係大於該導電凸塊221,221a之端面的最大直徑r，如圖4所示。例如，該網格結構21之條狀體21a之寬度d係至少為10微米(um)。
如圖2B所示，形成一封裝層23於該承載件20上，以令該封裝層23包覆該電子元件22及該保護層222。
於本實施例中，形成該封裝層23之材質係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載件20上。
再者，可藉由整平製程，如研磨方式，移除該封裝層23之部分材質，甚至移除該保護層222及/或導電凸塊221,221a之部分材質，使該封裝層23之上表面齊平該保護層222之上表面，以令該電子元件22上之導電凸塊221,221a外露出該封裝層23。
如圖2C所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，以形成一線路結構24於該封裝層23與該電子元件22上，且該線路結構24電性連接該電子元件22與該網格結構21。
於本實施例中，該線路結構24係包含至少一介電層240、及設於該介電層240上且電性連接該導電凸塊221a之線路層241，且於最外側之線路層241上具有電性接觸墊242，以結合如銲錫材料之導電元件25。例如，形成該線路層241之材質係為銅，且形成該介電層240之材質係為如ABF(Ajinomoto Build-up Film)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它介電材或如綠漆、石墨之防銲材。
再者，該線路結構24係定義有相對之第一側24a與第二側24b，且以其第一側24a結合至該封裝層23上，並使該些導電元件25設於該第二側 24b之電性接觸墊242上。例如，該線路結構24於其第一側24a係具有一接觸部分該導電凸塊221與網格結構21之導電片243，其與該第一側24a之線路層241相互間隔，以令該導電片243電性連接該網格結構21與該作為電源接點之電極墊220上之導電凸塊221，且該第一側24a之線路層241電性連接該作為訊號接點之電極墊220a上之導電凸塊221a。
如圖2D所示，移除該承載件20與該離形層200，以外露該封裝層23與該電子元件22之非作用面22b，而製得本發明之電子封裝件2。
於本實施例中，該封裝層23之外露表面係齊平該電子元件22之非作用面22b，使該電子元件22之非作用面22b外露於該封裝層23，供該電子元件22散熱。
再者，該電子封裝件2可藉由該些導電元件25接置至少一如封裝模組、電路板、晶片或其它之電子裝置。
因此，本發明之製法係藉由該網格結構21之設計以增加電流之分流路徑，故相較於習知技術，即使該線路結構24朝薄化設計而使其線路層241與導電片243之厚度極薄，該電子元件22於結合該線路結構24後，該作為電源接點之電極墊220之電流可經由該網格結構21與該導電凸塊221所構成之導電區域而通過該導電片243以傳遞至該第二側24b之導電元件25，因而能減少電源損耗，使該電子元件21之電壓降(IR drop)符合需求。
再者，該網格結構21之佈設面積越大(或該條狀體21a之寬度d越厚)，則減少電源損耗之效果越好。例如，當該條狀體21a之寬度d大於或等於10微米(um)時，該電子元件21之電壓降可由19.41(無該網格結構21之情況下)降低至14.09，約降低25%。
圖3A至圖3B係為本發明之電子封裝件3之第二實施例之製法的剖面示意圖。本實施例與第一實施例之差異在於封裝形式，其它設計大致相同，故以下不再贅述相同處。於本實施例中，該電子封裝件3係採用覆晶封裝規格。
如圖3A所示，於線路結構24之第一側24a上形成一網格結構21及複數導電凸塊221,221a。
於本實施例中，該線路結構24係為載板形式，如具有核心層之封裝基板(substrate)或無核心層(coreless)式封裝基板。然而，有關該線路結構24之種類繁多，只需可供承載如晶片等電子元件之載板即可，如矽中介板(interposer)，並無特別限制。
再者，可藉由電鍍製程，於該線路結構24之第一側24a之表面上同時製作該網格結構21與該些導電凸塊221,221a，且該線路結構24之第一側24a佈設有導電片243。
如圖3B所示，將電子元件22藉由覆晶方式以其電極墊220,220a結合至該些導電凸塊221,221a上，使該網格結構21位於該電子元件22與該線路結構24之第一側24a之間。之後，形成一如底膠之封裝層33於該電子元件22與該線路結構24之第一側24a之間，以令該封裝層33包覆該網格結構21與該些導電凸塊221,221a。
於本實施例中，可於該線路結構24之第二側24b配置該些導電元件25。
因此，本發明之製法係藉由該網格結構21之設計以增加電流之分流路徑，故相較於習知技術，該電子元件22於結合該線路結構24後，該作為電源接點之電極墊220之電流可經由該網格結構21與該導電凸塊221所構成之 導電區域而通過該導電片243以傳遞至該第二側20b之導電元件25，因而能減少電源損耗，使該電子元件21之電壓降(IR drop)符合需求。
本發明復提供一種電子封裝件2,3，其包括：一線路結構24、至少一電子元件22、以及一網格結構21。
所述之線路結構24係定義有相對之第一側24a與第二側24b，其中，該線路結構24於其第一側24a係配置導電片243及與該導電片243相互間隔之線路層241。
所述之電子元件22係設於該線路結構24之第一側24a，其中，該電子元件22係具有複數電極墊220,220a，且令該複數電極墊220a之至少一者電性連接該線路層241。
所述之網格結構21係設於該電子元件22與該線路結構24之第一側24a之間，以電性連接該導電片243與該複數電極墊220之至少另一者，其中，該網格結構21係具有複數相互交錯之條狀體21a，以於對應部分該電極墊220a處形成網孔210。
於一實施例中，該複數電極墊220a之至少一者作為訊號接點，而該複數電極墊220之至少另一者作為電源接點。
於一實施例中，該複數電極墊220,220a上係形成有導電凸塊221,221a，以令其中一部分該導電凸塊221a電性連接該線路層241，而另一部分該導電凸塊221電性連接該導電片243。進一步，該電子元件22上設有該網格結構21與一保護層222，使該保護層222覆蓋該網格結構21、該複數電極墊220,220a與複數該導電凸塊221,221a。例如，該網格結構21與該導電凸塊221,221a係共平面。或者，該條狀體21a之寬度d係大於該導電凸塊221,221a之端面的最大直徑r。
於一實施例中，該條狀體21a之寬度d係至少為10微米。
於一實施例中，該網格結構21係為金屬網格。
於一實施例中，所述之電子封裝件2復包括結合該線路結構24之封裝層23，以令該電子元件22嵌埋於該封裝層23中。
於一實施例中，所述之電子封裝件2復包括設於該電子元件22與該線路結構24之間以包覆該網格結構21之封裝層33。
綜上所述，本發明之電子封裝件及其製法，係藉由該網格結構之設計增加電流之分流路徑，使本發明之電子封裝件中，作為電源接點之電極墊之電流可經由該網格結構與該導電凸塊而通過該導電片以傳遞至該線路結構之第二側，因而能減少電源損耗，使該電子元件之電壓降(IR drop)符合需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
21:網格結構
22:電子元件
22a:作用面
22b:非作用面
220,220a:電極墊
221,221a:導電凸塊
222:保護層
23:封裝層
24:線路結構
24a:第一側
24b:第二側
241:線路層
243:導電片
25:導電元件

Claims (20)

  1. 一種電子封裝件，係包括：
    線路結構，係定義有相對之第一側與第二側，其中，該線路結構於其第一側係配置導電片及與該導電片相互間隔之線路層；
    電子元件，係設於該線路結構之第一側，其中，該電子元件係具有複數電極墊，以令該複數電極墊之至少一者電性連接該線路層；以及
    網格結構，係設於該電子元件與該線路結構之第一側之間，且令該網格結構電性連接該導電片與該複數電極墊之至少另一者，其中，該網格結構係具有複數相互交錯之條狀體，以於對應該複數電極墊處形成複數網孔。
  2. 如請求項1所述之電子封裝件，其中，該複數電極墊之至少一者作為訊號接點，而該複數電極墊之至少另一者作為電源接點。
  3. 如請求項1所述之電子封裝件，其中，該複數電極墊上係形成有複數導電凸塊，以令其中一部分該複數導電凸塊電性連接該線路層，而另一部分該複數導電凸塊電性連接該導電片。
  4. 如請求項3所述之電子封裝件，其中，該電子元件上設有該網格結構與一保護層，使該保護層覆蓋該網格結構、該複數電極墊與該複數導電凸塊。
  5. 如請求項3所述之電子封裝件，其中，該網格結構與各該複數導電凸塊係共平面。
  6. 如請求項3所述之電子封裝件，其中，各該條狀體之寬度係大於各該複數導電凸塊之端面的最大直徑。
  7. 如請求項1所述之電子封裝件，其中，各該條狀體之寬度係至少為10微米。
  8. 如請求項1所述之電子封裝件，其中，該網格結構係為金屬網格。
  9. 如請求項1所述之電子封裝件，復包括結合該線路結構之封裝層，以令該電子元件嵌埋於該封裝層中。
  10. 如請求項1所述之電子封裝件，復包括設於該電子元件與該線路結構之間以包覆該網格結構之封裝層。
  11. 一種電子封裝件之製法，係包括：
    提供一線路結構，該線路結構係定義有相對之第一側與第二側，且該線路結構於其第一側係配置導電片及與該導電片相互間隔之線路層；
    將一具有複數電極墊之電子元件設於該線路結構之第一側，以令該複數電極墊之至少一者電性連接該線路層；以及
    將網格結構設於該電子元件與該線路結構之第一側之間，且令該網格結構電性連接該導電片與該複數電極墊之至少另一者，其中，該網格結構係具有複數相互交錯之條狀體，以於對應該複數電極墊處形成複數網孔。
  12. 如請求項11所述之電子封裝件之製法，其中，該複數電極墊之至少一者作為訊號接點，而該複數電極墊之至少另一者作為電源接點。
  13. 如請求項11所述之電子封裝件之製法，其中，該複數電極墊上係形成有複數導電凸塊，以令其中一部分該複數導電凸塊電性連接該線路層，而另一部分該複數導電凸塊電性連接該導電片。
  14. 如請求項13所述之電子封裝件之製法，復包括於該電子元件上配置該網格結構與一保護層，使該保護層覆蓋該網格結構、該複數電極墊與該複數導電凸塊。
  15. 如請求項13所述之電子封裝件之製法，其中，該網格結構與各該複數導電凸塊係共平面。
  16. 如請求項13所述之電子封裝件之製法，其中，各該條狀體之寬度係大於各該複數導電凸塊之端面的最大直徑。
  17. 如請求項11所述之電子封裝件之製法，其中，各該條狀體之寬度係至少為10微米。
  18. 如請求項11所述之電子封裝件之製法，其中，該網格結構係為金屬網格。
  19. 如請求項11所述之電子封裝件之製法，復包括：
    將網格結構設於該電子元件上；
    藉由封裝層包覆該電子元件與該網格結構，以令該電子元件嵌埋於該封裝層中；以及
    形成該線路結構於該封裝層上。
  20. 如請求項11所述之電子封裝件之製法，復包括：
    將該網格結構設於該線路結構上；
    將該電子元件以覆晶方式設於該線路結構與該網格結構上；以及
    於該電子元件與該線路結構之間形成封裝層，以令該封裝層包覆該網格結構。
TW111133425A 2022-09-02 2022-09-02 電子封裝件及其製法 TWI815639B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW111133425A TWI815639B (zh) 2022-09-02 2022-09-02 電子封裝件及其製法
CN202211115371.5A CN117690912A (zh) 2022-09-02 2022-09-14 电子封装件及其制法
US18/056,078 US20240079301A1 (en) 2022-09-02 2022-11-16 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111133425A TWI815639B (zh) 2022-09-02 2022-09-02 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TWI815639B TWI815639B (zh) 2023-09-11
TW202412246A true TW202412246A (zh) 2024-03-16

Family

ID=88966185

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111133425A TWI815639B (zh) 2022-09-02 2022-09-02 電子封裝件及其製法

Country Status (3)

Country Link
US (1) US20240079301A1 (zh)
CN (1) CN117690912A (zh)
TW (1) TWI815639B (zh)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5872766B2 (ja) * 2010-12-10 2016-03-01 ローム株式会社 半導体装置および半導体パッケージ
WO2015092579A1 (en) * 2013-12-18 2015-06-25 Koninklijke Philips N.V. Reflective solder mask layer for led phosphor package
KR101933423B1 (ko) * 2017-11-28 2018-12-28 삼성전기 주식회사 팬-아웃 센서 패키지
CN109980070B (zh) * 2017-12-22 2024-03-19 海迪科（南通）光电科技有限公司 一种晶圆级芯片级csp封装结构及其制备方法
US10950738B2 (en) * 2018-08-02 2021-03-16 Xintec Inc. Chip package and method for forming the same
KR102722905B1 (ko) * 2019-07-25 2024-10-30 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR20220041430A (ko) * 2020-09-25 2022-04-01 삼성전자주식회사 Ubm층을 가지는 팬 아웃 반도체 패키지
TW202220139A (zh) * 2020-11-12 2022-05-16 矽品精密工業股份有限公司 電子封裝件及其線路結構
TWI734651B (zh) * 2020-11-27 2021-07-21 矽品精密工業股份有限公司 電子封裝件及其製法

Also Published As

Publication number Publication date
TWI815639B (zh) 2023-09-11
US20240079301A1 (en) 2024-03-07
CN117690912A (zh) 2024-03-12

Similar Documents

Publication Publication Date Title
TWI645527B (zh) 電子封裝件及其製法
TWI418003B (zh) 嵌埋電子元件之封裝結構及其製法
US9754868B2 (en) Substrate structure, electronic package and method for fabricating the electronic package
US20190043819A1 (en) Electronic package having redistribution structure
TWI728936B (zh) 電子封裝件及其製法
TW202101713A (zh) 電子封裝件及其製法
TWI649839B (zh) 電子封裝件及其基板構造
US12107055B2 (en) Electronic package and fabrication method thereof
US20240162169A1 (en) Electronic package and fabrication method thereof
CN114121869A (zh) 电子封装件及其制法
CN107403785B (zh) 电子封装件及其制法
TWI832571B (zh) 電子封裝件及其製法
US20120299177A1 (en) Semiconductor component and method of fabricating the same
US20120211257A1 (en) Pyramid bump structure
CN109427725B (zh) 中介基板及其制法
TW202046456A (zh) 電子封裝件及其製法
TWI815639B (zh) 電子封裝件及其製法
CN111490025B (zh) 电子封装件及其封装基板与制法
CN114496973A (zh) 电子封装件及其线路结构
TWI849757B (zh) 電子封裝件及其封裝基板與製法
TWI839645B (zh) 電子封裝件及其製法
TWI804411B (zh) 電子封裝件及其製法
TWI809787B (zh) 電子封裝件及其製法
TWI819440B (zh) 電子封裝件及其製法
CN107871724B (zh) 基板结构及其制法