TW202037049A - Time signal generator - Google Patents

Abstract

A time signal generator generating a time signal for a DC-DC conversion circuit to convert an input voltage into an output voltage is disclosed. The DC-DC conversion circuit is coupled to a loading and a loading current flowing through the loading. The time signal generator includes an analog-to-digital converting unit, a compensation unit, a counting unit, a comparing unit and a logic unit. The analog-to-digital converting unit receives an output voltage, an input voltage and the loading current and converts them into corresponding digital signals. The compensation unit receives the digital signals and processes the digital signals to generate a compensation signal. The counting unit provides a counting signal according to a clock signal and a trigger signal. The comparing unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide the time signal.

Description

Time signal generator

The invention relates to a DC-to-DC conversion circuit, and particularly relates to a time signal generator applied in a DC-to-DC conversion circuit.

When a DC-to-DC conversion circuit with a constant on-time is operating in a heavy-load steady state, since its on-time is constant, in order to offset the power conversion loss caused by the parasitic resistance of the components in the circuit, the off time of the time signal provided by it will be changed. Shorten (as shown in Figure 1A, the length of the turn-off time is shortened from TOFF1 to TOFF2), the switching cycle becomes shorter, and the average value of the inductor current through the output inductor will become larger (the inductor current in Figure 1B is changed from Iind1 becomes as Iind2).

However, the shortening of the period of the time signal represents an increase in the switching frequency of the output stage of the DC-to-DC conversion circuit, resulting in poor power conversion efficiency when the DC-to-DC conversion circuit operates in a heavy load steady state. This shortcoming needs to be overcome.

In view of this, the present invention provides a time signal generator to solve the problems mentioned in the prior art.

A preferred embodiment of the present invention is a time signal generator. In this embodiment, the time signal generator generates a time signal to enable the DC-to-DC conversion circuit to convert the input voltage to the output voltage. The DC to DC conversion circuit is coupled to the load, and a load current flows through the load. The time signal generator includes an analog-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-digital conversion unit receives the output voltage, the input voltage and the load current respectively, and respectively converts them into a digital input voltage signal, a digital output voltage signal and a digital load current signal. The compensation unit receives the digital output voltage signal, the digital input voltage signal and the digital load current signal respectively, and performs arithmetic processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate the compensation signal. The counting unit provides a counting signal according to the clock signal and the trigger signal. The comparison unit receives the compensation signal and the count signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide a time signal.

In an embodiment of the present invention, the time signal is related to the digital input voltage signal, the digital output voltage signal, and the digital load current signal.

In an embodiment of the present invention, during heavy load, the load current passing through the load increases, causing the digital load current signal related to the load current to increase. The compensation signal generated by the compensation unit and the comparison signal provided by the comparison unit also increase accordingly.

In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, an adder, and a divider. The first multiplier is used to multiply the digital load current signal by a first constant to obtain a first product. The second multiplier is used to multiply the digital input voltage signal by a second constant to obtain a second product. The adder is coupled to the first multiplier for adding the first product to the digital output voltage signal to obtain the sum value. The divider is coupled to the adder and the second multiplier, and is used to divide the sum value by the second product to obtain a compensation signal.

In an embodiment of the present invention, the time signal also increases with the total value, and the increase of the time signal is related to the increase of the digital load current signal.

In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, a first divider, a second divider, and an adder. The first multiplier is used to multiply the digital load current signal by a first constant to obtain a first product. The second multiplier is used to multiply the digital input voltage signal by a second constant to obtain a second product. The first divider is coupled to the first multiplier and the second multiplier for dividing the load current signal by the second product to obtain the first quotient. The second divider is coupled to the second multiplier for dividing the digital output voltage by the second product to obtain the second quotient value. The adder is coupled to the first divider and the second divider for adding the first quotient value and the second quotient value to obtain a compensation signal.

Compared with the prior art, the time signal generator of the present invention can adjust the time signal provided by the compensation signal related to the load current. Therefore, when the DC-to-DC conversion circuit operates in a heavy load steady state, the load current increases At the same time, the on-time of the time signal provided by the time signal of the time signal generator of the present invention is also increased, so as to maintain the constant switching frequency of the DC-to-DC conversion circuit and improve the operation of the DC-to-DC conversion circuit under heavy load and steady state. Power conversion efficiency.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Reference will now be made in detail to exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Elements/components with the same or similar numbers used in the drawings and embodiments are used to represent the same or similar parts.

A preferred embodiment according to the present invention is a time signal generator. In this embodiment, the time signal generator is applied to the DC-DC conversion circuit to generate the time signal.

Please refer to FIG. 2. FIG. 2 illustrates a schematic diagram of the time signal generator in this embodiment applied to a DC-DC conversion circuit. As shown in FIG. 2, the DC to DC conversion circuit 2 is coupled to the load LD and a load current _IL flows through the load LD. During heavy load, the load current _IL through the load LD will increase.

The DC-DC conversion circuit 2 includes a time signal generator 1, a driving circuit DR, an output stage OS and a feedback circuit FB. The time signal generator 1 is coupled to the driving circuit DR and the feedback circuit FB. The driving circuit DR is coupled to the time signal generator 1 and the output stage OS. The output stage OS is coupled to the input voltage Vin, the ground voltage GND, the driving circuit DR, the feedback circuit FB and the load LD, and generates an output voltage Vout. The feedback circuit FB is coupled to the output voltage Vout and the time signal generator 1.

The time signal generator 1 respectively receives the input voltage Vin, the output voltage Vout, the load current IL, the clock signal CLK and the trigger signal TR, and provides the time signal Ton to the driving circuit DR. The driving circuit DR generates the first driving signal DS1 and the second driving signal DS2 to the output stage OS according to the time signal Ton. The output stage OS is driven by the first driving signal DS1 and the second driving signal DS2 to generate an output voltage Vout. The feedback circuit FB generates a trigger signal TR to the time signal generator 1 according to the output voltage Vout.

In practical applications, the output stage OS includes a first switch and a second switch connected in series between the input voltage Vin and the ground voltage GND, which are driven by the first drive signal D1 and the second drive signal D2, respectively, and are connected between the first switch and the second switch. The inductor current Iind is output between the second switches and an output voltage Vout is generated.

Please refer to FIG. 3, which is a functional block diagram of the time signal generator 1 in FIG. As shown in FIG. 3, the time signal generator 1 includes an analog-to-digital conversion unit 10, a compensation unit 11, a counting unit 12, a comparison unit 14 and a logic unit 16. The analog-to-digital conversion unit 10 is coupled to the compensation unit 11. Both the compensation unit 11 and the counting unit 12 are coupled to the comparison unit 14. The comparison unit 14 is coupled to the logic unit 16.

The analog-to-digital conversion unit 10 receives the output voltage Vout, the input voltage Vin, and the load current IL respectively, and converts them into a digital output voltage signal SVout, a digital input voltage signal SVin, and a digital load current signal SIL, respectively, and then provides them to the compensation unit 11.

The compensation unit 11 receives the digital output voltage signal SVout, the digital input voltage signal SVin, and the digital load current signal SIL, respectively, and processes the digital output voltage signal SVout, the digital input voltage signal SVin, and the digital load current signal SIL to generate a compensation signal S1 . The counting unit 12 provides the counting signal S2 according to the clock signal CLK and the trigger signal TR.

The comparing unit 14 receives the compensation signal S1 from the compensation unit 11 and the counting signal S2 from the counting unit 12 respectively, and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the counting signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3 respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.

In practical applications, the time signal Ton provided by the logic unit 16 of the time signal generator 1 is related to the digital input voltage signal SVin, the digital output voltage signal SVout, and the digital load current signal SIL, but not limited to this.

During the light load period, the compensation value caused by the load current IL is omitted, and the time signal Ton provided by the logic unit 16 remains unchanged. During the heavy load period, the load current IL passing through the load LD increases, causing the digital load current signal SIL related to the load current IL to increase, and the compensation unit 11 generates the compensation signal S1 according to the digital load current signal SIL and the comparison unit 14 according to the compensation The comparison signal S3 provided by the signal S1 will also increase, so that the time signal Ton provided by the logic unit 16 will also increase with the comparison signal S3 and the increase in the time signal Ton will be related to the increase in the digital load current signal SIL, but Not limited to this.

Please refer to FIG. 4A. FIG. 4A shows an embodiment of a digital time signal generator. As shown in FIG. 4A, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison unit 14, and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, an adder ADD, and a divider DIV. The adder ADD is coupled to the first multiplier M1. The divider DIV is coupled to the adder ADD and the second multiplier M2.

The first multiplier M1 is used to multiply the digital load current signal SIL by a first constant ki to obtain a first product (ki*SIL). The second multiplier M2 is used to multiply the digital input voltage signal SVin by a second constant kv to obtain a second product (kv*SVin). The adder ADD is used to add the digital output voltage signal SVout to the first product ki*SIL to obtain the sum value SUM=(SVout+ki*SIL). The divider DIV is used to divide the sum value SUM by the second product (kv*SVin) to obtain the compensation signal S1, that is, the compensation signal S1=(SVout+ki*SIL)/(kv*SVin).

The counting unit 12 provides the counting signal S2 according to the clock signal CLK and the trigger signal TR. The comparing unit 14 receives the compensation signal S1 from the compensation unit 11 and the counting signal S2 from the counting unit 12 respectively, and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the counting signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3 respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.

It should be noted that the digital output voltage signal SVout, digital input voltage signal SVin, and digital load current signal SIL provided to the compensation unit 11 can be obtained by converting the output voltage Vout, input voltage Vin, and load current IL by the analog-digital conversion unit 10, respectively. But not limited to this.

Please refer to FIG. 4B. FIG. 4B shows another embodiment of a digital time signal generator. As shown in FIG. 4B, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison unit 14, and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, a first divider DIV1, a second divider DIV2, and an adder ADD. The first multiplier M1 is coupled to the first divider DIV1. The second multiplier M2 is coupled to the divider DIV and coupled to the first divider DIV1 and the second divider DIV2. The first divider DIV1 and the second divider DIV2 are both coupled to the adder ADD.

The first multiplier M1 is used to multiply the digital load current signal SIL by a first constant ki to obtain a first product (ki*SIL). The second multiplier M2 is used to multiply the digital input voltage SVin signal by a second constant kv to obtain a second product (kv*SVin). The first divider DIV1 is used to divide the first product (ki*SIL) by the second product (kv*SVin) to obtain the first quotient value (ki*SIL)/(kv*SVin). The second divider DIV2 is used to divide the digital output voltage signal SVout by the second product (kv*SVin) to obtain the second quotient value SVout/(kv*SVin). The adder ADD is used to add the first quotient value (ki*SIL)/(kv*SVin) and the second quotient value SVout/(kv*SVin) to obtain the compensation signal S1, that is, the compensation signal S1=(SVout+ ki*SIL)/ (kv*SVin).

It should be noted that the digital output voltage signal SVout, digital input voltage signal SVin, and digital load current signal SIL provided to the compensation unit 11 can be obtained by converting the output voltage Vout, input voltage Vin, and load current IL by the analog-digital conversion unit 10, respectively. But not limited to this.

Next, please refer to FIGS. 5A to 5D. 5A and 5B show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under light load and steady state, respectively. 5C and 5D show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under heavy load and steady state, respectively.

As shown in Figures 5A and 5B, in the light-load steady state, due to the characteristics of the digital circuit, small calculation errors (such as the compensation value caused by the load current in the light-load state) will be omitted, so the conventional digital formula The period D1 and on-time length T1 of the time signal Ton1 provided by the time signal generator and the period D2 and on-time length T2 of the time signal Ton2 provided by the digital time signal generator of the present invention remain unchanged, for example, both The period of both is 1000ns and the length of the on-time of both is 300ns.

As shown in FIG. 5C, in the heavy load steady state, the on-time length T1' of the time signal Ton1 provided by the conventional digital time signal generator is still maintained at 300ns, but this also results in the period D1 of the time signal Ton1 'From 1000ns to 860ns, a total of 140ns is shortened, which causes the switching frequency of the conventional DC-to-DC converter circuit to increase and affect its power conversion efficiency.

In contrast, as shown in Figure 5D, in the heavy load steady state, the on-time length T2' of the time signal Ton2 provided by the digital time signal generator of the present invention will change from 300ns to 300ns as the load current increases. 340 ns, and the period D2' of the time signal Ton2 will only change from 1000 ns to 995 ns, which is only shortened by 5 ns in total. Therefore, the present invention can maintain the constant switching frequency of the DC-to-DC converter circuit and improve its power conversion efficiency.

Compared with the prior art, the time signal generator of the present invention can adjust the time signal provided to the driving circuit of the DC-DC conversion circuit by the compensation signal related to the load current. Therefore, when the DC-DC conversion circuit operates When the load current increases due to the heavy load steady state, the on-time in the time signal provided by the time signal generator of the present invention also increases, so as to maintain the constant switching frequency of the DC-DC conversion circuit and increase the DC-DC The conversion efficiency of the power supply when the conversion circuit operates under heavy load and steady state.

Based on the detailed description of the preferred embodiments above, it is hoped that the characteristics and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent application for the present invention.

Ton1, Ton2: Time signal Toff1, Toff2: length of off time Iind1, Iind2: inductor current 2: DC to DC conversion circuit 1: Time signal generator 10: Analog to digital conversion unit 11: Compensation unit 12: Counting unit 14: Comparison unit 16: logic unit DR: drive circuit OS: output stage LD: load FB: feedback circuit CLK: clock signal TR: trigger signal GND: Ground voltage SVout: Digital output voltage signal Vout: output voltage SVin: Digital input voltage signal Vin: input voltage SIL: Digital load current signal IL: Load current S1: Compensation signal S2: counting signal S3: compare signal Ton: Time signal DS1: the first drive signal DS2: second drive signal M1: first multiplier M2: second multiplier DIV: divider DIV1: First divider DIV2: second divider ADD: adder SUM: Sum value T1, T2, T1’, T2’: Length of on-time D1, D2, D1’, D2’: period of time signal

The drawings of the present invention are described as follows: FIG. 1A is a schematic diagram showing that the turn-off time and period of the pulse width modulation signal provided by the conventional DC-to-DC conversion circuit are shortened under heavy load and steady state. FIG. 1B is a schematic diagram showing that the average value of the inductor current of the conventional DC-to-DC conversion circuit becomes larger and its period becomes shorter under heavy load and steady state. FIG. 2 is a schematic diagram of the time signal generator in a preferred embodiment of the present invention applied to a DC-DC conversion circuit. FIG. 3 is a functional block diagram of the time signal generator in FIG. 2. FIG. 4A shows an embodiment of a digital time signal generator. FIG. 4B shows another embodiment of the digital time signal generator. 5A and 5B show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under light load and steady state, respectively. 5C and 5D show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under heavy load and steady state, respectively.

1: Time signal generator

10: Analog to digital conversion unit

11: Compensation unit

12: Counting unit

14: Comparison unit

16: logic unit

CLK: clock signal

TR: trigger signal

SVout: Digital output voltage signal

SVin: Digital input voltage signal

SI _L : Digital load current signal

Vout: output voltage

Vin: input voltage

I _L : Load current

S1: Compensation signal

S2: counting signal

S3: compare signal

Ton: Time signal

Claims (6)

A time signal generator generates a time signal so that a DC-to-DC conversion circuit converts an input voltage into an output voltage. The DC-to-DC conversion circuit is coupled to a load and a load current flows through the load. The signal generator includes: An analog-to-digital conversion unit that receives the output voltage, the input voltage, and the load current respectively, and converts them into a digital output voltage signal, a digital input voltage signal, and a digital load current signal; A compensation unit that receives the digital output voltage signal, the digital input voltage signal, and the digital load current signal, and performs an arithmetic processing on the digital output voltage signal, the digital input voltage signal, and the digital load current signal to generate A compensation signal; A counting unit, which provides a counting signal according to a clock signal and a trigger signal; A comparison unit that receives the compensation signal and the count signal to provide a comparison signal; and A logic unit receives the trigger signal and the comparison signal to provide the time signal. The time signal generator described in item 1 of the scope of patent application, wherein the time signal is related to the digital input voltage signal, the digital output voltage signal, and the digital load current signal. The time signal generator described in the first item of the scope of patent application, wherein during heavy load, the load current flowing through the load increases, causing the digital load current signal related to the load current to increase, and the compensation unit generates The compensation signal and the comparison signal provided by the comparison unit also increase accordingly. The time signal generator described in item 1 of the scope of patent application, wherein the compensation unit includes: A first multiplier for multiplying the digital load current signal by a first constant to obtain a first product; A second multiplier for multiplying the digital input voltage signal by a second constant to obtain a second product; An adder, coupled to the first multiplier, for adding the digital output voltage signal to the first product to obtain a total value; and A divider, coupled to the adder and the second multiplier, is used to divide the sum value by the second product to obtain the compensation signal. For the time signal generator described in item 4 of the scope of patent application, the time signal also increases with the total value, and the increase of the time signal is related to the increase of the digital load current signal. The time signal generator described in item 1 of the scope of patent application, wherein the compensation unit includes: A first multiplier for multiplying the digital load current signal by a first constant to obtain a first product; A second multiplier for multiplying the digital input voltage signal by a second constant to obtain a second product; A first divider, coupled to the first multiplier and the second multiplier, for dividing the load current signal by the second product to obtain a first quotient; A second divider, coupled to the second multiplier, for dividing the digital output voltage by the second product to obtain a second quotient; and An adder, coupled to the first divider and the second divider, is used to add the first quotient value and the second quotient value to obtain the compensation signal.

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