CN111224645B - DC-DC conversion circuit and time signal generator thereof - Google Patents
DC-DC conversion circuit and time signal generator thereof Download PDFInfo
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- CN111224645B CN111224645B CN201811415834.3A CN201811415834A CN111224645B CN 111224645 B CN111224645 B CN 111224645B CN 201811415834 A CN201811415834 A CN 201811415834A CN 111224645 B CN111224645 B CN 111224645B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
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Abstract
The invention discloses a direct current-direct current conversion circuit and a time signal generator thereof. The time signal generator generates a time signal to enable the direct current-direct current conversion circuit to convert an input voltage into an output voltage. The DC-DC conversion circuit is coupled to the load and has a load current flowing through the load. The time signal generator comprises an analog-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-digital conversion unit receives the output voltage, the input voltage and the load current respectively and converts the output voltage, the input voltage and the load current into corresponding digital signals respectively. The compensation unit receives the digital signals and performs operation processing to generate compensation signals. The counting unit provides a counting signal according to the clock signal and the trigger signal. The comparison unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide a time signal. The invention can effectively improve the power conversion efficiency of the DC-DC conversion circuit when the DC-DC conversion circuit operates in a heavy load steady state.
Description
Technical Field
The present invention relates to a dc-dc conversion circuit, and more particularly to a dc-dc conversion circuit and a time signal generator thereof.
Background
When the dc-dc conversion circuit with constant on-time is operating in the heavy-duty steady state, since the on-time is constant, the interval time of the time signal provided for canceling the power conversion loss caused by the parasitic resistance of the device in the circuit is shortened (as shown by shortening the interval time of the off-on-time from TOFF1 to TOFF2 in fig. 1A), the switching period is shortened, and the average value of the inductor current passing through the output inductor is increased (as shown by changing the inductor current from Iind1 to Iind2 in fig. 1B).
However, the period of the time signal is shortened, which means that the switching frequency of the output stage of the dc-dc converter circuit is increased, resulting in a deterioration of the power conversion efficiency of the dc-dc converter circuit when operating in a heavy load steady state.
Disclosure of Invention
The invention provides a direct current-direct current conversion circuit and a time signal generator thereof, which are used for solving the problems described in the prior art.
A preferred embodiment of the present invention is a time signal generator. In this embodiment, the time signal generator generates a time signal to enable the DC-DC conversion circuit to convert the input voltage into the output voltage. The DC-DC conversion circuit is coupled to the load and has a load current flowing through the load. The time signal generator comprises an analog-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-to-digital conversion unit receives the output voltage, the input voltage and the load current respectively and converts the output voltage, the input voltage and the load current into a digital input voltage signal, a digital output voltage signal and a digital load current signal respectively. The compensation unit receives the digital output voltage signal, the digital input voltage signal and the digital load current signal respectively, and performs operation processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal. The counting unit provides a counting signal according to the clock signal and the trigger signal. The comparison unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide the time signal.
In one embodiment of the present invention, the time signal is related to the digital input voltage signal, the digital output voltage signal and the digital load current signal.
In one embodiment of the present invention, during heavy load, the load current flowing through the load increases, causing the digital load current signal associated with the load current to increase. The compensation signal generated by the compensation unit and the comparison signal provided by the comparison unit are increased.
In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, an adder and a divider. The first multiplier is used for multiplying the digital load current signal by a first constant to obtain a first product. The second multiplier multiplies the digital input voltage signal by a second constant to obtain a second product. The adder is coupled to the first multiplier for adding the first product to the digital output voltage signal to obtain a sum. A divider is coupled to the adder and the second multiplier for dividing the sum by the second product to obtain the compensation signal.
In one embodiment of the present invention, the time signal also increases with the sum value, and the increase in the time signal is related to the increase in the digital load current signal.
In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, a first divider, a second divider, and an adder. The first multiplier is used for multiplying the digital load current signal by a first constant to obtain a first product. The second multiplier multiplies the digital input voltage signal by a second constant to obtain a second product. The first divider is coupled to the first multiplier and the second multiplier for dividing the load current signal by the second product to obtain a first quotient. The second divider is coupled to the second multiplier for dividing the digital output voltage by the second product to obtain a second quotient. The adder is coupled to the first divider and the second divider for adding the first quotient and the second quotient to obtain the compensation signal.
Another preferred embodiment of the present invention is a dc-dc conversion circuit. In this embodiment, the dc-dc conversion circuit converts an input voltage into an output voltage. The DC-DC conversion circuit is coupled to the load and has a load current flowing through the load. The DC-DC conversion circuit comprises an output stage, a driving circuit, a feedback circuit and a time signal generator. The output stage is coupled to the load and receives at least one driving signal to convert the input voltage into an output voltage. The driving circuit is coupled to the output stage and generates at least one driving signal according to the time signal. The feedback circuit is coupled to the output stage and generates a trigger signal according to the output voltage. The time signal generator is coupled between the feedback circuit and the driving circuit and receives the input voltage, the output voltage, the load current and the trigger signal to generate a time signal. The time signal generator comprises a compensation unit which receives a digital output voltage signal related to the output voltage, a digital input voltage signal related to the input voltage and a digital load current signal related to the load current respectively, and performs operation processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal, and provides the time signal according to the compensation signal.
In an embodiment of the invention, the time signal generator further includes an analog-to-digital conversion unit coupled to the compensation unit, and configured to receive the output voltage, the input voltage, and the load current, and convert the output voltage, the input voltage, and the load current into a digital output voltage signal, a digital input voltage signal, and a digital load current signal, respectively.
In one embodiment of the present invention, the time signal is related to a digital input voltage signal, a digital output voltage signal, and a digital load current signal.
In one embodiment of the present invention, during the heavy load, the load current flowing through the load increases, so that the digital load current signal related to the load current increases, and the compensation signal generated by the compensation unit also increases.
Compared with the prior art, the DC-DC conversion circuit and the time signal generator thereof can adjust the time signal provided by the DC-DC conversion circuit through the compensation signal related to the load current, so that when the load current is increased by the DC-DC conversion circuit operating in a heavy load steady state, the conduction time of the time signal provided by the time signal generator of the invention is also increased, thereby maintaining the switching frequency of the DC-DC conversion circuit constant and improving the power conversion efficiency of the DC-DC conversion circuit operating in the heavy load steady state.
The advantages and spirit of the present invention will be further understood from the following detailed description of the invention and the accompanying drawings.
Drawings
Fig. 1A is a schematic diagram showing that the turn-off time and period of a pwm signal provided by a conventional dc-dc converter circuit are shortened under a heavy load steady state.
Fig. 1B is a schematic diagram of a conventional dc-dc conversion circuit in which the average value of the inductor current is increased and the period is shortened under a heavy load steady state.
Fig. 2 is a schematic diagram of a time signal generator applied to a dc-dc conversion circuit according to a preferred embodiment of the invention.
FIG. 3 is a functional block diagram of the time signal generator of FIG. 2.
FIG. 4A is a schematic diagram of an embodiment of a digital time signal generator.
Fig. 4B is a schematic diagram of another embodiment of a digital time signal generator.
Fig. 5A and 5B are schematic diagrams of time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention in a light load steady state.
Fig. 5C and 5D are schematic diagrams of the time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention in a heavy-duty steady state.
Description of main reference numerals:
ton1, ton2: time signal
Toff1, toff2: length of off time
Iind1, iind2: inductor current
2: DC-DC conversion circuit
1: time signal generator
10: analog-to-digital conversion unit
11: compensation unit
12: counting unit
14: comparison unit
16: logic unit
DR: driving circuit
OS: output stage
LD: load(s)
And (B): feedback circuit
CLK: clock signal
TR: trigger signal
GND: ground voltage
SVout: digital output voltage signal
Vout: output voltage
SVin: digital input voltage signal
Vin: input voltage
SI L : digital load current signal
I L : negative poleCurrent carrying
S1: compensation signal
S2: counting signal
S3: comparing signals
Ton: time signal
DS1: a first driving signal
DS2: a second driving signal
M1: first multiplier
M2: second multiplier
DIV: divider
DIV1: first divider
DIV2: second divider
ADD: adder device
SUM: sum value
T1, T2, T1', T2': length of on time
D1, D2, D1', D2': period of time signal
Detailed Description
Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The same or similar reference numbers are used in the drawings and the embodiments to refer to the same or similar parts.
A preferred embodiment according to the present invention is a time signal generator. In this embodiment, the time signal generator is applied to the dc-dc conversion circuit for generating the time signal.
Referring to fig. 2, fig. 2 is a schematic diagram of a time signal generator applied to a dc-dc conversion circuit in this embodiment. As shown in fig. 2, the dc-dc conversion circuit 2 is coupled to a load LD and has a load current I L Flows through the load LD. During heavy load, load current I through load LD L Will increase.
The dc-dc conversion circuit 2 includes a time signal generator 1, a driving circuit DR, an output stage OS and a feedback circuit FB. The time signal generator 1 is coupled to the driving circuit DR and the feedback circuit FB. The driving circuit DR is coupled to the time signal generator 1 and the output stage OS. The output stage OS is coupled to the input voltage Vin, the ground voltage GND, the driving circuit DR, the feedback circuit FB and the load LD, and generates an output voltage Vout. The feedback circuit FB is coupled to the output voltage Vout and the time signal generator 1.
The time signal generator 1 receives an input voltage Vin, an output voltage Vout, and a load current I L The clock signal CLK and the trigger signal TR and provides a time signal Ton to the driving circuit DR. The driving circuit DR generates a first driving signal DS1 and a second driving signal DS2 to the output stage OS according to the time signal Ton. The output stage OS is driven by the first driving signal DS1 and the second driving signal DS2 to generate an output voltage Vout. The feedback circuit FB generates a trigger signal TR to the time signal generator 1 according to the output voltage Vout.
In practical applications, the output stage OS includes a first switch and a second switch connected in series between the input voltage Vin and the ground voltage GND, and is driven by a first driving signal D1 and a second driving signal D2, respectively, to output an inductor current Iind between the first switch and the second switch and generate an output voltage Vout.
Referring to fig. 3, fig. 3 is a functional block diagram of the time signal generator 1 in fig. 2. As shown in fig. 3, the time signal generator 1 includes an analog-to-digital conversion unit 10, a compensation unit 11, a counting unit 12, a comparison unit 14, and a logic unit 16. The analog-to-digital conversion unit 10 is coupled to the compensation unit 11. The compensation unit 11 and the counting unit 12 are coupled to the comparing unit 14. The comparing unit 14 is coupled to the logic unit 16.
The analog-digital conversion unit 10 receives the output voltage Vout, the input voltage Vin and the load current I L And respectively converted into a digital output voltage signal SVout, a digital input voltage signal SVin and a digital load current signal SI L And then to the compensation unit 11.
The compensation unit 11 receives the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SI L And digital output voltage signal SVout, digital input voltage signal SVin and digital load current signal SI L After the operation process, a compensation signal S1 is generated. The counting unit 12 provides a counting signal S2 according to the clock signal CLK and the trigger signal TR.
The comparing unit 14 receives the compensating signal S1 from the compensating unit 11 and the counting signal S2 from the counting unit 12, respectively, and provides the comparing signal S3 to the logic unit 16 according to the compensating signal S1 and the counting signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3, respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.
In practical applications, the logic unit 16 of the time signal generator 1 provides the time signal Ton and the digital input voltage signal SVin, the digital output voltage signal SVout and the digital load current signal SI L The present invention is not limited thereto.
During light load, load current I L The resulting compensation value is omitted and the time signal Ton provided by the logic unit 16 remains unchanged. During heavy load, load current I through load LD L Increase, cause and load current I L Related digital load current signal SI L Is increased and the compensation unit 11 is based on the digital load current signal SI L The generated compensation signal S1 and the comparison unit 14 will also increase according to the comparison signal S3 provided by the compensation signal S1, so that the time signal Ton provided by the logic unit 16 will also increase along with the comparison signal S3 and the increase of the time signal Ton will be equal to the digital load current signal SI L The increase in (2) is not limited thereto.
Referring to fig. 4A, fig. 4A is an embodiment of a digital time signal generator. As shown in fig. 4A, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparing unit 14, and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, an adder ADD, and a divider DIV. The adder ADD is coupled to the first multiplier M1. The divider DIV is coupled to the adder ADD and the second multiplier M2.
The first multiplier M1 is used for converting the digital load current signal SI L Multiplying the first constant ki to obtain a first product (ki SI L ). The second multiplier M2 multiplies the digital input voltage signal SVin by a second constant kv to obtain a second product (kv×svin). Adder ADD ADDs the first product ki SI to digital output voltage signal SVout L To obtainTo SUM = (svout+ki SI) L ). The divider DIV is used for dividing the SUM by the second product (kv SVin) to obtain the compensation signal S1, i.e. the compensation signal s1= (svout+ki SI) L )/(kv*SVin)。
The counting unit 12 provides a counting signal S2 according to the clock signal CLK and the trigger signal TR. The comparing unit 14 receives the compensating signal S1 from the compensating unit 11 and the counting signal S2 from the counting unit 12, respectively, and provides the comparing signal S3 to the logic unit 16 according to the compensating signal S1 and the counting signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3, respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.
It should be noted that the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SI provided to the compensation unit 11 L The analog-digital conversion unit 10 can convert the output voltage Vout, the input voltage Vin and the load current I L And is not limited thereto.
Referring to fig. 4B, fig. 4B is a schematic diagram of another embodiment of a digital time signal generator. As shown in fig. 4B, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparing unit 14, and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, a first divider DIV1, a second divider DIV2, and an adder ADD. The first multiplier M1 is coupled to the first divider DIV1. The second multiplier M2 is coupled to the divider DIV and coupled to the first divider DIV1 and the second divider DIV2. The first divider DIV1 and the second divider DIV2 are coupled to the adder ADD.
The first multiplier M1 is used for converting the digital load current signal SI L Multiplying the first constant ki to obtain a first product (ki SI L ). The second multiplier M2 multiplies the digital input voltage SVin signal by a second constant kv to obtain a second product (kv×svin). A first divider DIV1 for dividing the first product (ki SI L ) Dividing the second product (kv SVin) by a first quotient (ki SI) L ) v/SVin. The second divider DIV2 is configured to divide the digital output voltage signal SVout by a second product (kv SVin) to obtain a second quotient SVout/(kv SVin). Adder ADD is used toFirst quotient (ki SI L ) v/SVin and the second quotient SVout/(kv/SVin) to obtain the compensation signal S1, i.e. the compensation signal s1= (svout+ki SI) L )/(kv*SVin)。
It should be noted that the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SI provided to the compensation unit 11 L The analog-digital conversion unit 10 can convert the output voltage Vout, the input voltage Vin and the load current I L And is not limited thereto.
Next, please refer to fig. 5A to 5D. Fig. 5A and 5B are schematic diagrams of time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention in a light load steady state. Fig. 5C and 5D are schematic diagrams of the time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention in a heavy-duty steady state.
As shown in fig. 5A and 5B, in the light load steady state, because of the characteristics of the digital circuit, a small calculation error (e.g., a compensation value caused by a load current in the light load state) is omitted, so that the period D1 of the time signal Ton1 and the length T1 of the on time provided by the conventional digital time signal generator are unchanged from the period D2 of the time signal Ton2 and the length T2 of the on time provided by the digital time signal generator of the present invention, for example, the periods of both are 1000ns and the length of the on time of both is 300ns.
As shown in fig. 5C, in the heavy-duty steady state, the length T1 'of the on-time of the time signal Ton1 provided by the conventional digital time signal generator is still maintained at 300ns, but this also results in the period D1' of the time signal Ton1 changing from 1000ns to 860ns, which shortens the total time by as much as 140ns, resulting in the switching frequency of the conventional dc-dc conversion circuit becoming high to affect the power conversion efficiency thereof.
In contrast, as shown in fig. 5D, in the heavy load steady state, the length T2 'of the on-time of the time signal Ton2 provided by the digital time signal generator of the present invention changes from 300ns to 340ns with the increase of the load current, and the period D2' of the time signal Ton2 changes from 1000ns to 995ns, which shortens only 5ns in total, so that the switching frequency of the dc-dc conversion circuit can be kept constant and the power conversion efficiency of the dc-dc conversion circuit can be improved.
Another preferred embodiment according to the present invention is a dc-dc conversion circuit. In this embodiment, the dc-dc conversion circuit is used to convert an input voltage into an output voltage.
As shown in fig. 2, the dc-dc conversion circuit 2 is coupled to a load LD and has a load current I L Flows through the load LD. The dc-dc conversion circuit 2 includes an output stage OS, a driving circuit DR, a feedback circuit FB and a time signal generator 1. The output stage OS is coupled to the load LD for receiving at least one driving signal DS 1-DS 2 to convert the input voltage Vin into the output voltage Vout. The driving circuit DR is coupled to the output stage OS for generating at least one driving signal DS 1-DS 2 according to the time signal Ton. The feedback circuit FB is coupled to the output stage OS for generating the trigger signal TR according to the output voltage Vout. The time signal generator 1 is coupled between the feedback circuit FB and the driving circuit DR for receiving the input voltage Vin, the output voltage Vout, and the load current I L And a trigger signal TR to generate a time signal Ton.
As shown in fig. 3, the time signal generator 1 includes a compensation unit 11. The compensation unit 11 receives a digital output voltage signal SVout related to the output voltage Vout, a digital input voltage signal SVin related to the input voltage Vin, and a load current I, respectively L Related digital load current signal SI L And digital output voltage signal SVout, digital input voltage signal SVin and digital load current signal SI L The operation process is performed to generate the compensation signal S1, and the time signal Ton is provided according to the compensation signal S1. Therefore, the time signal Ton and the digital input voltage signal SVin, the digital output voltage signal SVout and the digital load current signal SI L Related to the following.
Furthermore, the time signal generator 1 comprises an analog-to-digital conversion unit 10. The analog-digital conversion unit 10 receives the output voltage Vout, the input voltage Vin and the load current I L And respectively converted into digital output voltage signals SVout and digital input voltage signals SVin and digital load current signal SI L And then to the compensation unit 11.
During heavy load, load current I flowing through load LD L Increase, cause and load current I L Related digital load current signal SI L The compensation signal S1 generated by the compensation unit 11 increases. The other components and operation of the dc-dc converter 2 are referred to the above embodiments, and are not described herein.
Compared with the prior art, the DC-DC conversion circuit and the time signal generator thereof can adjust the time signal provided by the time signal generator to the driving circuit of the DC-DC conversion circuit through the compensation signal related to the load current, so that when the DC-DC conversion circuit operates in a heavy load steady state and the load current increases, the conduction time in the time signal provided by the time signal generator of the invention also increases, thereby maintaining the switching frequency of the DC-DC conversion circuit constant and improving the power conversion efficiency of the DC-DC conversion circuit in the heavy load steady state.
In view of the foregoing detailed description of the preferred embodiments, it is intended that the features and spirit of the invention be more clearly described rather than limiting the scope of the invention as defined by the foregoing description of the preferred embodiments. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
Claims (10)
1. A time signal generator for generating a time signal to enable a dc-dc conversion circuit to convert an input voltage into an output voltage, the dc-dc conversion circuit being coupled to a load and having a load current flowing through the load, the time signal generator comprising:
an analog-to-digital conversion unit for receiving the output voltage, the input voltage, and the load current, respectively, and converting the output voltage, the input voltage, and the load current into digital output voltage signals, digital input voltage signals, and digital load current signals, respectively;
a compensation unit for receiving the digital output voltage signal, the digital input voltage signal and the digital load current signal, respectively, and performing operation processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal;
a counting unit for providing a counting signal according to the clock signal and the trigger signal;
a comparison unit for receiving the compensation signal and the count signal to provide a comparison signal; and
and the logic unit is used for receiving the trigger signal and the comparison signal to provide the time signal.
2. The time signal generator of claim 1, wherein the time signal is related to the digital input voltage signal, the digital output voltage signal, and the digital load current signal.
3. The time signal generator of claim 1, wherein during a heavy load, the load current flowing through the load increases, such that the digital load current signal associated with the load current increases, and the compensation signal generated by the compensation unit and the comparison signal provided by the comparison unit also increase.
4. The time signal generator according to claim 1, wherein the compensation unit comprises:
a first multiplier for multiplying the digital load current signal by a first constant to obtain a first product;
a second multiplier for multiplying the digital input voltage signal by a second constant to obtain a second product;
an adder coupled to the first multiplier for adding the first product to the digital output voltage signal to obtain a sum; and
a divider coupled to the adder and the second multiplier for dividing the sum by the second product to obtain the compensation signal.
5. The time signal generator of claim 4, wherein the time signal also increases with the sum, and wherein the increase in the time signal is related to the increase in the digital load current signal.
6. The time signal generator according to claim 1, wherein the compensation unit comprises:
a first multiplier for multiplying the digital load current signal by a first constant to obtain a first product;
a second multiplier for multiplying the digital input voltage signal by a second constant to obtain a second product;
a first divider coupled to the first multiplier and the second multiplier for dividing the load current signal by the second product to obtain a first quotient;
a second divider coupled to the second multiplier for dividing the digital output voltage by the second product to obtain a second quotient; and
and the adder is coupled with the first divider and the second divider and is used for adding the first quotient and the second quotient to obtain the compensation signal.
7. A dc-dc conversion circuit for converting an input voltage into an output voltage, the dc-dc conversion circuit being coupled to a load and having a load current flowing through the load, the dc-dc conversion circuit comprising:
an output stage coupled to the load for receiving at least one driving signal to convert the input voltage into the output voltage;
the driving circuit is coupled with the output stage and generates at least one driving signal according to the time signal;
the feedback circuit is coupled with the output stage and generates a trigger signal according to the output voltage; and
the time signal generator is coupled between the feedback circuit and the driving circuit and receives the input voltage, the output voltage, the load current and the trigger signal to generate the time signal;
wherein the time signal generator comprises:
and a compensation unit for receiving the digital output voltage signal related to the output voltage, the digital input voltage signal related to the input voltage and the digital load current signal related to the load current, respectively, and performing an operation process on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal, and providing the time signal according to the compensation signal.
8. The dc-dc conversion circuit according to claim 7, wherein the time signal generator further comprises:
the analog-digital conversion unit is coupled to the compensation unit, receives the output voltage, the input voltage and the load current, and converts the output voltage, the input voltage and the load current into the digital output voltage signal, the digital input voltage signal and the digital load current signal, respectively.
9. The dc-dc conversion circuit of claim 7 wherein the time signal is related to the digital input voltage signal, the digital output voltage signal, and the digital load current signal.
10. The dc-dc conversion circuit of claim 7, wherein during a heavy load, the load current flowing through the load increases, such that the digital load current signal associated with the load current increases, and the compensation signal generated by the compensation unit increases.
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| CN201811415834.3A CN111224645B (en) | 2018-11-26 | 2018-11-26 | DC-DC conversion circuit and time signal generator thereof |
| TW108142759A TWI789561B (en) | 2018-11-26 | 2019-11-25 | Dc-dc converter and time signal generator thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN111224645A (en) | 2020-06-02 |
| TWI789561B (en) | 2023-01-11 |
| TW202037049A (en) | 2020-10-01 |
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