TW201933449A - Device manufacturing method and transfer substrate - Google Patents

Abstract

The present invention reduces the burden of electronic device manufacturers and enables highly accurate electronic device manufacturing. A device manufacturing method wherein a multilayer structure is transferred onto a second substrate after forming at least some multilayer structures, which constitute an electronic device, on a first substrate that serves as a transfer substrate. This device manufacturing method comprises: a first step wherein a multilayer structure is produced by forming a first conductive layer on a first substrate, forming a function layer on the first conductive layer, and forming a second conductive layer on the function layer; and a second step wherein the multilayer structure is transferred onto a second substrate by temporarily having the first substrate and the second substrate closely adhere to each other in such a manner that the second conductive layer is positioned on the second substrate side.

Description

Transfer substrate

The present invention relates to a transfer substrate on which a laminated structure constituting at least a part of an electronic component is formed, and a component manufacturing method for producing an electronic component by transferring the laminated structure formed on the transfer substrate to a substrate to be transferred. method.

A method for forming an organic EL layer is disclosed in Japanese Patent Application Laid-Open No. 2006-302814. Briefly, firstly, a hole transport layer is formed on the first endless belt by a coating method (jet method, etc.), and a light-emitting layer is formed on the second endless belt by a coating method (jet method, etc.). Method, etc.) An electron transporting layer is formed on the third endless belt. Next, the hole-shaped transport layer formed on the first endless belt is transferred from the sheet substrate supplied from the supply roll, and then the light-emitting layer formed on the second endless belt is transferred to the hole-transported layer. The organic EL layer is formed by transferring the electron transporting layer formed on the third endless belt to the light-emitting layer.

However, for example, when manufacturing electronic components including semiconductor elements such as thin-film transistors, in order to improve the performance or yield of the semiconductor elements or stabilize the characteristics, it is preferable to form the film in a vacuum space such as easy control of film thickness. The transfer method of the technique described in Japanese Patent Application Laid-Open No. 2006-302814 makes it difficult to manufacture high-precision electronic components.

On the other hand, although most electronic components are generally manufactured on glass substrates, and the completed electronic components are transferred from the glass substrate to other final substrates (such as a flexible resin film or Plastic plate), but in this case, the manufacturers of electronic components are film-forming in a vacuum space and the layers constituting the electronic components are formed on a glass substrate, or the lithography is used repeatedly according to the laminated structure of the electronic components. After developing the electronic components by developing processing, etching processing, CVD processing, sputtering processing, etc., the completed electronic components are transferred to the final substrate. Therefore, in addition to the manufacturing cost of manufacturing electronic components on glass substrates, manufacturers of electronic components need to use equipment to implement most film-forming processes for forming the layer structure of electronic components on glass substrates. It takes manufacturing costs (equipment) to transfer (transfer) the electronic components on the glass substrate to the final substrate. Therefore, it is difficult to reduce the price of the final electronic components (LCD or organic EL display panels, touch panels, etc.), which places a great burden on the manufacturers of electronic components.

A first aspect of the present invention is a component manufacturing method in which at least a part of a laminated structure constituting an electronic component is formed on a first substrate, and then the laminated structure is transferred onto a second substrate. : In the first step, a first conductive layer formed of a conductive material is formed on the first substrate, and a functional layer made of at least one of an insulating material and a semiconductor is formed on the first conductive layer. A second conductive layer formed of a conductive material is formed thereon to form the laminated structure; and a second step is to temporarily place the first substrate and the second substrate such that the second conductive layer is positioned on the second substrate side. The laminated structure is brought into close contact with or closely adhered to the second substrate.

A second aspect of the present invention is a transfer substrate for transferring at least a part of a laminated structure constituting an electronic component to a transferred substrate, wherein the laminated structure is formed on a surface of the transfer substrate. The aforementioned laminated structure system includes a first conductive layer formed on the transfer substrate using a conductive material, a functional layer formed on the first conductive layer using at least one of an insulating material and a semiconductor, and a conductive material. Formed on the aforementioned functional layer It is composed of the second conductive layer.

A third aspect of the present invention is a transfer substrate for supporting the laminated structure to transfer at least a part of the laminated structure constituting the electronic component onto a product substrate forming an electronic component including a semiconductor element. The above-mentioned laminated structure is the same or selectively the first conductive layer formed from the surface side of the transfer substrate in the same or selectively using a conductive material, using an insulating material, or a material exhibiting semiconductor characteristics. The formed functional layer and the second conductive layer formed in the same or selectively formed using a conductive material are sequentially laminated.

A fourth aspect of the present invention is a component manufacturing method in which a first substrate on which at least a part of a laminated structure constituting an electronic component is formed is transferred onto a second substrate, and the method includes the first step of preparing the foregoing The first substrate is a first conductive layer made of a conductive material. A functional layer made of at least one of an insulating material and a semiconductor is formed on the first conductive layer, and a first layer made of a conductive material is formed on the functional layer. 2 conductive layers to form the laminated structure; and a second step of temporarily bringing the first substrate and the second substrate close to or in close contact with each other so that the second conductive layer is located on the second substrate side, so as to include the foregoing The laminated structure of the first substrate is transferred to the second substrate.

A fifth aspect of the present invention is a transfer substrate for transferring at least a part of a laminated structure constituting an electronic component to a transfer substrate, and is characterized in that it includes a conductive foil, and uses a conductive material to develop the first component. 1 a conductive layer function; a functional layer formed on the aforementioned first conductive layer using at least one of an insulating material and a semiconductor; and a second conductive layer formed on the aforementioned functional layer using a conductive material.

10‧‧‧Film forming device

12‧‧‧ supply reel

14‧‧‧Recycling reel

16‧‧‧Processing Room

18‧‧‧Vacuum pump

20‧‧‧ substrate

22‧‧‧ Rotary cylinder for film formation

30‧‧‧Laminated device

32, 34‧‧‧ supply reels

36‧‧‧Compression heating roller

38, 40‧‧‧ Recycling reels

GR1, GR2, GR3, GR5, GR6 ‧‧‧Guide rollers

50‧‧‧ peeling layer

52‧‧‧Laminated structures

52a‧‧‧The first conductive layer

52b‧‧‧Functional layer

52c‧‧‧Second conductive layer

54‧‧‧ Adjacent layer

56‧‧‧Gold

58‧‧‧Semiconductor layer

P1‧‧‧The first substrate

P2‧‧‧The second substrate

FIG. 1 is a diagram showing a configuration of a film forming apparatus for forming a thin film on a substrate according to a first embodiment.

FIG. 2 is a diagram showing a configuration of a multilayer device for transferring a structure of a multilayer body formed on a first substrate to a second substrate according to the first embodiment.

FIG. 3 is a flowchart showing an example of steps in a method of manufacturing a bottom-contact TFT.

FIG. 4 is a flowchart showing an example of steps in a method of manufacturing a bottom-contact TFT.

5A to 5F are cross-sectional views showing a manufacturing process state of a TFT manufactured by the steps shown in FIGS. 3 and 4.

6A to 6D are cross-sectional views showing a manufacturing process state of a TFT manufactured by the steps shown in FIGS. 3 and 4.

FIG. 7 is a flowchart showing an example of steps in a method of manufacturing a top-contact TFT.

FIG. 8 is a flowchart showing an example of steps in a method of manufacturing a top-contact TFT.

9A to 9D are cross-sectional views showing a manufacturing process state of a TFT manufactured by the steps shown in FIGS. 7 and 8.

10A to 10C are cross-sectional views showing a manufacturing process state of a TFT manufactured by the steps shown in FIGS. 7 and 8.

FIG. 11 is a flowchart showing an example of steps in a method of manufacturing a top-contact TFT according to Modification 1 of the first embodiment.

FIG. 12 is a flowchart showing an example of steps in a method of manufacturing a top-contact TFT according to Modification 1 of the first embodiment.

13A to 13F are cross-sectional views showing a manufacturing process state of a TFT manufactured by the steps shown in FIGS. 11 and 12.

14A to 14F are cross-sectional views showing a manufacturing process state of a TFT manufactured by the steps shown in FIGS. 11 and 12.

FIG. 15 is a cross-sectional view when an alignment mark is formed on the second conductive layer in the third modification of the first embodiment.

FIG. 16 is a cross-sectional view when a window portion is formed on the first conductive layer in the third modification of the first embodiment.

FIG. 17 is a diagram showing a configuration of a lamination apparatus in Modification 4 of the first embodiment.

FIG. 18 is a diagram showing a configuration of a lamination apparatus in Modification 5 of the first embodiment.

FIG. 19 is a diagram showing an example of a pixel circuit of an organic EL display in the second embodiment.

FIG. 20 is a diagram showing a specific structure of the pixel circuit shown in FIG. 19.

FIG. 21 is a flowchart showing an example of steps in a method of manufacturing the pixel circuit shown in FIG. 20.

FIG. 22 is a flowchart showing an example of steps in a method of manufacturing the pixel circuit shown in FIG. 20.

FIG. 23 is a cross-sectional view of a laminated structure formed on a first substrate in steps S101 to S105 of FIG. 21.

FIG. 24 is a cross-sectional view of the laminated structure with the second conductive layer processed in steps S106 to S111 of FIG. 21.

FIG. 25 is a plan view of the laminated structure shown in FIG. 24.

FIG. 26 is a cross-sectional view when the laminated structure formed on the first substrate in step S113 of FIG. 21 is transferred to the second substrate.

FIG. 27 is a cross-sectional view of the laminated structure of the first conductive layer processed in steps S114 to S118 of FIG. 22.

FIG. 28 is a plan view of the laminated structure shown in FIG. 27.

FIG. 29 is a cross-sectional view when the functional layer of the contact hole portion shown in FIG. 27 is etched in steps S119 to S122 of FIG. 22.

FIG. 30 is a cross-sectional view when a non-plated contact is formed on the contact hole portion shown in FIG. 29 in step S123 of FIG. 22.

FIG. 31 is a diagram showing a modified example of the film forming apparatus shown in FIG. 1. FIG.

FIG. 32 is a diagram showing another configuration example of the multilayer structure of the top-contact TFT and a transfer example of the multilayer structure.

FIG. 33 is a diagram showing a state where a planarizing film is used during the transfer shown in FIG. 32.

34A to 34D are diagrams showing a manufacturing process of the laminated structure when the laminated structure of the electronic component shown in FIGS. 23 to 30 is improved.

FIG. 35 is a diagram showing a plan arrangement configuration of the laminated structure shown in FIG. 34D formed on a first substrate.

FIG. 36A is a diagram showing a moment after transferring the laminated structure shown in FIG. 34D formed on the first substrate to the second substrate in a transfer step, and FIG. 36B is a diagram showing the first conductive structure shown in FIG. 36A The layers are formed with patterns such as a gate electrode and a drain electrode.

FIG. 37 is a diagram showing an example of a plan arrangement configuration of the TFT of FIG. 36B.

With regard to the element manufacturing method and the transfer substrate according to aspects of the present invention, a preferred embodiment is disclosed, which will be described in detail below with reference to the drawings. In addition, aspects of the present invention are not limited to these embodiments, and include various modifications or improvements.

[First Embodiment]

FIG. 1 shows a film forming apparatus 10 for forming a thin film on a substrate (hereinafter referred to as a first substrate) P1. Composed figure. The first substrate P1 is a flexible sheet-like substrate (sheet-like substrate), and the film forming apparatus 10 has a supply from which the first substrate (transfer substrate, carrier substrate) P1 is wound into a roll shape. The first substrate P1 supplied by the reel 12 is subjected to a film formation process and is taken up by a recovery roll 14 after being subjected to a film forming process, which is a so-called roll-to-roll structure. This first substrate P1 has a strip-like shape in which the moving direction of the first substrate P1 is a long side direction (long strip) and the width direction is a short side direction (short side). The film forming apparatus 10 further includes a processing chamber 16, a vacuum pump 18 that sucks air in the processing chamber 16 and makes the processing chamber 16 become a vacuum, a substrate 20 as a film forming material (thin film material), guide rollers GR1 to GR3, And the rotating cylinder 22 for film formation.

A motor (not shown) is provided in the supply reel 12 and the recovery reel 14, and the first substrate P1 is unloaded from the supply reel 12 by rotating the motor, and the first substrate sent out is wound by the recovery reel 14. P1. In addition, the film-forming rotating cylinder 22 is a portion that carries the first substrate P1 while rotating and supports the film formation on a circumferential surface. Thereby, the 1st board | substrate P1 is conveyed along the outer peripheral surface (circumferential surface) of the film-forming rotating cylinder 22 to the collection | recovery roll 14. The guide rollers GR1 to GR3 are used to guide the path of the first substrate P1 to be conveyed. A film-forming rotary cylinder 22 is provided with a motor (not shown), and the film-forming rotary cylinder 22 is rotated by this motor.

The film forming apparatus 10 forms a thin film (layer) on the first substrate P1 by vapor deposition or sputtering. When forming a film by vapor deposition, the substrate 20 is heated by a method such as resistance heating, electron beam, high-frequency induction, or laser, so that the vaporized or sublimated film-forming material is adhered to the first substrate P1 to Form a thin film. When forming a film by sputtering, the ionized argon gas is collided with the base material 20 to release the molecules of the base material 20, and the free molecules are attached to the first substrate P1 to form a thin film. Therefore, the recovery roll 14 is a first substrate P1 on which a film (layer) is formed on its surface. In addition, the film forming apparatus 10 may form a thin film by CVD (Chemical Vapor Deposition). In addition, as the film forming apparatus 10, for example, an apparatus using the atomized deposition method (atomized CVD method) disclosed in the specification of International Publication No. 2013/176222 may be used.

This type of film forming apparatus 10 can be used to successively laminate several layers of thin films on the first substrate P1. That is, the reel 14 used for winding the first substrate P1 having the first layer formed on the surface is used as the supply roll 12 of another film forming apparatus 10, that is, by the aforementioned another film forming apparatus. 10 to build a new layer (layer 2) on top of layer 1. In addition, when laminating, it is also possible to laminate films of different materials by changing the base material 20 as a film-forming raw material. By laminating this thin film, at least a part of the laminated structure of an electronic element constituting a semiconductor element such as a thin film transistor (TFT) can be formed on the first substrate P1 as a supporting substrate.

For example, when forming a bottom-contact TFT (thin film transistor), a film-forming device 10 is used to sequentially laminate a metal-based material (Cu, Al, Mo, etc.) or a thin film of ITO (first an electrically conductive layer), a film (insulating layer) of insulating material (SiO _2, Al ₂ O _3, etc.), film (second conductive layer), a metal-based material (Cu, Al, Mo, etc.), constituting the TFT of at least a portion The laminated structure is formed on the first substrate P1. When forming a top-contact TFT, a thin film (first conductive layer) of a metal-based material (Cu, Al, Mo, etc.), and an oxide semiconductor (IGZO, ZnO, etc.) are sequentially laminated by the film forming apparatus 10. Thin films (semiconductor layers) such as silicon (α-Si) or organic semiconductors (pentacene), thin films (insulating layers) of insulating materials (SiO ₂ , Al ₂ O _3, etc.), and metallic materials (Cu, Al , Mo, etc.) or a thin film (second conductive layer) of ITO, whereby a multilayer structure constituting a TFT can be formed on the first substrate P1.

The first substrate P1 in which the laminated structure is formed as described above is processed by a non-vacuum processing device such as photolithography (photo-patterning) and etching, which will be described in detail later, and processed into an electrode layer for a semiconductor element. , Insulating layer, wiring layer, or semiconductor layer. The laminated structure of the first substrate P1 processed into such a pattern shape is transferred to a substrate (hereinafter referred to as a second substrate) P2. FIG. 2 is a diagram showing a configuration of a lamination apparatus 30 for transferring (laminating) a laminated structure formed on a first substrate P1 to a second substrate P2 (product substrate). This laminated device 30 is, for example, a low-temperature thermal transfer system that transfers the laminated structure formed on the first substrate P1 to the second substrate P2 at a low temperature of 100 degrees or less. The laminating device 30 includes supply rolls 32 and 34, pressure-contact heating rolls 36, recovery rolls 38 and 40, and guide rolls GR5 and GR6.

The supply roll 32 is a roll in which the first substrate P1 having the laminated structure formed on the surface is rolled into a roll shape, and the first substrate P1 is carried out to the recovery roll 38. The supply roll 34 rolls the second substrate P2 of the transfer laminated structure into a roll shape, and carries the second substrate P2 to the recovery roll 40. In addition, the second substrate P2 is also a flexible sheet-like substrate (sheet substrate, substrate to be transferred) similar to the first substrate P1, and the moving direction of the second substrate P2 is the long side direction (long strip). , The width direction is a strip shape in the short side direction (short strip).

The crimping heating roller 36 sandwiches the first substrate P1 supplied from the supply reel 32 and the second substrate P2 supplied from the supply reel 34 from both sides, and temporarily contacts the two substrates for pressure bonding and simultaneously heating. This makes it possible to transfer the multilayer structure formed on the first substrate P1 to the second substrate P2. That is, the laminated structure formed on the first substrate P1 is softened by heating (for example, a low temperature of 100 ° C. or lower) by the pressure-bonding heating roller 36, and is softened by the pressure-bonding by the pressure-bonding heating roller 36. The laminated structure on the first substrate P1 is transferred to the second substrate P2. An elastic body is preferably used for the surface of the pressure-bonding heating roller 36, and the temperature and pressure (pressure) of the pressure-bonding heating roller 36 are arbitrarily set depending on the transfer material.

The recovery roll 38 is recovered by rolling up the first substrate P1 passing through the pressure-contact heating roller 36, that is, the first substrate P1 from which the laminated structure has been peeled off. Recovery roll 40 by The second substrate P2, which is the pressure-bonded heating roller 36, that is, the second substrate P2 (the second substrate P2 having the laminated structure formed on the surface) on which the laminated structure is transferred is wound up and recovered. The guide roller GR5 is used to guide the first substrate P1 supplied from the supply roll 32 to the pressure heating roller 36, and the guide roller GR6 is used to guide the second substrate P2 supplied from the supply roll 34 to压 接 热 轮 36。 Pressing the heating roller 36.

Here, as the first substrate P1 and the second substrate P2, for example, a foil made of a metal or an alloy such as a resin film and stainless steel can be used. As the material of the resin film, for example, polyethylene resin, polypropylene resin, polyester resin, ethylene-vinyl acetate copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, and polycarbonate can be used. The ester resin, the polystyrene resin, and the vinyl acetate resin include at least one of them. In addition, the thickness or rigidity (Young's modulus) of the first substrate P1 and the second substrate P2 does not cause creases or irreversible wrinkles caused by bending on the first substrate P1 and the second substrate P2 during transportation. The range is fine. As the base material of the first substrate P1 and the second substrate P2, films such as PET (polyethylene terephthalate) and PEN (polynaphthalene dicarboxylic acid) having a thickness of about 25 μm to 200 μm are typical of preferred sheet substrates.

The first substrate P1 and the second substrate P2 may be heated during the processing applied to the first substrate P1 and the second substrate P2. Therefore, it is preferable to select a substrate having a material whose thermal expansion coefficient is not significantly large. For example, a thermal expansion coefficient can be suppressed by mixing an inorganic filler with a resin film. The inorganic filler may be, for example, titanium oxide, zinc oxide, aluminum oxide, or silicon oxide. In addition, the first substrate P1 and the second substrate P2 may be a single-layer body of ultra-thin glass having a thickness of about 100 μm manufactured by a floating method or the like, or may be attached to the ultra-thin glass to which the above-mentioned resin film and foil are bonded. Laminated body.

In addition, as shown in the film forming apparatus 10 of FIG. 1, the first substrate P1 may be heated to a temperature of, for example, 100 ° C. to 300 ° C. during film formation. Therefore, the base material of the first substrate P1 is preferably a polymer having excellent heat resistance. Imide resin, extremely thin glass, or extremely thin metal foil (rolled into ten (Copper foil, stainless steel foil, aluminum foil, etc.) with a thickness of several μm to several hundreds of μm. Moreover, the first substrate P1 does not have to be a long sheet-like substrate that can be rolled into a roll, but it can also be a single-piece piece that is cut to a size that matches the size of the electronic component (or its circuit substrate) to be manufactured. Substrate, glass substrate, metal plate.

Next, a method for manufacturing a TFT will be described. Although the structure of the TFT can be largely divided into a bottom-gate structure and a top-gate structure, in this first embodiment, the manufacturing steps of the TFT with the bottom-gate structure are explained, and the manufacture of the TFT with the top-gate structure is omitted. Explanation of steps. In addition, TFTs with a bottom gate structure are classified into a bottom contact type and a top contact type. Therefore, the method of manufacturing the bottom contact TFT will be described first, and then the method of manufacturing the top contact TFT will be described.

(Manufacturing method of bottom-contact TFT)

3 and 4 are flowcharts showing an example of the steps of a method for manufacturing a bottom-contact TFT. FIGS. 5A to 5F and FIGS. 6A to 6D show the manufacturing process status of a TFT manufactured by the steps shown in FIGS. 3 and 4. Section view. First, in step S1 of FIG. 3, as shown in FIG. 5A, a release layer 50 is formed on the first substrate P1. For example, the release layer 50 may be formed by applying a fluorine-based material or an alkali-soluble release agent (a material soluble in alkali) on the surface of the first substrate P1, or by forming a photosensitive alkali-soluble film The dry film resist (DFR) is laminated on the first substrate P1 to form a peeling layer 50. Examples of the alkali-soluble release agent include a mixture of a binder resin and a carboxyl group. This peeling layer 50 is a layer for easily peeling the laminated structure from the first substrate P1.

Next, as shown in FIG. 5B, a laminated structure 52 is formed on the first substrate P1 (first step). The laminated structure 52 is made of a metal-based material (conductive material such as Cu, Al, Mo, Au, etc.) or ITO (conductive material) deposited on the first substrate P1 (on the release layer 50) with a predetermined thickness. thin film (first conductive layer) 52a, at a predetermined thickness deposited on an insulating material (SiO _2, Al ₂ O ₃ and the like of the insulating material) of the first conductive layer 52a of (functional layer) 52b, at a predetermined thickness is deposited on The functional layer 52b is made of a metal-based material (conductive material such as Cu, Al, Mo, or Au) or a thin film (second conductive layer) 52c of ITO (conductive material). In addition, when copper (Cu) is used as the material of the first conductive layer 52a and the second conductive layer 52c constituting the laminated structure 52, the material of the first substrate P1 is also copper (Cu) so that the thermal expansion coefficients are uniform.

Therefore, first, in step S2, a first conductive layer 52a is formed (stacked) on the first substrate P1 (the peeling layer 50). Next, in step S3, an insulating layer, that is, a functional layer 52b is formed (deposited) on the first conductive layer 52a, and a second conductive layer 52c is formed (deposited) in step S4. Thereby, a laminated structure 52 is formed on the first substrate P1. The first conductive layer 52a, the functional layer 52b, and the second conductive layer 52c are continuously formed on the first substrate P1 by using the film forming apparatus 10 of FIG. 1 as described above. The first conductive layer 52a functions as an electrode layer of the source electrode and the drain electrode, and functions as a wiring layer of the wiring attached to the source electrode and the drain electrode. In addition, the second conductive layer 52c functions as an electrode layer of the gate electrode and a wiring layer of wiring attached to the gate electrode. Here, in order to make the electrical characteristics (mobility, ON / OFF ratio, leakage current, etc.) of the TFT good, the interface between the first conductive layer 52a and the functional layer 52b, or the interface between the functional layer 52b and the second conductive layer 52c, It is preferable to be flattened at a level of an ultramicron or less. Therefore, it is also preferable that the surface on the peeling layer 50 side of the first substrate P1 is flattened to a level of ultra-micron or less.

Thereafter, the first substrate P1 on which the laminated structure 52 is formed is subjected to an etching process using a lithography method, and as shown in FIG. 5C, a gate electrode and wirings attached thereto are formed on the second conductive layer 52 c. (Step 1). Note that only the gate electrode is shown in FIG. 5C.

Since the etching process using this lithography method is a well-known technique, it is briefly explained that a photoresist layer is formed on the second conductive layer 52c in step S5. The photoresist layer is formed by The liquid resist can be easily implemented by a roll printing method, a spin coating method, a spray method, or the like, or a photoresist layer of a dry film resist (DFR) is laminated on the second conductive layer 52c. Next, in step S6, a predetermined pattern (a pattern of the gate electrode and wiring attached thereto) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S7 (the first substrate P1 is immersed in TMAH or the like for development). Liquid), thereby removing a portion of the photoresist layer that has been exposed to ultraviolet light. Thereby, a predetermined pattern (resist image) is formed on the photoresist layer. Next, in step S8 after the first substrate P1 is washed and dried, the first substrate P1 on which the laminated structure 52 is formed is immersed in an etching solution (for example, second iron oxide), and a predetermined pattern is formed. The photoresist layer is used as an etching treatment for the photomask, and a gate electrode and wirings attached thereto are formed on the second conductive layer 52c. Next, in step S9, the photoresist layer on the second conductive layer 52c is peeled off, and the first substrate P1 is cleaned. Thereby, a laminated structure 52 as shown in FIG. 5C is obtained. In addition, the cleaning of the first substrate P1 may be performed by using an alkaline cleaning solution such as NaOH.

Next, in step S10, as shown in FIG. 5D, the adhesive layer 54 is formed by applying an adhesive to the surface side (layer structure 52 side) of the first substrate P1 on which the layered structure 52 is formed. This adhesive layer 54 is for making the laminated structure 52 formed on the first substrate P1 easy to be transferred (adhered to) the second substrate P2. As this adhesive, for example, an adhesive for drying a laminate, a UV (ultraviolet) curing adhesive that can change from a liquid to a solid in response to the light energy of ultraviolet rays, or a thermal curing adhesive can also be used. In the first embodiment, a dry laminating adhesive is used.

Next, in the case of drying the adhesive for lamination, the first substrate P1 and the second substrate P2 are temporarily brought into close contact with or closely contacted with each other so that the second conductive layer 52c is positioned on the second substrate P2 side, and will be formed on the first substrate. The laminated structure 52 on the substrate P1 is transferred to the second substrate P2 (second step). This transfer is performed by the laminating apparatus 30 of FIG. 2 as described above. That is, the peeling layer 50, the laminated structure 52, and the adhesive layer 54 are used as a supply roll of the stacking device 30 by winding the first substrate P1 laminated in a roll form from the surface side of the first substrate P1 in the aforementioned order. 32 is used, and the laminated structure 52 formed on the first substrate P1 can be transferred to the second substrate P2. At this time, the release layer 50 does not transfer to the second substrate P2 side but remains on the first substrate P1 side.

To explain in detail, first, as shown in FIG. 5E, the adhesive layer 54 formed on the laminated structure 52 is adhered to the surface of the second substrate P2 (step S11). As shown in FIG. 5F, the laminated structure is formed by the release layer 50. The body 52 is peeled from the first substrate P1 (step S12). Thereby, the laminated structure 52 on the first substrate P1 is transferred to the second substrate P2. By this transfer, the laminated structure 52 is formed on the second substrate P2 in an inverted state. That is, the second conductive layer 52c, the functional layer 52b, and the first conductive layer 52a constituting the laminated structure 52 are laminated on the second substrate P2 from the surface side of the second substrate P2 in the aforementioned order, and the first conductive layer 52a is exposed. . The second substrate P2 on which the laminated structure 52 is transferred by the laminating device 30 is taken up by the recovery roll 40. When the release layer 50 has been peeled from the first substrate P1 and transferred to the second substrate P2 side, the release layer 50 is removed and the second substrate P2 is washed. The second substrate P2 may be cleaned by using an alkaline cleaning solution such as NaOH. Since the peeling layer 50 is soluble, it can be removed from the first conductive layer 52a by a solvent.

Next, the recovery roll 40 is used as a supply roll, and the second substrate P2 carried out from the supply roll is subjected to an etching process using a lithography method. As shown in FIG. 6A, a source electrode is formed on the first conductive layer 52a. And the wiring attached to the drain electrode, the source electrode, and the drain electrode (step 4). Note that FIG. 6A shows only the source electrode and the drain electrode.

A brief description of the source electrode etc. performed by the etching process using the lithography method For formation, first, a photoresist layer is formed on the surface side (the first conductive layer 52a side) of the second substrate P2 in step S13 of FIG. 4. As described in step S5, the photoresist layer is formed by transferring a dry film resist (DFR) or applying a liquid resist. Next, in step S14, a predetermined pattern (a pattern of the source electrode and the drain electrode and the wiring attached to the source electrode and the drain electrode) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S15. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S16, the second substrate P2 on which the laminated structure 52 is formed is immersed in an etching solution (for example, second iron oxide, etc.), and the photoresist layer having a predetermined pattern is etched as a photomask. A source electrode, a drain electrode, and the like are formed on the first conductive layer 52a. Next, in step S17, the photoresist layer on the first conductive layer 52a is peeled off, and the second substrate P2 is cleaned. Thereby, the laminated structure 52 as shown in FIG. 6A is produced.

The source electrode and the drain electrode must be precisely aligned (superimposed) on the gate electrode (second conductive layer 52c) below the functional layer (insulating layer) 52b, which is located immediately below. Therefore, the exposure device (drawing device) used in the exposure step of step S14 includes the step of forming the gate electrodes and the like in steps S5 to S9 in FIG. The alignment mark formed by the second conductive layer 52c passes through the functional layer (insulating layer) 52b or an alignment sensor that is optically detected directly and precisely adjusts the predetermined pattern according to the detection position of the mark and the predetermined pattern to be exposed at step S14 ( The function of the relative positional relationship between the ultraviolet rays and the second substrate P2 corresponding to the patterns of the source electrode, the drain electrode, and the attached wiring).

Next, in step S18, as shown in FIG. 6B, the source electrode and the drain electrode of the first conductive layer 52a are subjected to Au replacement plating (a fourth step). Au (gold) 56 coated by this replacement plating process is used to reduce the impedance (improve the electron mobility) of the contact interface between the source electrode and the drain electrode and a semiconductor layer described later.

Thereafter, in step S19, as shown in FIG. 6C, a thin film (semiconductor layer) 58 of a semiconductor (IGZO, ZnO, etc.) is formed on the second substrate P2 (on the first conductive layer 52a) (fourth step). Next, an etching process using a lithography method is performed, and as shown in FIG. 6D, the semiconductor layer 5 is processed (fourth step). That is, a photoresist layer is formed on the semiconductor layer 58 in step S20, a predetermined pattern is formed on the formed photoresist layer using ultraviolet rays in step S21, and development is performed in step S22. At the time of this exposure, the alignment mark is used to detect the alignment mark, so that the portion of the semiconductor layer 58 that should be left precisely crosses between the drain electrode and the source electrode to precisely position the irradiation position of ultraviolet rays. .

Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S23, the second substrate P2 is immersed in an etching solution (such as hydrogen fluoride), and the photoresist layer having a predetermined pattern is etched as a photomask to process the semiconductor layer 58. Thereby, as shown in FIG. 6D, the semiconductor layer 58 at least between the source electrode and the drain electrode remains, and the unnecessary semiconductor layer 58 can be removed except for this. Thereafter, in step S24, the photoresist layer on the semiconductor layer 58 is peeled off, and the second substrate P2 is cleaned. Through such a step, a bottom-contact TFT as shown in FIG. 6D is formed on the second substrate P2. The semiconductor layer 58 may be an organic semiconductor or an oxide semiconductor. In this case, patterning with a resist may be performed in advance to selectively apply the liquid material of the semiconductor to a region including between the source electrode and the drain electrode (channel portion), and then use a lift-off method on the source electrode. A semiconductor layer 58 is formed between the electrode and the drain electrode.

In the steps described above, the supplier of the first substrate P1 may also perform at least steps S1 to S4 of FIG. 3 (FIGS. 5A and 5B), and the steps after the steps performed by the supplier are performed by the electronic components. Manufacturers carry on. For example, steps S1 to S4 in FIG. 3 may be performed by a supplier, and steps S5 to S4 in FIG. 3 may be performed by a manufacturer. Steps (Figure 5C ~ Figure 6D). In this embodiment, the first substrate P1 (the supporting substrate of the laminated structure 52) manufactured through steps S1 to S4 in FIG. 3 is in a state of being rolled into a roll shape as an intermediate product or Manufacturers of electronic components that are cut into pieces in a predetermined length.

As described above, for example, the supplier of the first substrate P1 performs the steps S1 to S4 of FIG. 3 (the steps requiring a vacuum processing device), and the manufacturer of the TFT (electronic component) performs the steps of FIG. 3. The steps from S5 to step S24 in FIG. 4 (steps that do not require a vacuum processing device), thereby reducing the burden on the manufacturer of electronic components, and can easily manufacture high-precision electronic components. That is, in order to manufacture a high-precision electronic component, although it is necessary to form at least a part of the laminated structure 52 constituting the electronic component in a vacuum space, since the manufacturer of the electronic component does not need to perform film formation in a vacuum space, Can reduce the burden on manufacturers of electronic components. In addition, since the manufacturer of an electronic component only needs to use the first substrate P1 on which the laminated structure 52 is formed to form the electronic component, the number and arrangement of the electronic components can be arbitrarily determined to manufacture the electronic components, and the thin-film components constituting the electronic components Increased freedom in the configuration of crystals or the design of wiring, bus lines, etc. Moreover, even a manufacturer who does not have many vacuum deposition equipment, coating equipment, or sputtering equipment necessary for forming films of all layers constituting an electronic component can easily manufacture high-performance electronic components.

(Manufacturing method of top contact TFT)

FIGS. 7 and 8 are flowcharts showing an example of the steps of a method for manufacturing a top-contact TFT. FIGS. 9A to 9D and 10A to 10C show the manufacturing process of a TFT manufactured by the steps shown in FIGS. 7 and 8. Section view. First, in step S31 of FIG. 7, as shown in FIG. 9A, a peeling layer 70 is formed on the first substrate P1. This step is the same as step S1 in FIG. 3.

Next, as shown in FIG. 9B, a laminated structure 72 is formed on the first substrate P1 (first step). This laminated structure 72 is made of a metal-based material (conductive material such as Cu, Al, Mo, Au, etc.) or ITO (conductive material) deposited on the first substrate P1 (on the release layer 70) with a predetermined thickness. Thin film (first conductive layer) 72a, thin film (semiconductor layer) 72b1 of a semiconductor (materials showing semiconductor characteristics such as IGZO, ZnO, silicon, thick pentabenzene, etc.) stacked on the first conductive layer 72a with a predetermined thickness, with a predetermined thickness Thin film (insulating layer) 72b2 of an insulating material (insulating material such as SiO ₂ and Al ₂ O ₃ ) deposited on the semiconductor layer 72b1, a metal-based material (Cu, Al, Mo) deposited on the insulating layer 72b2 with a predetermined thickness A conductive material such as Au, Au) or a thin film (second conductive layer) 72c of ITO (conductive material). The semiconductor layer 72b1 and the insulating layer 72b2 constitute a functional layer 72b. In addition, here, too, the base material of the first substrate P1 is preferably a polyimide resin, an extremely thin glass, or an extremely thin glass having good heat resistance in consideration of the heating (100 to 300 ° C) during film formation. Metal foil (copper foil, stainless steel foil, aluminum foil rolled into a thickness of several tens to several hundreds of μm), etc. In addition, as the release layer 70, a fluorine-based material, an alkali-soluble release agent, a release agent based on an inorganic material, a silicon release agent, or the like can be used as in the release layer 50 described in FIGS. 3 to 6 described above.

Therefore, first, in step S32, a first conductive layer 72a is formed (stacked) on the first substrate P1 (the peeling layer 70). Next, in step S33, a semiconductor layer 72b1 is formed (deposited) on the first conductive layer 72a, and in step S34, an insulating layer 72b2 is further formed (deposited), thereby forming a functional layer 72b. Thereafter, in step S35, a second conductive layer 72c is formed (deposited) on the functional layer 72b. Thereby, a laminated structure 72 is formed on the first substrate P1. The first conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the second conductive layer 72c are continuously formed on the first substrate P1 by using the film forming apparatus 10 described above. In addition, the first conductive layer 72a functions as an electrode layer of the source electrode and the drain electrode and a wiring layer of the wiring attached to the source electrode and the drain electrode. Features. The second conductive layer 72c functions as an electrode layer of the gate electrode and a wiring layer of wiring attached to the gate electrode. In the above configuration, when the first substrate P1 or the first conductive layer 72a is made of a metal-based material (for example, Cu), when the semiconductor layer 72b1 is formed on the first conductive layer 72a, it can be heated far higher than a resin such as PET. The temperature of the glass transition temperature of the film (for example, 200 ° C or higher), so the orientation (crystallization) of organic semiconductor materials or oxide semiconductor materials can be performed well, and the electrical characteristics (such as mobility) of the TFT can be improved in a leap. . Further, at least the interface between the first conductive layer 72a and the semiconductor layer 72b1 and the interface between the insulating layer 72b2 and the second conductive layer 72c are first flattened to a level of ultra-micron or less, which also helps to improve the electrical characteristics of TFT .

Thereafter, the first substrate P1 on which the laminated structure 72 is formed is subjected to an etching process using a lithography method, and as shown in FIG. 9C, a gate electrode and wirings attached thereto are formed on the second conductive layer 72c. (Step 1). In addition, only the gate electrode is shown in FIG. 9C.

Brief description is made of the etching process using this lithography method. First, in step S36, a photoresist layer is formed on the second conductive layer 72c. The photoresist layer is formed by, for example, step S5 of FIG. 3, the transfer of a dried film resist, or the application of a resist solution. Next, in step S37, a predetermined pattern (a pattern of the gate electrode and wiring attached thereto) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S38 (the first substrate P1 is immersed in TMAH or the like for development). liquid). Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S39, the first substrate P1 on which the laminated structure 72 is formed is immersed in an etching solution (for example, second iron oxide), and an etching process is performed in which a photoresist layer having a predetermined pattern is used as a mask. A gate electrode or the like is formed on the second conductive layer 72c. Next, in step S40, the photoresist layer on the second conductive layer 72c is peeled off, and the first substrate P1 is cleaned. Thereby, the laminated structure 72 shown in FIG. 9C is manufactured. In addition, the cleaning of the first substrate P1, It can also be washed with an alkaline cleaning solution such as NaOH.

Next, in step S41 of FIG. 8, the adhesive layer 54 is formed by applying an adhesive on the surface side (layered structure 72 side) of the first substrate P1 on which the laminated structure 72 is formed.

Next, the second conductive layer 72c is positioned on the second substrate P2 side, the first substrate P1 and the second substrate P2 are temporarily brought into close contact or close contact with each other, and the laminated structure 72 formed on the first substrate P1 is transferred. To the second substrate P2 (second step). This transfer is performed by the laminating device 30 as described above. That is, the first substrate P1 laminated from the surface side of the first substrate P1 in the order of the release layer 70, the laminated structure 72, and the adhesive layer 74 is set in a roll shape on the supply roll of the laminate device 30. 32. The lamination device 30 can transfer the laminated structure 72 formed on the first substrate P1 to the second substrate P2. At this time, the peeling layer 70 for easily removing the laminated structure 72 from the first substrate P1 is not transferred to the second substrate P2 side but remains on the first substrate P1 side.

First, as shown in FIG. 10A, the adhesive layer 74 formed on the laminated structure 72 is adhered to the surface of the second substrate P2 (step S42). As shown in FIG. 10B, the laminated structure 72 is removed from the first layer by the release layer 70. 1 The substrate P1 is peeled (step S43). Thereby, the laminated structure 72 on the first substrate P1 is transferred to the second substrate P2. By this transfer, the laminated structure 72 is formed on the second substrate P2 in an inverted state. That is, the second conductive layer 72c, the functional layer 72b, and the first conductive layer 72a constituting the laminated structure 72 are laminated on the second substrate P2 from the surface side of the second substrate P2 in the aforementioned order, and the first conductive layer 72a is exposed. . The second substrate P2 on which the laminated structure 72 is transferred by the laminating device 30 is taken up by the recovery roll 40. When the release layer 70 has been peeled from the first substrate P1 and transferred to the second substrate P2 side, the release layer 70 is removed and the second substrate P2 is cleaned. Since the release layer 70 is soluble, it can be removed from the first conductive layer by a solvent. 72a removed.

Next, the recovery roll 40 is used as a supply roll, and the second substrate P2 carried out from the supply roll is subjected to an etching process using a lithography method. As shown in FIG. 10C, a source electrode is formed on the first conductive layer 72a. And the wiring attached to the drain electrode, the source electrode, and the drain electrode (step 4). Note that FIG. 10C shows only the source electrode and the drain electrode.

The formation of source electrodes and the like by an etching process using a photolithography method will be briefly described. First, in step S44, a photoresist layer is formed on the surface side (the first conductive layer 72a side) of the second substrate P2. The photoresist layer is formed by drying a film resist or coating as described in step S5 in FIG. 3. Next, in step S45, a predetermined pattern (a pattern of the source electrode and the drain electrode and the wiring attached to the source electrode and the drain electrode) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S46. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S47, the second substrate P2 on which the laminated structure 72 is formed is immersed in an etching solution (for example, second iron oxide, etc.), and the photoresist layer having a predetermined pattern is etched as a photomask. A source electrode, a drain electrode, and the like are formed on the first conductive layer 72a. Next, in step S48, the photoresist layer on the first conductive layer 72a is peeled off, and the second substrate P2 is cleaned. Through such a step, a top-contact TFT as shown in FIG. 10C is formed on the second substrate P2. In addition, the second substrate P2 may be cleaned by using an alkaline cleaning solution such as NaOH.

In the steps described above, the supplier of the first substrate P1 may also perform at least steps S31 to S35 of FIG. 7 (FIGS. 9A and 9B), and the steps after the steps performed by the supplier are performed by the electronic components. Manufacturers carry on. For example, steps S31 to S35 in FIG. 7 may be performed by a supplier, and steps S36 to S48 in FIG. 7 may be performed by a manufacturer (FIGS. 9C to 10D).

As described above, for example, the supplier of the first substrate P1 performs the steps from step S31 to step S35 in FIG. 7, and the TFT (electronic component) manufacturer performs the steps from step S36 to step S48 in FIG. 8. This can reduce the burden on the manufacturers of electronic components, and can easily manufacture high-precision electronic components. That is, in order to manufacture a high-precision electronic component, although it is necessary to form at least a part of the laminated structure 72 constituting the electronic component in a vacuum space, the manufacturer of the electronic component does not need to perform the film formation in the vacuum space. Can reduce the burden on manufacturers of electronic components. In addition, since the manufacturer of an electronic component only needs to use the first substrate P1 on which the laminated structure 72 is formed to form the electronic component, the number and arrangement of the electronic components can be arbitrarily determined to manufacture the electronic components, and the thin-film electrical components constituting the electronic components Increased freedom in the configuration of crystals or the design of wiring, bus lines, etc. Moreover, even a manufacturer who does not have many vacuum deposition equipment, coating equipment, or sputtering equipment necessary for forming films of all layers constituting an electronic component can easily manufacture high-performance electronic components. Similarly in this embodiment, the first substrate P1 (the supporting substrate of the laminated structure 72) manufactured through steps S31 to S35 in FIG. 7 is rolled into a roll shape as an intermediate product. It is supplied to manufacturers of electronic components in a state of being cut into pieces in a predetermined length.

[Modification of the first embodiment]

The above-mentioned first embodiment may be modified as described below.

(Modification 1)

In the first modification, the top-contact TFT is manufactured by forming a multilayer structure while applying an etching process using a lithography method. FIG. 11 and FIG. 12 are flowcharts showing an example of steps of a method for manufacturing a top-contact TFT according to Modification 1. FIGS. 13A to 13F and FIGS. 14A to 14F show the steps shown in FIGS. 11 and 12. A cross-sectional view of the manufacturing process of a manufactured TFT. First, at step S61 in FIG. 11, as shown in FIG. 13A, a peeling layer 80 is formed on the first substrate P1. The step of forming the release layer 80 is the same as step S1 in FIG. 3.

Next, in step S62, shown in Figure 13B, is formed of an insulating material deposited to a predetermined thickness (SiO _2, Al ₂ O _3, etc.) of the film (insulating layer) 82 on the first board P1 (over the peeling layer 80) . This insulating layer 82 is formed on the first substrate P1 by using the film forming apparatus 10 described above. This insulating layer 82 has a function as a passivation, and also has a function as an etching stopper.

Next, in step S63, as shown in FIG. 13C, a thin film of a metal-based material (conductive material such as Cu, Al, Mo, etc.) (a 1 conductive layer) 84a (first step). The first conductive layer 84a functions as an electrode layer of a source electrode and a drain electrode and a wiring layer attached to the source electrode and the drain electrode. This first conductive layer 84a is formed on the first substrate P1 by using the film forming apparatus 10 described above.

Thereafter, an etching process using a lithography method is applied, and as shown in FIG. 13D, a source electrode and a drain electrode and wirings attached to the source electrode and the drain electrode are formed on the first conductive layer 84a. step). At this time, etching of the peeling layer 80 is prevented by the insulating layer 82 which also functions as an etching stopper. Note that FIG. 13D shows only the source electrode and the drain electrode.

The formation of source electrodes and the like by an etching process using a lithography method will be briefly described. First, in step S64, a photoresist layer is formed on the first conductive layer 84a. The photoresist layer is formed by drying a film resist or coating as described in step S5 in FIG. 3. Next, in step S65, a predetermined pattern (the pattern of the source electrode and the drain electrode and the wiring attached to the source electrode and the drain electrode) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S66. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S67, the first substrate P1 on which the first conductive layer 84a is formed is immersed in an etching solution (for example, second iron oxide, etc.), and the photoresist layer on which a predetermined pattern is formed is etched as a photomask A source electrode, a drain electrode, and the like are formed on the first conductive layer 84a. Next, in step S68, the photoresist layer on the first conductive layer 84a is peeled off, and the first substrate P1 is cleaned.

Next, in step S69, as shown in FIG. 13E, a thin film (semiconductor layer) 84b1 (first 1 step). This semiconductor layer 84b1 is formed on the first substrate P1 by using the film forming apparatus 10 described above. Next, an etching process using a lithography method is performed. As shown in FIG. 13F, the semiconductor layer 84b1 is processed (first step). That is, in step S70, a photoresist layer is formed on the semiconductor layer 84b1. The photoresist layer is formed by drying a film resist or coating as described in step S5 in FIG. 3. Next, in step S71, a predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S72. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S73, the first substrate P1 is immersed in an etching solution (for example, hydrogen fluoride, etc.), and the photoresist layer formed with a predetermined pattern is etched as a photomask to process the semiconductor layer 84b1. Thereby, as shown in FIG. 13F, the semiconductor layer 84b1 located at least between the source electrode and the drain electrode remains, and an unnecessary semiconductor layer 84b1 can be removed except for this. Next, in step S74, the photoresist layer is peeled off, and the first substrate P1 is cleaned.

Thereafter, in step S75 of FIG. 12, as shown in FIG. 14A, a thin film of an insulating material (SiO ₂ , Al ₂ O _3, etc.) deposited with a predetermined thickness is formed on the surface side (semiconductor layer 84b1 side) of the first substrate P1. (Insulating layer) 84b2 (first step). This insulating layer 84b2 is formed on the first substrate P1 by using the film forming apparatus 10 described above. The semiconductor layer 84b1 and the insulating layer 84b2 constitute a functional layer 84b.

Next, in step S76, as shown in FIG. 14B, a thin film of a metal-based material (conductive material such as Cu, Al, Mo, etc.) (a conductive material such as Cu, Al, Mo, etc.) stacked in a predetermined thickness is formed on the first substrate P1 (above the insulating layer 84b2), as shown in FIG. 14B. 2 conductive layer) 84c. This second conductive layer 84c is formed on the first substrate P1 by using the film-forming apparatus 10 described above. The second conductive layer 84c functions as an electrode layer of the gate electrode and a wiring layer of wiring attached to the gate electrode. The first conductive layer 84a, the functional layer 84b, and the second conductive layer 84c constitute a laminated structure 84.

Next, an etching process using a lithography method is performed. As shown in FIG. 14C, a gate electrode and wirings attached thereto are formed on the second conductive layer 84c (first step). Note that only the gate electrode is shown in FIG. 14C. In the step shown in FIG. 14C, the first substrate P1 on which the second conductive layer 84c is formed is subjected to an etching process using a photolithography method to form a gate electrode and wirings attached thereto. Thereby, a TFT is formed on the first substrate P1.

The formation of gate electrodes and the like by an etching process using a lithography method will be briefly described. First, in step S77, a photoresist layer is formed on the second conductive layer 84c. The photoresist layer is formed by drying a film resist or coating as described in step S5 in FIG. 3. Next, in step S78, a predetermined pattern (a pattern of the gate electrode and the wiring and the like attached thereto) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S79. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S80, the first substrate P1 is immersed in an etching solution (for example, second iron oxide, etc.), and an etching process is performed using a photoresist layer formed with a predetermined pattern as a photomask on the second conductive layer. 84c forms the gate electrode and its attached wiring. Next, in step S81, the photoresist layer on the second conductive layer 84c is peeled off, and the first substrate P1 is cleaned. The laminated structure 84 is formed on the first substrate P1 by the steps from step S63 in FIG. 11 to step S81 in FIG. 12.

Next, in step S82, as shown in FIG. 14D, an adhesive is applied on the first substrate P1 on which the laminated structure 84 is formed, that is, on the second conductive layer 84c to form an adhesive layer 86. This adhesive layer 86 is used to allow the laminated structure 84 formed on the first substrate P1 to be easily transferred (adhered) to the second substrate P2. As this adhesive, for example, a UV-curable resin can be used. In this case, ultraviolet rays are irradiated to the adhesive layer 86 after the adhesive layer 86 is formed.

Next, in step S83, the first substrate P1 and the second substrate P2 are temporarily approached or closely contacted with each other such that the second conductive layer 84c is positioned on the second substrate P2 side, and are formed on the first substrate as shown in FIG. 14E The laminated structure 84 on P1 is transferred to the second substrate P2 (second step). This transfer is performed by the laminating device 30 described above. That is, a roll of the first substrate P1 laminated from the surface side of the first substrate P1 in the order of the release layer 80, the insulating layer 82, the laminated structure 84, and the adhesive layer 86 is used as a supply roll of the laminated device 30. The tube 32 is used, whereby the laminated structure 84 formed on the first substrate P1 can be transferred to the second substrate P2. Thereby, the laminated structure 84 is formed on the second substrate P2 in an inverted state. That is, the second conductive layer 84c, the functional layer 84b, and the first conductive layer 84a constituting the laminated structure 84 are laminated on the second substrate P2 in the aforementioned order from the surface side of the second substrate P2. At this time, the release layer 80 does not transfer to the second substrate P2 side but remains on the first substrate P1 side. The second substrate P2 on which the laminated structure 84 is transferred by the laminating device 30 is taken up by the recovery roll 40. Through such a step, a top-contact TFT as shown in FIG. 14E is formed on the second substrate P2.

In addition, after the laminated structure 84, that is, the TFT, is transferred on the second substrate P2, the insulating layer 82 may be processed as shown in FIG. 14F by applying an etching process using a lithography method (fourth step). . By the steps shown in FIG. 14F, the insulating layer 82 at least between the source electrode and the drain electrode remains, and the insulating layer 82 is not required except for removing the insulating layer 82.

In the steps described above, the supplier of the first substrate P1 may also perform at least the steps of step S61 to step S81 of FIG. 12 (FIGS. 13A to 14C), and the steps after the steps performed by the supplier are performed by Manufacturers of electronic components. For example, the supplier may perform steps S61 in FIG. 11 to step S82 in FIG. 12, and the manufacturer may perform steps in step S83 in FIG. 12 (FIG. 14E).

As described above, for example, the supplier of the first substrate P1 performs the steps of step S61 in FIG. 11 to step S82 in FIG. 12, and the manufacturer of the electronic component performs at least the step in step S83 of FIG. 12. Electronic component manufacturers can afford high precision electronic components.

(Modification 2)

Although the insulating layer 82 is formed between the peeling layer 80 and the first conductive layer 84a in the first modification, the insulating layer 82 is not formed in the second modification. That is, in the second modification, the step of step S62 in FIG. 11 is not performed. Therefore, the step of step S63 is performed after the step of step S61 of FIG. 11 is passed. For example, a passivation layer may not be provided, and when there is no possibility that the peeling layer 80 is etched, the insulating layer 82 may not be provided between the peeling layer 80 and the first conductive layer 84a. In addition, in this case, since the insulating layer 82 is not originally formed, there is no need to apply an etching treatment using a lithography method to the insulating layer 82 as shown in FIG. 14F.

(Modification 3)

In addition, the supplier of the first substrate P1 may provide the first substrate P1 on which the alignment mark Ks is formed to the manufacturer. This alignment mark Ks is a reference mark for aligning (aligning) a predetermined pattern of the exposed area W exposed on the substrate with the substrate. By detecting this alignment mark Ks optically with a photographing device with a microscope, the position of the substrate (the substrate Position in the long side direction, position in the short side direction, tilted state) or distortion state in the plane of the substrate. This alignment mark Ks is formed, for example, at a certain interval along the substrate longitudinal direction (long direction) at both end sides in the width direction of the substrate.

For example, the supplier of the first substrate P1 can also use the lithography method as shown in FIG. 15 after forming a laminated structure 52 (72) on the first substrate P1 as shown in FIG. 5B or FIG. 9B. In the etching process, an alignment mark Ks is formed on the second conductive layer 52c (72c) (third step). Then, the first substrate P1 on which the alignment mark Ks is formed may be used to perform the steps subsequent to FIG. 5C (FIG. 9C). In this case, since the first conductive layer 52a (72a) becomes the surface side of the second substrate P2 and the second conductive layer 52c (72c) becomes the deep portion side of the second substrate P2 by transfer, the formed alignment is formed. The mark Ks is hidden by the first conductive layer 52a (72a). Therefore, after the transfer (for example, when the source electrode and the drain electrode are formed), an etching process using a lithography method may be used, and as shown in FIG. 16, the alignment mark Ks may be removed to face The first conductive layer 52a (72a) in the region is provided with a window portion 90. The window portion 90 may be provided by forming the first conductive layer 52a (72a) in a region not facing the alignment mark Ks. Thereby, the step of removing the first conductive layer 52a (72a) in the area facing the alignment mark Ks can be omitted. In addition, the functional layer 52b (72b) is made of a transmissive material, so although the alignment mark Ks can be photographed with an optical alignment system such as a microscope, the functional layer 52b (72b) is non-transmissive In the case of a material configuration, it is preferable that a window portion 90 is also provided in the functional layer 52b (72b). The window portion 90 is an opening portion formed to capture the alignment mark Ks. The alignment mark Ks may be formed on the first conductive layer 52a (72a), and the window portion 90 may be formed on the second conductive layer 52c (72c).

When the first conductive layer 52a (72a) has been formed, an etching process using a lithography method is used to form an alignment mark Ks or a window portion 90 on the first conductive layer 52a (72a). When the second conductive layer 52c (72c) is formed, an etching process using a lithography method is used to form a window portion 90 or an alignment mark Ks on the second conductive layer 52c (72c). In particular, in the above-mentioned modification examples 1 and 2, since the laminated structure 84 is gradually formed while performing an etching process using a lithography method, alignment can also be formed together in the formation of the laminated structure 84. Mark Ks and window 90.

In addition, the supplier of the first substrate P1 has previously grasped the wiring patterns in the component area on the circuit board for electronic components (for example, manual operations such as the shape, arrangement, and size of larger patterns such as ground bus lines and power bus lines). In this case, it is also possible to form the alignment mark Ks or the window portion 90 at the same time by forming the first conductive layer 52a (72a) or the second conductive layer 52c (72c) by an etching process using a lithography method, and then forming the same. Wiring pattern. Furthermore, when the supplier of the first substrate P1 has previously grasped the area where the wiring pattern and the semiconductor element (TFT) are formed (or the area where the TFT is not formed at all), the functional layer may be selectively deposited in the area where the TFT is formed. 52b (72b) semiconductor layer, and an insulating layer as a functional layer 52b (72b) is selectively deposited in a region where no TFT is formed at all. In this case, in order to make the thickness of the entire functional layer 52b (72b) as uniform as possible, the semiconductor layer and the insulating layer may be adjusted to have approximately the same thickness.

(Modification 4)

FIG. 17 is a diagram showing a configuration of a lamination device 30a in a modification 4. FIG. In the fourth modification, the same reference numerals are given to the same configurations as those in the first embodiment described above, and descriptions thereof are omitted. In the modification 4, a guide roller GR6a having a larger radius than the guide roller GR6 is provided instead of the guide roller GR6. The laminating device 30a is provided with a die coater head DCH that applies a heat-curing adhesive to the second substrate P2 wound around the guide roller GR6a and is cured by heat. That is, in Modification 4, the adhesive is applied to the second substrate P2 side instead of the first substrate P1 side, thereby forming the adhesive layer 54 (74). Therefore, the adhesive layer 54 (74) is not provided on the first substrate P1. borrow The area on the second substrate P2 coated with the thermosetting adhesive by the die coating head DCH is supported by the circumferential surface of the guide roller GR6a. This die coating head DCH applies the thermosetting adhesive to the second substrate P2 in a wide and uniform manner. Thereby, the laminated structure 52 (72) formed on the 1st board | substrate P1 can be transferred to the 2nd board | substrate P2 by the pressure-contact heating roller 36.

Specifically, the pressure-contact heating roller 36 sandwiches the first structure from both sides in such a manner that the laminated structure 52 (72) is located on the second substrate P2 side and is in contact with the thermosetting adhesive applied on the second substrate P2. The substrate P1 and the second substrate P2 are brought into close contact with each other and heated at the same time. Since the heat-curing adhesive is hardened by this heating, an adhesive layer 54 (or 74) is formed, and the laminated structure 52 (72) and the second substrate P2 are firmly adhered, and the laminated structure formed on the first substrate P1 is formed. The body 52 (72) is transferred to the second substrate P2. In addition, the first substrate P1 and the second substrate P2 are separated from each other by the pressure-bonding heating roller 36.

(Modification 5)

FIG. 18 is a diagram showing a configuration of a lamination device 30b in a fifth modification. In the fifth modification, the same reference numerals are given to the same components as those in the first embodiment described above, and descriptions thereof are omitted. In the fifth modification, instead of the crimping heating roller 36, a crimping roller 36b that is only crimped without heating is provided, and a guide roller GR6b having a larger radius than the guide roller GR6 is provided instead of the guide roller GR6. This crimping roller 36b has a roller R and a cylindrical DRS having a larger radius than the roller R. Therefore, the first substrate P1 and the second substrate P2, which are held in close contact with each other by the roller R and the cylindrical DRS, are transported along the circumferential surface of the cylindrical DRS in a state of being superimposed on each other, and thereafter, guided by the guide The guide rollers GR7 and GR8 are separated from each other. The first substrate P1 is guided by the recovery roll 38 by the guide roller GR7, and the second substrate P2 is guided by the recovery roll 40 by the guide roller GR8.

A second substrate P2 is provided on the laminating device 30b and wound around the guide roller GR6b. Die-coating head DCH1 that applies a UV-curing adhesive that hardens due to UV light. That is, in Modification 5, the adhesive is applied to the second substrate P2 side instead of the first substrate P1 side, thereby forming the adhesive layer 54 (74). Therefore, the adhesive layer 54 (74) is not provided on the first substrate P1. The area on the second substrate P2 coated with the UV curing adhesive by the die coating head DCH1 is supported by the circumferential surface of the guide roller GR6b. This die coating head DCH1 applies a wide range of UV curing adhesives to the second substrate P2 and applies the same. In addition, the lamination device 30b is provided with an irradiation device UVS. The irradiation device UVS has a plurality of first substrates P1 and second substrates P2 which are crimped by the crimping roller 36b and irradiates UV (ultraviolet) light to the UV curing adhesive before separation The ultraviolet irradiation source 94. Thereby, the laminated structure 52 (72) formed on the 1st board | substrate P1 can be transferred to the 2nd board | substrate P2 by the pressure bonding roller 36b.

Specifically, the roller R and the cylinder DRS of the crimping roller 36b are formed in such a manner that the laminated structure 52 (72) is located on the second substrate P2 side and is in contact with the UV curing adhesive applied on the second substrate P2. The first substrate P1 and the second substrate P2 are sandwiched and held in close contact with each other. Thereafter, the irradiation device UVS irradiates UV light onto the first substrate P1 and the second substrate P2 that are wound around the cylindrical DRS in a state of being superimposed on each other and transported. The UV curing adhesive located between the first substrate P1 and the second substrate P2 is hardened by the irradiation of the UV light, so that an adhesive layer 54 (or 74) is formed, and the laminated structure 52 (72) and the second substrate P2 are coated. Firmly followed. After this UV irradiation, the first substrate P1 and the second substrate P2 are separated from each other by the guide rollers GR7 and GR8. Thereby, the laminated structure 52 (72) formed on the first substrate P1 is transferred to the second substrate P2.

[Second Embodiment]

In the second embodiment, a specific method of manufacturing a pixel circuit of an organic EL display will be described. FIG. 19 shows an example of a pixel circuit of a light-emitting pixel of an organic EL display of an active matrix method. FIG. 20 is a diagram showing a specific structure of the pixel circuit shown in FIG. 19. The pixel circuit includes a TFT, a capacitor C, and an organic light emitting diode (OLED: Organic Light Emitting Diode). The source electrode S and the drain electrode D of the TFT and its attached wiring L1, one of the electrodes C1 of the capacitor C, and the pixel electrode E connected to the cathode of the OLED are formed on the first conductive layer 102 of the multilayer structure 100. The gate electrode G of the TFT and the other electrode C2 of the attached wiring L2 and the capacitor C are formed on the second conductive layer 104 of the multilayer structure 100. An electrode C2 of the capacitor C is connected to a ground GND (ground). An electroless-plated contact M is provided at a position where the wiring L1 formed on the first conductive layer 102 and the wiring L2 formed on the second conductive layer 104 must be connected. In addition, in FIG. 20, in order to distinguish the first conductive layer 102 from the second conductive layer 104, the first conductive layer 102 is indicated by diagonal lines for convenience of explanation.

In this second embodiment, a method for manufacturing a pixel circuit having a top-contact TFT will be described. 21 and 22 are flowcharts showing an example of steps in a method of manufacturing a pixel circuit.

First, after steps S101 to S105, as shown in FIG. 23, the release layer 106, the first conductive layer 102, the semiconductor layer 108, the insulating layer 110, and the second conductive layer are sequentially removed from the surface side of the first substrate P1. The layer 104 is formed on the first substrate P1. The steps from step S101 to step S105 are the same as the steps from step S31 to step S35 in FIG. 7. The semiconductor layer 108 and the insulating layer 110 constitute a functional layer 112, and the first conductive layer 102, the functional layer 112 (semiconductor layer 108 and the insulating layer 110), and the second conductive layer 104 constitute a laminated structure 100. In the second embodiment, the first conductive layer 102 and the second conductive layer 104 are formed of Cu (copper), the semiconductor layer 108 is formed of ZnO, which is an oxide semiconductor, and the insulating layer 110 is formed of SiO ₂ .

Next, by an etching process using a lithography method, as shown in FIG. 24 and FIG. 25, a predetermined pattern is formed on the second conductive layer 104 (the above-mentioned gate electrode G, wiring L2, and capacitor C Pattern of electrode C2). Note that in FIG. 24, only the gate electrode G and the wiring L2 are shown in the second conductive layer 104. In FIG. 25, in order to distinguish the first conductive layer 102 from the second conductive layer 104, the first conductive layer 102 is shown with diagonal lines.

The formation of gate electrodes and the like by an etching process using a lithography method will be briefly described. First, in step S106, a photoresist layer is formed on the second conductive layer 104. Next, in step S107, a predetermined pattern (the pattern of the gate electrode G, the wiring L1, and the electrode C2) is exposed to the applied photoresist layer using ultraviolet rays, and development is performed in step S108. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S109, the first substrate P1 is immersed in an etching solution that oxidizes the second iron, and an etching process is performed using a photoresist layer having a predetermined pattern as a photomask to form a gate on the second conductive layer 104. Electrode G, etc. Next, in step S110, the photoresist layer is peeled off, and the first substrate P1 is cleaned. The steps from step S106 to step S110 are the same as steps S36 to S40 of FIG. 7. In the area where the second conductive layer 104 is removed by this etching treatment, the functional layer 112 is exposed.

Thereafter, in step S111, the first substrate P1 is immersed in an etching solution of hydrogen fluoride, and the functional layer 112 is also etched (processed) as shown in FIG. 24. Since the functional layer 112 is exposed in the region after the second conductive layer 104 is removed by the etching process in step S109, the functional layer 112 in the region after the second conductive layer 104 is removed is removed by the etching process in step S111. .

Thereafter, in step S112, the adhesive layer 114 is formed by applying an adhesive to the surface side (second conductive layer 104 side) of the first substrate P1 on which the laminated structure 100 is formed. Next, in step S113, the first substrate P1 and the second substrate P2 are temporarily brought into close contact with or in close contact with each other so that the second conductive layer 104 is positioned on the second substrate P2 side. As shown in FIG. 26, they will be formed on the first substrate. The laminated structure 100 of P1 is transferred to the second substrate P2. This transfer is performed by the laminating device 30. The steps S112 and S113 are the same as steps S41 to S43 in FIG. 8.

Next, by an etching process using a photolithography method, a predetermined pattern is formed on the first conductive layer 102 as shown in FIGS. 27 and 28 (the source electrode S and the drain electrode D described above, the electrodes of the wiring L1, and the capacitor C). C1, and the pattern of the pixel electrode E). In FIG. 27, only the source electrode S, the drain electrode D, and the wiring L1 are shown in the first conductive layer 102. In addition, in FIG. 28, in order to distinguish the first conductive layer 102 from the second conductive layer 104, the first conductive layer 102 is shown by oblique lines.

The formation of source electrodes and the like by an etching process using a photolithography method will be briefly explained, and a photoresist layer is formed on the surface side (the first conductive layer 102 side) of the second substrate P2 in step S114 of FIG. 22. Next, in step S115, a predetermined pattern (the pattern of the source electrode S, the drain electrode D, the wiring L1, the electrode C1, and the pixel electrode E) is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S116. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S117, the second substrate P2 is immersed in an etching solution that oxidizes the second iron, and the photoresist layer formed with a predetermined pattern is etched as a photomask to form a source electrode on the first conductive layer 102. The electrode S, the drain electrode D, and the like. At this time, an opening portion of the contact hole H for forming the electroless plated contact M is also formed in the first conductive layer 102. Next, in step S118, the photoresist layer on the first conductive layer 102 is peeled off, and the second substrate P2 is cleaned. The steps from step S114 to step S118 are the same as steps S44 to S48 in FIG. 8 except that the contact hole H is formed.

Next, as shown in FIG. 29, by using an etching process using a photolithography method, the functional layer 112 (semiconductor layer 108 and insulating layer 110) of the contact hole H portion is etched. That is, in step S119, a photoresist layer is formed on the surface side (the first conductive layer 102 side) of the second substrate P2. Next, in step S120, a predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S121. Thereby, a predetermined pattern is formed on the photoresist layer. Next, in step S122, by 2 The substrate P2 is immersed in an etching solution of hydrogen fluoride, and the photoresist layer formed with a predetermined pattern is etched as a photomask, and the functional layer 112 of the contact hole H portion is also etched. Thereby, the contact hole H is completed.

Thereafter, in step S123, an electroless plating process is performed on the contact hole H portion. As shown in FIG. 30, an electroless plated contact M made of, for example, Cu, Cr, NiP, etc. is formed, and the first conductive layer 102 (wiring L1) is formed. It is electrically connected to the second conductive layer 104 (wiring L2). Next, in step S124, the photoresist layer on the second substrate P2 is peeled off, and the second substrate P2 is cleaned. Through the above steps, a pixel circuit as shown in FIG. 20 can be manufactured.

In addition, in the first embodiment (including the modification example) and the second embodiment described above, although the film is processed by the etching process using the lithography method, as long as it is the processing process using the photopatterning method, Any method will do. As the processing process using the photopatterning method, in addition to the etching process using the lithography method, for example, there is a pattern light that irradiates ultraviolet rays while the first substrate P1 on which the laminated structure 52 is formed is immersed in a special liquid The etching of the resist layer covered on the second conductive layer 52c, or the pattern light of ultraviolet rays irradiated with the spot of the laser beam with high NA condensing, is used to directly remove (etch) the peeling of the second conductive layer 52c. Techniques and so on.

In addition, although the TFTs having the bottom gate structure have been described as examples in the above-mentioned first embodiment (including modifications) and the second embodiment, they may also be TFTs having a top-gate structure. The multilayer structures 52 and 72 formed on the first substrate P1 (support substrate) are not limited to thin film transistors (TFTs), and are also useful for the manufacture of electronic components including thin film diodes (TFDs). Furthermore, in the structure of the laminated structure bodies 52, 72, etc., the functional layer 52b (72b) sandwiched between the first conductive layer and the second conductive layer above and below may be a thin film of two or more layers. For example, in a case where the functional layer 52b (72b) is constituted by a laminated layer of a first functional film and a second functional film, The first functional film may be formed on the first substrate P1 in a region corresponding to the entire device region in the same manner, and the second functional film may be selectively formed on a part of the first functional film.

In addition, in the above-mentioned first embodiment (including modifications) and the above-mentioned second embodiment, an insulating layer of a laminated structure is laminated on the surface of the first substrate P1 (supporting base material such as a metal foil) or When the roughness of the surface of the semiconductor layer is expressed by the arithmetic mean roughness Ra value (nm) defined by the JIS standard, the roughness Ra value is determined to be within a range not exceeding the thickness of the insulating layer (or semiconductor layer) of the layer being deposited. . However, in order to ensure long-term stable operation as a TFT, the roughness Ra value of the surface of the first substrate P1 is preferably set to 200 nm or less (ultra micron or less), and more preferably set to a range of 1 nm to tens of nm. The smaller the coarseness Ra value is, the higher the electronic mobility, ON / OFF ratio, and leakage current characteristics, which are the electrical characteristics of the TFT. Although it is possible to set the roughness Ra value to 1 nm, as a practical roughness Ra value, it may be about several nm. Such a coarseness Ra value can be easily obtained by current surface treatment (grinding) technology. In addition, when the first conductive layer (52a, 72a, 84a, 102) of the laminated structure is formed on the surface of the first substrate P1, the method of flattening the surface of the first substrate P1 by polishing or the like may be used instead. After forming a planarization film on the surface of the first substrate P1, a release layer (50, 70, 80, 106) and a first conductive layer (52a, 72a, 84a, 102) are sequentially formed on the planarization film. . The flattening film is a material such as silicon oxide that fills the recesses on the surface of the first substrate P1 to ease unevenness, has strong etching resistance, and does not degrade during heat treatment during transfer (lamination) or post annealing (SiO ₂ ) based wet material. As materials for such a flattening film, sumefine (registered trademark) manufactured by Sumitomo Osaka Cement Co., Ltd., BISUTOREITA (registered trademark) manufactured by Soda Co., Ltd., COLCOAT (registered trademark) manufactured by COLCOAT Co., Ltd. SOG (Spin On Glass) and other flattening materials sold by Hanwei United or Hitachi Chemical Co., Ltd.

[Modifications of the above embodiments]

Each of the above-mentioned embodiments (including the modification examples) can be further modified as follows.

[Modification 1]

FIG. 31 shows a schematic configuration of a film forming apparatus 10A in which a laminated structure for electronic components is continuously formed on a first substrate P1 in the same manner as the film forming apparatus 10 of FIG. 1. The film-forming apparatus 10A of FIG. 31 includes a processing chamber 16, a vacuum pump 18, a film-forming rotary cylinder 22, and a plurality of film-forming raw materials (thin-film raw materials) that are arranged around the film-forming rotary cylinder 22 and are continuously stacked. Base materials 20A, 20B, 20C, and guide rollers GR1 to GR3. As described in the previous embodiments or modifications, a two-layer structure including a conductive layer (metal film, ITO film, etc.) and an insulating layer (dielectric film) is formed on the first substrate P1, or the two-layer structure is formed on the first substrate P1. The film has a three-layer structure with a semiconductor layer. Therefore, the substrate 20A disposed around the film-forming rotating cylinder 22 is formed into a conductive layer by evaporation, sputtering, or CVD, and the substrate 20B is formed by evaporation, sputtering, or CVD and the like form an insulating layer on the conductive layer, and the substrate 20C forms a semiconductor layer on the insulating layer by evaporation, sputtering, or CVD. In addition, in the case where a two-layered structure having a conductive layer and an insulating layer is formed on the first substrate P1, it is not necessary to form a film of the base material 20C. Furthermore, depending on the structure of the TFT to be produced, the configuration of the substrate 20B and the substrate 20C may be replaced, and the film may be formed in the order of a conductive layer, a semiconductor layer, and an insulating layer.

As described above, the film forming portions of the substrates 20A, 20B, and 20C of the plurality of thin film materials are sequentially arranged around the film forming rotary cylinder 22, because the first substrate P1 is rolled up by the recovery roll 14 The desired laminated structure is formed on the surface at one time. Therefore, it is not necessary to change the recovery roll 14 to another film forming device, and the productivity is improved. In this case, it is preferable to firstly The film-forming portion of the base material 20B and the film-forming portion of the base material 20C are both set to the same temperature. Further, as the film forming apparatus 10A, an apparatus using a mist deposition method (atomization CVD method) disclosed in, for example, International Publication No. 2013/176222 can be used. In this case, the base material of the film-forming material is contained in a state of ionic or nano particles in a mist sprayed on the surface of the first substrate P1. In addition, if a high-voltage pulse power supply is used to generate an unbalanced atmospheric piezoelectric slurry in the space between the spray nozzle of the mist and the surface of the first substrate P1, it can be performed even if the temperature of the first substrate P1 is about 200 ° C. Good film formation by atomized CVD method, film formation rate is also increased.

[Modification 2]

FIG. 32 is a schematic diagram showing a modification example of the previous transfer method of FIGS. 9 and 10, and members (layers, films, materials, etc.) having the same symbols as those in FIGS. 9 and 10 are given the same symbols. In the example of FIG. 9, as shown in FIG. 9B, after the peeling layer 70, the first conductive layer 72 a, the semiconductor layer 72 b 1, the insulating layer 72 b 2, and the second conductive layer 72 c are sequentially laminated on the first substrate P1, As shown in FIG. 9C, the second conductive layer 72c is etched to form a gate electrode. Although the same is applied to the first substrate P1 shown in FIG. 32, the peeling layer 70, the first conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the second conductive layer 72c are laminated, but in this modification, the semiconductor is not The layer 72b1 is similarly formed on the first conductive layer 72a, and the semiconductor layer 72b1 is selectively formed in a local area corresponding to the channel portion (the gap portion between the source electrode and the drain electrode) of the TFT. In this case, as long as a photoresist layer is formed on the first conductive layer 72a, an opening portion of the resist layer is formed in a region where the semiconductor layer 72b1 is to be formed by a lithography method, and evaporation and sputtering are formed in the opening portion. And CVD can be used to deposit semiconductor materials.

Thereafter, in the modification of FIG. 32, an insulating layer 72b2 is formed so as to cover the first conductive layer 72a and the selectively formed semiconductor layer 72b1. A second conductive layer 72c is formed on the edge layer 72b2. The second conductive layer 72c is processed into a gate electrode (and wiring connected thereto) by an etching process using a photolithography method in the same manner as in FIG. 9C. . In this modification, since the semiconductor layer 72b1 can be selectively formed into a film by limiting the formation region of the TFT, the amount of semiconductor material used can be suppressed. As described above, when the laminated structure 72 formed on the first substrate P1 is transferred to the second substrate P2, the surface of the laminated structure 72 on the first substrate P1 is coated with the adhesive layer 74 in FIG. 9D, but In this modification, the adhesive layer 74 is formed on the second substrate P2 side as shown in FIG. 32. The second substrate P2 in this modification is a structure of a buffer layer P2b such as polyethylene (PE) on the surface area layer of a sheet substrate P2a such as PET or PEN, and the surface of the buffer layer P2b is a transparent seal layer (Silicon Sealant, etc.) ) P2c to form the adhesive layer 74.

As shown in FIG. 32, when the laminated structure 72 on the first substrate P1 side is formed with a selective semiconductor layer 72b1 or a gate electrode, unevenness is generated on the surface of the laminated structure 72 that faces the second substrate P2. Therefore, there may be cases where the close contact with the second substrate P2 is not uniform during the transfer. Therefore, a buffer layer P2b is provided in order to absorb such unevenness. As the buffer layer P2b, those having stability and plasticity are preferred, and when thermocompression bonding is performed during transfer, materials having thermoplasticity such as polyethylene (PE) are preferred. In addition, in this modification, the adhesive layer 74 formed on the buffer layer P2b is a synthetic resin emulsion adhesive EVA (Ethylene Vinyl Acetate) mainly composed of vinyl acetate resin and ethylene-vinyl acetate copolymer resin. By adopting such a configuration, the laminated structure 72 on the first substrate P1 side having unevenness can be accurately transferred to the second substrate P2 side without being damaged by cracks or the like.

[Modification 3]

As shown in FIG. 32 described above, although the transfer layer 74 (EVA) can be transferred well, if the unevenness of the laminated structure 72 on the first substrate P1 side is large, there is a possibility that the transfer layer 74 (EVA) may cause The internal stress generated during the hardening of the EVA) causes fine cracks in the hardened adhesive layer 74 (EVA), particularly on or near the second conductive layer 72c of the laminated structure 72. Therefore, as shown in FIG. 32, a laminated structure 72 (a first conductive layer 72a, a semiconductor layer 72b1, an insulating layer 72b2, and a second conductive layer 72c) is formed on the first substrate P1, as shown in FIG. 33, so as to cover The planarization film FP is formed integrally on the laminated structure 72. This flattening film FP is a material that fills the recessed portions of the laminated structure 72 to ease unevenness, has strong etching resistance, and does not denature during heat treatment during transfer (lamination) or post-annealing, such as silicon oxide (SiO ₂ ) The system is composed of wet materials. As the material of such a flattening film FP, sumisefine (registered trademark) manufactured by Sumitomo Osaka Cement Co., Ltd., BISUTOREITA (registered trademark) manufactured by Soda Co., Ltd., and COLCOAT (registered trademark) manufactured by COLCOAT Co., Ltd. can be used. , SOG (Spin On Glass) and other flattening materials sold by Hanwei United or Hitachi Chemical Co., Ltd. Then, after the material of the planarizing film FP is completely dried or in the middle of drying, the laminated structure 72 having the planarizing film FP is pressure-bonded and transferred onto the adhesive layer 74 (EVA) on the second substrate P2.

The flattening film FP is an inorganic insulating film (or organic insulating film), and has the effect of reducing cracks caused by internal stress when the adhesive layer 74 (EVA) is hardened by directly bonding to the laminated adhesive layer 74 (EVA) Role. In addition, in FIG. 33, although the laminated structure 72 is formed on the first substrate P1, a wet material of the planarizing film FP is applied thereon, but as shown in FIG. 32, it may be formed on the second substrate P2. After the layer 74 (EVA) is adhered, a planarizing film EP is formed on the adhesive layer 74 (EVA). Before the planarizing film FP is dried, the laminated structure 72 on the first substrate P1 is transferred to a flat surface while being heated. Chemical film FP. In addition, in FIGS. 32 and 33, although the laminated structure 72 formed on the first substrate P1 is described, the first conductive layer 72a on the first substrate P1 side becomes the source electrode / drain electrode of the TFT and is connected thereto. Wiring, second on the second substrate P2 side The conductive layer 72c serves as the gate electrode of the TFT and the wiring connected to it, but it may be reversed. That is, the first conductive layer 72a may be used as the gate electrode of the TFT and wiring connected to it, and the second conductive layer 72c may be used as the source electrode / drain electrode of the TFT and wiring connected to it.

[Third Embodiment]

FIGS. 34 to 36 are diagrams showing the manufacturing steps of an electronic device (TFT) in which a part of the manufacturing method of the embodiment shown in FIGS. 23 to 30 is improved. Therefore, the same components as those in FIGS. 23 to 30 among the components (materials) shown in FIG. 34 to FIG. 36 are assigned the same symbols as those in FIGS. 23 to 30. In this embodiment, as shown in FIG. 34A, the first substrate P1 is a sheet-like copper foil of copper (Cu) having a thickness of several tens of μm to several hundreds of μm, and a copper layer is provided on the entire surface with a peeling layer 106 interposed therebetween. (Cu) first conductive layer 102. The first conductive layer 102 is formed by laminating a copper foil having a thickness of several tens of μm or less on the release layer 106. The first conductive layer 102 after lamination is polished so that the arithmetic average roughness Ra value of the surface becomes approximately several nm to several ten nm while reducing its thickness.

Next, as shown in FIG. 34B, an insulating layer 110 is formed on the first conductive layer 102 of the first substrate P1 to function as a gate insulating film of the TFT. This insulating layer 110 is a typical silicon oxide film (SiO ₂ ), and can be formed by selectively removing the silicon oxide film other than the TFT formation area by etching or the like after the first conductive layer 102 is fully formed, or by selectively forming a film. It is formed by a method such as vapor-depositing a silicon oxide film only on the formation region of the TFT from the beginning. Since both the first substrate P1 and the first conductive layer 102 are copper (Cu) having high heat resistance, they can be formed at a high temperature in a vacuum, and the flatness (roughness Ra) of the silicon oxide film can be made good.

Next, as shown in FIG 34C, the insulating layer 110 (SiO ₂₎ 108 is formed on the semiconductor layer. Here, the semiconductor layer 108 is an IGZO (oxide semiconductor) composed of indium, gallium, zinc, and oxygen. The semiconductor layer 108 of IGZO uses indium, gallium, zinc, and oxygen as constituent elements. The ratio of the atomic ratio of indium relative to the total amount of indium and gallium to the total amount of zinc relative to the total amount of indium and gallium and zinc is used. An oxide sintered body having a predetermined atomic ratio is formed as a sputtering device as a sputtering target. Prior to the sputtering step, a comprehensive resist layer is formed on the first substrate P1, and a lithography step (exposure of the pattern and development of the resist) is performed to form a window corresponding to the formation region of the semiconductor layer 108. After the IGZO semiconductor is sputtered by a sputtering device, a step of stripping the resist layer is also performed. Thereby, as shown in FIG. 34C, a semiconductor layer 108 of IGZO is selectively formed on the insulating layer 110.

Next, as shown in FIG. 34D, the source electrode 104 (S) and the drain electrode 104 (D) as the second conductive layer 104 face each other with a certain gap so as to form a channel portion on the semiconductor layer 108. Configuration. Here too, a lithography step is used to form a window portion of a resist layer in a region where the source electrode 104 (S) and the drain electrode 104 (D) are formed, and metal is deposited in the window portion by evaporation or the like. The source electrode 104 (S) and the drain electrode 104 (D). The source electrode 104 (S) and the drain electrode 104 (D) are bonded to the semiconductor layer 108. Therefore, gold (Au) with a large working coefficient is preferred, but other metal materials (aluminum, copper) or A conductive ink material containing silver nano particles or metallic carbon nanotubes. Here, as shown in FIG. 34D, the source electrode 104 (S) and the drain electrode 104 (D) are formed as the first conductive layer 102 extending from the channel portion to the outside of the region of the insulating layer 110, and the source electrode 104 (S ) And the drain electrode 104 (D) are in an electrically conductive state (ohmic contact) with the first conductive layer 102. Through the above steps, a laminated structure 100 (a first conductive layer 102, an insulating layer 110, a semiconductor layer 108, and a second conductive layer 104) is formed on the first substrate P1.

FIG. 35 is a plan view showing a multilayer structure 100 formed on the first substrate P1. Configuration composition diagram. As the electrical characteristics of the TFT, it is expected that both the electron mobility and ON / OFF are high and the leakage current is sufficiently small. In this embodiment, the surface of the first conductive layer 102 serving as the base of the TFT is a smooth surface with a sufficiently small arithmetic mean roughness Ra value. Therefore, the insulating layer 110 and the semiconductor layer 108 formed thereon are also formed into a flat film of uniform thickness, and the flatness of the contact interface between the semiconductor layer 108 and the second conductive layer 104 (source electrode and drain electrode) is also good. To maintain. Thereby, good characteristics of the electronic mobility, ON / OFF ratio, and leakage current are obtained. In addition, since the gap between the source electrode 104 (S) and the drain electrode 104 (D) of the channel portion can be set to a small gap of about several μm, a high-performance TFT that exhibits the characteristics of IGZO semiconductor can be obtained. In addition, as shown in FIG. 35, when the insulating layer 110, the semiconductor layer 108, and the second conductive layer 104 (the source electrode and the drain electrode) are stacked, they must be relatively laminated at a micrometer level. Therefore, an alignment operation must be performed in the lithography step, that is, an alignment mark formed at a specific position on the first substrate P1 (especially the first conductive layer 102) is detected by an alignment sensor in the exposure device. Position to adjust the pattern exposure position.

FIG. 36 is a diagram showing a state where the laminated structure 100 shown in FIGS. 34 and 35 is transferred to the second substrate P2 and further processed. FIG. 36A shows the situation immediately after the laminated structure 100 on the first substrate P1 is transferred to the second substrate P2 by the transfer (lamination) step. In this embodiment, the planarization film FP covering the entire surface of the laminated structure 100 covering the first substrate P1 is formed on the first substrate P1 as described in FIG. 33 before the transfer. As described in 32, a buffer layer P2b of polyethylene resin is prepared on the surface of the sheet substrate P2a of PET to form a second substrate P2 of a predetermined thickness, and an adhesive layer of vinyl acetate resin (EVA) 114 is further formed on the second substrate P2 Formed to a predetermined thickness. During the transfer, the flattening film FP on the first substrate P1 and the adhesive layer (EVA) 114 on the second substrate P2 are fixed at a predetermined pressure. While pressure-bonding, the adhesive layer (EVA) 114 is hardened by heating, and the laminated structure 100 is peeled from the first substrate P1. As a result, as shown in FIG. 36A, on the second substrate P2, the laminated structure 100 is bonded in a state where the first conductive layer (Cu) 102 is exposed on the uppermost surface.

In the state immediately after the transfer shown in FIG. 36A, the residue of the release layer 106 may adhere to the surface of the first conductive layer 102 in some cases. In this case, the surface of the first conductive layer 102 may be washed or polished. In particular, when the thickness of the first conductive layer 102 is about several tens of μm, it may take time to perform subsequent processing (especially etching) of the first conductive layer 102, so it may be placed in a polishing step first. First, the thickness of the first conductive layer 102 is made about several μm. In this embodiment, since the buffer layer P2b, the adhesion layer 114 of EVA, and the flattening film FP are provided, the external TFT can be prevented from being damaged (cracks or broken lines) by external force during polishing of the surface of the first conductive layer 102 . In addition, among the alignment marks used in the lithography step when the TFT laminated structure 100 is manufactured on the first substrate P1, the alignment marks formed at the positions of the plurality of positions of the first conductive layer 102 are fine. In the case of a through hole (such as a circle with a diameter of 20 μm, a rectangle with an angle of 20 μm, etc.), since the first conductive layer 102 is the uppermost as shown in FIG. 36A, it is easy to detect its alignment with the alignment sensor of the exposure device. Quasi-marking. Therefore, when the first conductive layer 102 is processed by the lithography step, the position of the TFTs under the first conductive layer 102 can be accurately specified based on the position of the alignment mark, especially the source electrode 104 (S) and Each position of the drain electrode 104 (D).

A resist layer is coated on the surface of the first conductive layer 102 in FIG. 36A, and the shape of the gate electrode, source electrode, drain electrode, and wiring connected to the electrodes of the TFT is matched by an exposure device. The pattern light is exposed to the resist layer. At this time, the projection position of the pattern light is obtained by detecting an alignment mark formed on the first conductive layer 102 with an alignment sensor of the exposure device. Set precisely. The gate electrode 102G, source electrode 102S, and drain electrode of the first conductive layer 102 are formed as shown in FIG. 36B by developing processing of the exposed resist layer and etching processing of the first conductive layer 102 (Cu). Electrode 102D (and wiring connected to these electrodes). At this time, alignment and patterning are performed to become the source electrode 102S after etching and the source electrode 104 (S) bonded directly to the semiconductor layer 108, the drain electrode 102D, and the drain electrode directly bonded to the semiconductor layer 108. The state where the electrode 104 (D) is joined. Furthermore, the gate electrode 102G after the etching is patterned so as to cover a channel portion (a gap portion between the source electrode 104 (S) and the drain electrode 104 (D)) shown in FIG. 35.

Fig. 37 is a diagram showing an example of a planar arrangement configuration of the TFT of Fig. 36B, and the cross-sectional view taken along the arrow 36B-36B 'in Fig. 37 is shown in Fig. 36B. Although an unnecessary portion of the first conductive layer 102 is removed by an etching process, an insulating planarizing film FP is exposed at the removed portion. In order to manufacture electronic components, when more functional elements (resistors, capacitors, light-emitting elements, light-receiving elements, ICs, etc.) are formed on the second substrate P2, they can be soldered to the wiring portion formed by the first conductive layer 102, etc. Functional components. When the first conductive layer 102 is copper (Cu), an insulating or heat-resistant film for preventing corrosion due to oxidation may be selectively or entirely formed.

As described above, in this embodiment, in order to make the arithmetic average thickness Ra of the first conductive layer 102 of the multilayer structure 100 formed on the first substrate P1 sufficiently small, and to use a vacuum process or a high-temperature process, metal foil is used. (Copper foil) As the first substrate P1, a high-performance TFT can be formed. Therefore, the performance of the electronic components (display panel, touch panel, chip sensor, etc.) manufactured on the flexible second substrate P2 can be improved dramatically in the end. In addition, in this embodiment, although the second conductive layer 104 in the multilayer structure 100 formed on the first substrate P1 is processed into a source electrode and a drain electrode of the TFT, the second conductive layer 104 may also be processed. Processed into a gate electrode. In this case, as long as the TFT (layered structure 100) is manufactured as shown in FIG. In the manufacturing step, the order (upper-lower relationship) between the insulating layer 110 and the semiconductor layer 108 laminated on the first conductive layer 102 may be reversed. That is, a semiconductor layer 108 is initially formed on a predetermined region on the first conductive layer 102, and an insulating layer 110 is formed thereon to a size that completely covers the semiconductor layer 108, and a second conductive layer 104 is formed on the insulating layer 110. The gate electrode may be formed to be partially bonded to the first conductive layer 102.

Furthermore, in the above embodiment, although the first substrate P1 is a sheet-like foil of copper (Cu), and the first conductive layer 102 of the laminated structure 100 is formed on the surface thereof with the release layer 106 interposed therebetween, it may be The copper foil (Cu) sheet foil of the 1st board | substrate P1 was made into the 1st conductive layer 102 of the laminated structure 100. In this case, the first substrate P1 may be rolled into a metal foil (copper foil) having a sufficiently small arithmetic mean thickness Ra value on the surface, and the surface may be further polished as required.

When the first conductive layer 102 is the first substrate P1, the first substrate P1 itself becomes the first conductive layer 102 (electrode, wiring) and is transferred to the second substrate P2 side. Therefore, for example, it is preferable to perform the transfer step. The polishing process for reducing the thickness of the first substrate P1 (the first conductive layer 102) is performed at a later moment. In this way, when the first substrate P1 itself is the first conductive layer 102, the entire multilayer structure (conductive layer, insulating layer, and semiconductor layer) including the first substrate P1 is transferred to the second substrate P2 side. As a result, the first substrate P1 is also transferred to the second substrate P2 side.

Furthermore, in the above embodiment, the laminated structure is formed by a structure in which the first conductive layer 102 (or the first substrate P1 itself) and the second conductive layer 104 sandwich the two layers of the insulating layer 110 and the semiconductor layer 108. However, as shown in FIG. 5 previously, a laminated structure may be formed by a structure in which the first conductive layer 102 (or the first substrate P1 itself) and the second conductive layer 104 are sandwiched only by an insulating layer (or only a semiconductor layer).

In this way, when the first substrate P1 itself is configured as a part of the laminated structure, A component manufacturing method for transferring a first substrate on which at least a part of a laminated structure constituting an electronic component is formed onto a second substrate is performed a first step and a second step. The first step is to prepare a first substrate as A first conductive layer made of a conductive material, a functional layer made of at least one of an insulating material and a semiconductor is formed on the first conductive layer, and a second conductive layer made of a conductive material is formed on the functional layer. In this way, a laminated structure is formed. The second step is to temporarily bring the first substrate and the second substrate into close contact with each other so that the second conductive layer is located on the second substrate side, so as to place the laminated structure including the first substrate. Transfer to the second substrate.

In addition, when the first substrate P1 itself is configured as a part of the multilayer structure, a transfer substrate for transferring at least a part of the multilayer structure constituting an electronic component to the transfer substrate is provided with a conductive material to exert its first effect. 1 a conductive foil (such as a metal foil) that functions as a conductive layer, a functional layer that is formed on the first conductive layer with at least one of an insulating material and a semiconductor, and a second layer that is formed on the functional layer with a conductive material Conductive layer. In this case, the entire transfer substrate is transferred (bonded) to the transferred substrate.

Furthermore, in the embodiment of FIG. 34 described above, although the copper foil is laminated as the first conductive layer 102 via the release layer 106 on the first substrate P1, aluminum (Al) and zinc may be laminated in addition to this. (Zn), molybdenum (Mo), nickel (Ni), tantalum (Ta), tin (Sn), stainless steel (SUS) and other foils or foils made of these alloys or plating gold (Au) on these foils The resulting foil is used as the first conductive layer 102. Although these metal foils are produced as rolled foils or electrolytic foils (electroplated foils), in order to improve the adhesion during lamination, the back surface facing the first substrate P1 must have a certain degree of thickness (for example, the arithmetic average thickness) (Ra value is about 200 nm). On the other hand, the surface of the metal foil forming a functional layer (such as an insulating layer or a semiconductor layer) must be a smooth surface having a roughness Ra value of several nm to several tens of nm. Therefore, when the first conductive layer 102 is a metal foil, the metal can be intentionally made. The roughness Ra value of the surface of the foil is different from that of the back surface. The surface having a large roughness Ra value is regarded as the first substrate P1 side, and the surface having a small roughness Ra value is regarded as a surface forming the laminated structure.

Claims (10)

A transfer substrate is used to transfer at least a part of a laminated structure constituting an electronic component onto a transferred substrate, characterized in that the laminated structure is formed on a surface of the transfer substrate, and the laminated structure system uses conductive material. A first conductive layer formed on the transfer substrate with a conductive material, a functional layer formed on the first conductive layer using at least one material of insulation and semiconductor, and a second layer formed on the functional layer using a conductive material The conductive layer is formed by forming an alignment mark on the second conductive layer or the first conductive layer by a photo-patterning process to detect the position of the transferred substrate. For example, the transfer substrate according to the first patent application range, wherein the aforementioned functional layer is composed of an insulating layer, or both a semiconductor layer and an insulating layer. For example, the transfer substrate of the scope of patent application No. 1 or 2, wherein the first conductive layer, the aforementioned functional layer, and the aforementioned first layer are continuously laminated on the surface of the aforementioned transfer substrate in such a manner as to cover the surface in a comprehensive manner. 2 conductive layer. For example, the transfer substrate of the first or second patent application scope, in which any or all of the first conductive layer, the functional layer, and the second conductive layer are formed by evaporation, sputtering, and CVD. Either form. For example, the transfer substrate of the first or second patent application range, wherein the transfer substrate is a flexible substrate; the first conductive layer, the functional layer, and the second conductive layer are roll-to-roll The aforementioned flexible substrate is transported by the method. For example, the transfer substrate of the scope of patent application No. 1 or 2, wherein the transfer substrate is A peeling layer made of an alkali-soluble material is provided between the first conductive layers; the peeling layer is removed from the first conductive layer by an alkaline solvent after the transfer. For example, the transfer substrate of the scope of application for the patent item 1 or 2, wherein the first conductive layer is formed on the transfer substrate and the element regions forming the electronic components are similarly or selectively stacked in the element regions. The functional layer is similarly or selectively deposited on the first conductive layer, and the second conductive layer is similarly or selectively deposited on the functional layer. A transfer substrate is for supporting the laminated structure to transfer at least a part of the laminated structure constituting the electronic component onto a product substrate forming an electronic component including a semiconductor element, wherein the laminated structure is formed from The surface side of the transfer substrate includes a first conductive layer that is formed similarly or selectively using a conductive material, a functional layer that is formed similarly or selectively using an insulating material or a material that exhibits semiconductor characteristics, and uses conductive properties. The second conductive layer is sequentially laminated in the same or selectively formed material, and the interface between the first conductive layer and the functional layer, or the interface between the functional layer and the second conductive layer is flattened to a level of less than a micron. Into. For example, the transfer substrate of the eighth patent application range, wherein the transfer substrate is made of a metal material, the conductive material is the same metal material or ITO as the transfer substrate, and the functional layer is the insulating material and A layer formed of any one of the aforementioned materials exhibiting semiconductor characteristics, or a laminate of the aforementioned insulating material and the aforementioned materials exhibiting semiconductor characteristics. For example, the transfer substrate with the scope of patent application No. 8 or 9, wherein the material of the transfer substrate is copper, and the conductive material constituting the first conductive layer and the second conductive layer is made of copper. Also set to copper.