TW201624645A - Semiconductor structure and fabrication method thereof - Google Patents

Abstract

A semiconductor structure and fabrication method thereof is provided. The semiconductor structure comprises a substrate, an insulating protective layer and a barrier structure. The substrate has a substrate body and a plurality of electrical connecting pads. The substrate body has opposite a first surface and a second surface, and the first surface of the substrate body defines an electrical connecting area. The electrical connecting pads are formed on the first surface and disposed inside of the electrical connecting area. The insulating protective layer is formed on the first surface of the substrate and the electrical connecting pads. The barrier structure is formed on the first surface of the substrate body or the insulating protective layer, and disposed outside of the electrical connecting area to surround the electrical connecting pads. Thereby, the invention can prevent an encapsulation permeating into the electrical connecting pads and improve yield of product.

Description

Semiconductor structure and its manufacturing method

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a barrier structure and a method of fabricating the same.

1A to 1B are schematic cross-sectional views showing a semiconductor structure 1 of the prior art and a method of manufacturing the same, wherein the 1A' is a bottom view of the line AA of FIG. 1A.

As shown in FIG. 1A, a substrate 10 having a substrate body 101 and a plurality of electrical connection pads 102 is provided. The substrate body 101 has a first surface 101a and a second surface 101b opposite to each other, and the substrate body 101 is A solder mask 11 having a lower surface 11a and a plurality of openings 111 and a plurality of recesses 112 (recesses) respectively formed on the lower surface 11a are formed on a surface 101a.

Next, the substrate 10 is diced and the defective product is removed, and the film 12 is attached to the lower surface 11a of the solder resist layer 11. Then, the wafer 13 is disposed on the second surface 101b of the substrate body 101, and electrically connected to the wafer 13 and the substrate body 101 through the plurality of conductive bumps 14.

As shown in FIG. 1B, an encapsulant 15 is formed on the film 12 and the base The substrate body 101, the solder resist layer 11, the wafer 13 and the conductive bumps 14 are covered on the board 10 by the encapsulant 15 .

However, the semiconductor structure 1 of the above-mentioned prior art has the disadvantage that the solder resist layer 11 forms a plurality of protrusions at the electrical connection pads 102, and a plurality of recesses 112 are formed at the non-electrical connection pads 102. (depression) such that a gap 121 is formed between the periphery of the substrate 10 (or the solder resist layer 11) and the film 12, and the lower surface 11a of the solder resist layer 11 becomes an uneven surface, so that the solder resist layer It is difficult to completely fit the surface 11a below the surface 11 with the film 12.

Therefore, during the molding process of the encapsulant 15 , the encapsulant 15 easily penetrates into the opening 111 of the solder resist 11 through the gap 121 and the recess 112 of the solder resist layer 11 , so that the encapsulant 15 contaminates the encapsulant 15 . The exposed surface 102a of the electrical connection pad 102 exposed by the openings 111 causes subsequent soldering balls (not shown) to be attached to the electrical connection pads 102, respectively. The electrical connection pads 102 are detached, thereby reducing the yield of the product.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

The present invention provides a semiconductor structure and a method of fabricating the same that prevents penetration of an encapsulant onto an electrical connection pad to improve product yield.

The semiconductor structure of the present invention comprises: a substrate having a substrate body and a plurality of electrical connection pads, wherein the substrate has a first surface and a second surface opposite to each other, and the first surface of the substrate body is electrically defined Sex And a plurality of electrical connection pads formed on the first surface of the substrate body and located in the electrical connection region; the insulating protection layer is formed on the first surface of the substrate body and the electrical connection pads And a blocking structure formed on the first surface of the substrate body or the insulating protective layer, and the blocking structure is located outside the electrical connecting region to surround the electrical connecting pads.

Moreover, the method for fabricating a semiconductor structure of the present invention includes: providing a substrate having a substrate body and a plurality of electrical connection pads, the substrate having a first surface and a second surface opposite to each other, and the first surface of the substrate body An electrical connection region is defined, and the electrical connection pads are formed on the first surface of the substrate body and located in the electrical connection region; and an insulating protection layer is formed on the first surface of the substrate body and the electricity And forming a blocking structure on the first surface of the substrate body or the insulating protective layer, wherein the blocking structure is located outside the electrical connecting region to surround the electrical connecting pads.

In the above semiconductor structure and method of fabricating the same, the barrier structure may be formed on a periphery of the first surface of the substrate body or an insulating protective layer on the periphery. Alternatively, the barrier structure may be formed between the periphery of the first surface of the substrate body and the electrical connection region and spaced apart from the periphery.

In the above semiconductor structure and the manufacturing method thereof, the material of the blocking structure may be a conductive material, and is the same or different from the material of the electrical connection pads, and the blocking structure may be electrically connected to the electrical connection pads. One is used as a power source or grounding. Alternatively, the material of the barrier structure is a non-conductive material or an insulating material, and is the same or different from the material of the insulating protective layer.

In the above semiconductor structure and its manufacturing method, the substrate can be At least one of the edge protection layer and the barrier structure is attached to the carrier, and the carrier may be a film, a release film or a carrier sheet having an adhesive layer.

In the above semiconductor structure and method of fabricating the same, the insulating protective layer may be formed on the electrical connection pads and have a plurality of openings to respectively expose the lower surfaces of the electrical connection pads.

In the above semiconductor structure and method of manufacturing the same, a semiconductor element may be disposed on the substrate, and the semiconductor element and the substrate may be electrically connected through the plurality of conductive elements.

In the above semiconductor structure and method of fabricating the same, an encapsulant may be formed on the substrate to cover a side surface of the substrate body.

It can be seen from the above that in the semiconductor structure and the manufacturing method thereof, the barrier structure is mainly formed on the first surface (such as the periphery) or the insulating protective layer of the substrate body, and the barrier structure surrounds the electrical connection region. A plurality of electrical connection pads.

Thereby, the barrier structure may have a sufficient thickness (height) or a thickness (height) of the insulating protective layer to block the encapsulant through the insulating protective layer during the molding process such as the encapsulant. The gap or recess (recess) of the carrier prevents the encapsulant from penetrating into the electrical connection pads, thereby preventing the encapsulant from contaminating the surface of the electrical connection pads, and facilitating subsequent electrical connections. The pads are respectively implanted such as solder balls or electrically connected to improve the yield of the product.

Moreover, the material of the blocking structure can be the same as the material of the electrical connection pads, and the blocking structure and the electrical connection pads can be simultaneously formed on the first surface of the substrate body to reduce the process of the semiconductor structure. And lower cost. Moreover, the blocking structure can be electrically connected to at least one of the electrical connection pads for use as a power source or a ground to enhance the electrical performance of the semiconductor structure.

In addition, the material of the barrier structure may be the same as the material of the insulating protective layer, and the barrier structure may be formed on the insulating protective layer by the same or repeated manner (such as printing) (or the insulating protective layer may be formed) The barrier structure can increase the thickness of the insulating protective layer or the blocking structure, and can simplify the process and reduce the cost.

1, 2, 3, 4‧‧‧ semiconductor structure

10, 20‧‧‧ substrate

101, 201‧‧‧ substrate body

101a, 201a‧‧‧ first surface

101b, 201b‧‧‧ second surface

102a, 11a, 202a, 21a, 22a‧‧‧ lower surface

102‧‧‧Electrical connection pads

11‧‧‧ solder mask

111, 211, 231‧‧‧ openings

112, 212‧‧‧ recess

12‧‧‧ Film

121‧‧‧ gap

13‧‧‧ wafer

14‧‧‧Electrical bumps

15, 28‧‧‧Package colloid

201c‧‧‧ side surface

201d‧‧‧Weekly

202‧‧‧First electrical connection pad

203‧‧‧Second electrical connection pad

204‧‧‧Electrical connection area

21‧‧‧First insulation protection layer

22‧‧‧Block structure

23‧‧‧Second insulation protection layer

24‧‧‧Carrier

25‧‧‧Semiconductor components

251‧‧‧ solder pads

26‧‧‧Conductive components

27‧‧‧Bottom glue

AA, BB‧‧ ‧ line segments

D‧‧‧ spacing

1A to 1B are schematic cross-sectional views showing a semiconductor structure and a method of manufacturing the same according to the prior art, wherein the 1A' is a bottom view of the line AA of FIG. 1A and the 2A to 2D. A schematic cross-sectional view of a first embodiment of a semiconductor structure and a method of fabricating the same according to the present invention, wherein the 2A' is a bottom view of the second section A in the line BB, and the 2A' is a 2A' FIG. 3 is a cross-sectional view showing a second embodiment of the semiconductor structure of the present invention; and FIG. 4 is a cross-sectional view showing a third embodiment of the semiconductor structure of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered.

At the same time, terms such as "upper", "lower", "one", "first", "second", "surface" or "electrical connection area" cited in this manual are also for convenience only. It is to be understood that the scope of the invention is not limited by the scope of the invention.

2A to 2D are schematic cross-sectional views showing a first embodiment of the semiconductor structure 2 of the present invention and a method of manufacturing the same, wherein the 2A' is a bottom view of the line BB of FIG. 2A, 2A" The figure is another embodiment of the 2A' diagram.

As shown in FIG. 2A and FIG. 2B , a substrate 20 having a substrate body 201 , a plurality of first electrical connection pads 202 and a plurality of second electrical connection pads 203 is provided, and the substrate 20 can be a circuit substrate or a semiconductor. Substrate or interposer, etc.

The substrate body 201 has an opposite first surface 201a (such as a surface) and a second surface 201b (such as the surface) and a side surface 201c, and the first surface 201a of the substrate body 201 defines an electrical connection region 204 (or Grafting area). The first electrical connection pads 202 are formed on the substrate body 201. The first surface 201a is located in the electrical connection region 204, and the second electrical connection pads 203 are formed on the second surface 201b of the substrate body 201.

In addition, a first insulating protective layer 21 (such as a solder resist layer) may be formed on the first surface 201a of the substrate body 201 and the first electrical connection pads 202, and the first insulating protective layer 21 may have a lower surface. 21a, and a plurality of openings 211 and recesses 212 (recesses) formed in the lower surface 21a, respectively, the openings 211 are respectively exposed to the lower surface 202a of the first electrical connection pads 202.

At the same time, the blocking structure 22 can be formed on the first surface 201a of the substrate body 201, and the blocking structure 22 is located outside the electrical connection region 204 to surround the first electrical connection pads 202, and the blocking structure 22 The shape can be square, rectangular, circular, elliptical, regular or irregular.

In the 2A and 2A', the barrier structure 22 is formed on the periphery 201d of the first surface 201a of the substrate body 201, and the first insulating protection layer 21 is further formed on the barrier structure 22 and exposed. One side surface of the blocking structure 22.

In the second embodiment, the barrier structure 22 can also be formed between the peripheral edge 201d of the first surface 201a of the substrate body 201 and the electrical connection region 204, and spaced apart from the peripheral edge 201d by a distance D.

The material of the barrier structure 22 can be a conductive material and can be the same or different from the materials of the first electrical connection pads 202. For example, the material of the barrier structure 22 is the same as that of the first electrical connection pads 202, and the barrier structure 22 and the first electrical connection pads 202 are formed on the first surface 201a of the substrate body 201. , the process of the semiconductor structure 2 can be reduced And reduce costs. Moreover, the blocking structure 22 can also be electrically connected to at least one of the first electrical connection pads 202 for use as a power source or a ground to enhance the semiconductor structure. 2 electrical performance.

The material of the blocking structure 22 may also be a non-conductive material or an insulating material, and may be the same or different from the material of the first insulating protective layer 21. For example, the material of the blocking structure 22 is the same as that of the first insulating protective layer 21, and the blocking structure 22 is formed on the first insulating protective layer 21 by the same or repeated manner (such as printing). The first insulating protective layer 21 on the blocking structure 22 can increase the thickness of the first insulating protective layer 21 or the blocking structure 22, and can simplify the process and reduce the cost.

In addition, a second insulating protective layer 23 (such as a solder resist layer) may be formed on the second surface 201b of the substrate body 201 and the second electrical connecting pads 203, and the second insulating protective layer 23 may have a plurality of openings The holes 231 are respectively exposed to the upper surfaces of the second electrical connection pads 203.

As shown in FIG. 2B, the second and second AA views are continued, and the carrier member 24 is attached to the lower surface 21a of the first insulating protective layer 21, and the width of the carrier member 24 is greater than the substrate. The width of the body 201 is to extend the carrier 24 to the outside of the side surface 201c of the substrate body 201. The carrier member 24 can be a film (such as a single-sided film or a double-sided film), a release film or a carrier sheet having an adhesive layer, and the adhesive layer of the carrier sheet faces or fits the first insulating protective layer. twenty one.

In this embodiment, the carrier member 24 can be attached only to the lower surface 21a of the first insulating protection layer 21 without further bonding to the first insulation protection. The opening 211 of the layer 21 and the recess 212 are such that the upper surface of the carrier 24 is flush with the lower surface 21a of the first insulating protective layer 21. However, in other embodiments, the carrier member 24 can be further attached to the opening 211 and the recess 212 of the first insulating protective layer 21 (see FIG. 4).

As shown in FIG. 2C, a semiconductor device 25 having a plurality of pads 251 is disposed on the second insulating protective layer 23 (or the second surface 201b of the substrate body 201) and electrically connected through the plurality of conductive members 26. The pad 251 of the semiconductor component 25 and the second electrical connection pad 203 of the substrate 20 are connected. The semiconductor component 25 can be a semiconductor wafer or a semiconductor package or the like, and the conductive components 26 can be conductive bumps or bonding wires or the like.

In addition, a primer 27 may be formed between the semiconductor device 25 and the second insulating protective layer 23 (or the second surface 201b of the substrate body 201) to cover the conductive elements 26 by the primer 27. Such as conductive bumps).

As shown in FIG. 2D, the encapsulant 28 is formed on the upper surface of the substrate 20 and the carrier member 24 to cover the side surface 201c of the substrate body 201 and the first insulating protective layer 21 by the encapsulant 28 The side surface, the second insulating protective layer 23, one side surface of the blocking structure 22, the semiconductor element 25 and the primer 27. Thereby, the semiconductor structure 2 of the present invention can be formed.

The present invention also provides a semiconductor structure 2 as shown in FIG. 2D, and the semiconductor structure 2 mainly includes a substrate 20, a first insulating protective layer 21, a blocking structure 22, and an encapsulant 28.

The substrate 20 can be a circuit substrate, a semiconductor substrate or an interposer, etc., and has a substrate body 201, a plurality of first electrical connection pads 202, and a plurality of second Electrical connection pad 203.

The substrate body 201 has an opposite first surface 201a (such as a surface) and a second surface 201b (such as the surface) and a side surface 201c, and the first surface 201a of the substrate body 201 defines an electrical connection region 204 (or Grafting area). The first electrical connection pads 202 are formed on the first surface 201a of the substrate body 201 and are located in the electrical connection region 204. The second electrical connection pads 203 are formed on the substrate body 201. Two surfaces 201b.

The first insulating protective layer 21 (such as a solder resist) is formed on the first surface 201a of the substrate body 201 and the first electrical connecting pads 202, and the first insulating protective layer 21 may have a lower surface 21a. And a plurality of openings 211 and a plurality of recesses 212 respectively formed on the lower surface 21a. The openings 211 respectively expose the lower surface 202a of the first electrical connection pads 202.

The blocking structure 22 is formed on the first surface 201a of the substrate body 201, and the blocking structure 22 is located outside the electrical connection region 204 to surround the first electrical connection pads 202, and the shape of the blocking structure 22 It can be square, rectangular, circular, elliptical, regular or irregular.

In this embodiment, the blocking structure 22 can be formed on the periphery 201d of the first surface 201a of the substrate body 201, and the first insulating protective layer 21 is formed on the blocking structure 22 and the side of the blocking structure 22 is exposed. surface.

In other embodiments, the barrier structure 22 can also be formed between the peripheral edge 201d of the first surface 201a of the substrate body 201 and the electrical connection region 204, and spaced apart from the peripheral edge 201d by a distance D. 2A" figure.

The material of the barrier structure 22 can be a conductive material and can be the same or different from the materials of the first electrical connection pads 202. For example, the blocking structure 22 The material is the same as the material of the first electrical connection pads 202, and the barrier structure 22 and the first electrical connection pads 202 are simultaneously formed on the first surface 201a of the substrate body 201, thereby reducing the semiconductor. Structure 2 process and cost reduction. Moreover, the blocking structure 22 can also be electrically connected to at least one of the first electrical connection pads 202 for use as a power source or ground for the barrier structure 22, thereby improving the electrical performance of the semiconductor structure 2.

The material of the blocking structure 22 may be a non-conductive material or an insulating material, and may be the same or different from the material of the first insulating protective layer 21. For example, the material of the blocking structure 22 is the same as that of the first insulating protective layer 21, and the blocking structure 22 is formed on the first insulating protective layer 21 by the same or repeated manner (such as printing). The first insulating protective layer 21 on the blocking structure 22 can increase the thickness of the first insulating protective layer 21 or the blocking structure 22, and can simplify the process and reduce the cost.

The encapsulant 28 is formed on the upper surface of the substrate 20 and the carrier 24 to cover the side surface 201c of the substrate body 201 and the side surface of the first insulating protective layer 21 by the encapsulant 28, Two insulating protective layers 23 and one side surface of the blocking structure 22.

The semiconductor structure 2 can include a carrier member 24 that is attached to the lower surface 21a of the first insulating protective layer 21, and the width of the carrier member 24 can be greater than the width of the substrate body 201 to The member 24 extends outside the side surface 201c of the substrate body 201. The carrier member 24 can be a film (such as a single-sided film or a double-sided film), a release film or a carrier sheet having an adhesive layer, and the adhesive layer of the carrier sheet faces or conforms to the first insulating protective layer 21.

The semiconductor structure 2 may include a second insulating protective layer 23 (such as a solder resist layer). The second insulating protective layer 23 is formed on the second surface 201b of the substrate body 201 and the second electrical connecting pads 203. And the upper surface of the second electrical connection pads 203 is exposed.

In this embodiment, the carrier member 24 can be attached only to the lower surface 21a of the first insulating protective layer 21 without further conforming to the opening 211 and the recess 212 of the first insulating protective layer 21, so that The upper surface of the carrier member 24 is flush with the lower surface 21a of the first insulating protective layer.

The semiconductor structure 2 can include a semiconductor component 25 having a plurality of pads 251 disposed on the second insulating protective layer 23 (or the second surface 201b of the substrate body 201) and through the plurality of conductive components. 26 are electrically connected to the second electrical connection pads 203 of the substrate 20 respectively. The semiconductor component 25 can be a semiconductor wafer or a semiconductor package or the like, and the conductive components 26 can be conductive bumps or bonding wires or the like.

The semiconductor structure 2 may include a primer 27 formed between the semiconductor component 25 and the second insulating protective layer 23 (or the second surface 201b of the substrate body 201) to form the primer. 27 covers the conductive elements 26 (such as conductive bumps). In addition, the encapsulant 28 can also cover the semiconductor component 25 and the primer 27.

The present invention further provides a semiconductor structure 3 as shown in FIG. 3, and FIG. 3 is a cross-sectional view showing a second embodiment of the semiconductor structure 3 of the present invention. The semiconductor structure 3 of Fig. 3 is substantially the same as the semiconductor structure 2 of Fig. 2 described above, so the same points are not repeated, and the main differences are as follows: The first insulating protective layer 21 of FIG. 3 is formed only on the first surface 201a of the substrate body 201 and the first electrical connection pad 202, and is not formed on the lower surface 22a of the blocking structure 22.

The blocking structure 22 of FIG. 3 can be formed between the first surface 201a of the substrate body 201 and the carrier 24, and the lower surface 22a of the blocking structure 22 can be flush with the lower surface 21a of the first insulating protective layer 21. And the thickness (height) of the blocking structure 22 may be greater than the thickness (height) of the blocking structure 22 of the 2D drawing.

Moreover, the encapsulant 28 of FIG. 3 may only cover one side surface of the blocking structure 22, and the side surface of the blocking structure 22 may be flush with the side surface 201c of the substrate body 201.

The present invention further provides a semiconductor structure 4 as shown in FIG. 4, and FIG. 4 is a cross-sectional view showing a third embodiment of the semiconductor structure 4 of the present invention. The semiconductor structure 4 of FIG. 4 is substantially the same as the semiconductor structure 2 of FIG. 2 described above, and therefore the same points are not repeatedly described. The main difference is as follows: The barrier structure 22 of FIG. 4 is formed on the first insulating protective layer. 21, that is, the blocking structure 22 is formed between the first insulating protective layer 21 and the carrier 24, and the blocking structure 22 can be located at the periphery 201d of the first surface 201a of the substrate body 201, and the carrier 24 Then, it is further adhered to the opening 211 and the recess 212 of the first insulating protective layer 21.

It can be seen from the above that in the semiconductor structure and the manufacturing method thereof, the barrier structure is mainly formed on the first surface (such as the periphery) or the insulating protective layer of the substrate body, and the barrier structure surrounds the electrical connection region. Multiple electricity Sex connection pad.

Thereby, the barrier structure may have a sufficient thickness (height) or a thickness (height) of the insulating protective layer to block the encapsulant through the insulating protective layer during the molding process such as the encapsulant. The gap or recess (recess) of the carrier prevents the encapsulant from penetrating into the electrical connection pads, thereby preventing the encapsulant from contaminating the surface of the electrical connection pads, and facilitating subsequent electrical connections. The pads are respectively implanted such as solder balls or electrically connected to improve the yield of the product.

Moreover, the material of the blocking structure can be the same as the material of the electrical connection pads, and the blocking structure and the electrical connection pads can be simultaneously formed on the first surface of the substrate body to reduce the process of the semiconductor structure. And reduce costs. Moreover, the blocking structure can be electrically connected to at least one of the electrical connection pads for use as a power source or a ground to enhance the electrical performance of the semiconductor structure.

In addition, the material of the barrier structure may be the same as the material of the insulating protective layer, and the barrier structure may be formed on the insulating protective layer by the same or repeated manner (such as printing) (or the insulating protective layer may be formed) The barrier structure can increase the thickness of the insulating protective layer or the blocking structure, and can simplify the process and reduce the cost.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application.

2‧‧‧Semiconductor structure

20‧‧‧Substrate

201‧‧‧Substrate body

201a‧‧‧ first surface

201b‧‧‧ second surface

201c‧‧‧ side surface

202‧‧‧First electrical connection pad

202a‧‧‧ lower surface

203‧‧‧Second electrical connection pad

204‧‧‧Electrical connection area

21‧‧‧First insulation protection layer

21a‧‧‧lower surface

211‧‧‧ openings

212‧‧‧ recess

22‧‧‧Block structure

23‧‧‧Second insulation protection layer

231‧‧‧ openings

24‧‧‧Carrier

25‧‧‧Semiconductor components

251‧‧‧ solder pads

26‧‧‧Conductive components

27‧‧‧Bottom glue

28‧‧‧Package colloid

Claims (18)

A semiconductor structure comprising: a substrate having a substrate body and a plurality of electrical connection pads, wherein the substrate has a first surface and a second surface opposite to each other, and the first surface of the substrate body defines electrical properties a connection region, wherein the electrical connection pads are formed on the first surface of the substrate body and located in the electrical connection region; an insulating protective layer is formed on the first surface of the substrate body; and the blocking structure is formed On the first surface of the substrate body or the insulating protective layer, and the blocking structure is located outside the electrical connection region to surround the electrical connection pads. The semiconductor structure of claim 1, wherein the barrier structure is formed on a periphery of the first surface of the substrate body or an insulating protective layer on the periphery. The semiconductor structure of claim 1, wherein the barrier structure is formed between a periphery of the first surface of the substrate body and the electrical connection region and spaced apart from the periphery. The semiconductor structure of claim 1, wherein the material of the barrier structure is a conductive material and is the same or different from the material of the electrical connection pads. The semiconductor structure of claim 4, wherein the blocking structure is electrically connected to at least one of the electrical connection pads for use as a power source or a ground. The semiconductor structure of claim 1, wherein the material of the barrier structure is a non-conductive material or an insulating material, and is the same as or different from the material of the insulating protective layer. The semiconductor structure of claim 1, further comprising a carrier attached to at least one of the insulating protective layer and the blocking structure. The semiconductor structure of claim 7, wherein the carrier is a film, a release film or a carrier sheet having an adhesive layer. The semiconductor structure of claim 1, wherein the insulating protective layer is formed on the electrical connection pads and has a plurality of openings to respectively expose the lower surfaces of the electrical connection pads. The semiconductor structure of claim 1, further comprising a semiconductor component disposed on the substrate and electrically connected to the substrate through a plurality of conductive elements. The semiconductor structure of claim 1, further comprising an encapsulant formed on the substrate and covering a side surface of the substrate body. A method of fabricating a semiconductor structure, comprising: providing a substrate having a substrate body and a plurality of electrical connection pads, wherein the substrate system has opposite first and second surfaces, and the first surface of the substrate body is defined An electrical connection pad is formed on the first surface of the substrate body and located in the electrical connection region; and an insulating protection layer is formed on the first surface of the substrate body, and is shaped The barrier structure is disposed on the first surface of the substrate body or the insulating protection layer, wherein the barrier structure is located outside the electrical connection region to surround the electrical connection pads. The method of fabricating a semiconductor structure according to claim 12, wherein the barrier structure is formed on a periphery of the first surface of the substrate body or an insulating protective layer on the periphery. The method of fabricating a semiconductor structure according to claim 12, wherein the barrier structure is formed between a periphery of the first surface of the substrate body and the electrical connection region, and spaced apart from the periphery. The method of fabricating the semiconductor structure of claim 12, further comprising attaching at least one of the insulating protective layer on the substrate to the barrier structure. The method of fabricating a semiconductor structure according to claim 12, wherein the insulating protective layer is formed on the electrical connection pads and has a plurality of openings to respectively expose the lower surfaces of the electrical connection pads. The method of fabricating a semiconductor structure according to claim 12, further comprising: disposing a semiconductor component on the substrate, and electrically connecting the semiconductor component and the substrate through the plurality of conductive components. The method for fabricating a semiconductor structure according to claim 12, further comprising forming an encapsulant on the substrate and covering a side surface of the substrate body.