CN105826287A - Semiconductor structure and method for fabricating the same - Google Patents
Semiconductor structure and method for fabricating the same Download PDFInfo
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- CN105826287A CN105826287A CN201510008201.0A CN201510008201A CN105826287A CN 105826287 A CN105826287 A CN 105826287A CN 201510008201 A CN201510008201 A CN 201510008201A CN 105826287 A CN105826287 A CN 105826287A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 239000000084 colloidal system Substances 0.000 claims abstract description 26
- 239000011241 protective layer Substances 0.000 claims description 80
- 239000000463 material Substances 0.000 claims description 32
- 238000002360 preparation method Methods 0.000 claims description 28
- 238000012856 packing Methods 0.000 claims description 25
- 239000010410 layer Substances 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 description 15
- 238000012545 processing Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor structure and a manufacturing method thereof are provided, the semiconductor structure comprises a substrate, an insulating protection layer and a barrier structure. The substrate is provided with a substrate body and a plurality of electric connection pads, the substrate body is provided with a first surface and a second surface which are opposite, the first surface of the substrate body is defined with an electric connection area, and the electric connection pads are formed on the first surface of the substrate body and are positioned in the electric connection area. The insulating protection layer is formed on the first surface of the substrate body and the electrical connection pad. The barrier structure is formed on the first surface of the substrate body or the insulating protection layer and is located outside the electrical connection region to surround the electrical connection pad. Therefore, the invention can prevent the packaging colloid from permeating into the electric connection pads so as to improve the yield of products.
Description
Technical field
The present invention relates to a kind of semiconductor structure and preparation method thereof, particularly relate to a kind of semiconductor structure with barrier structure and preparation method thereof.
Background technology
Figure 1A to Figure 1B is semiconductor structure 1 and the cross-sectional schematic of preparation method thereof illustrating prior art, and wherein, Figure 1A ' is that Figure 1A is in the elevational schematic view of line segment AA.
As shown in Figure 1A, one substrate 10 with substrate body 101 and multiple electric connection pads 102 is first provided, this substrate body 101 has relative first surface 101a and second surface 101b, and on the first surface 101a of this substrate body 101, it being formed with welding resisting layer 11 (soldermask), this welding resisting layer 11 has lower surface 11a and the multiple perforates 111 being respectively formed in this lower surface 11a and multiple recesses 112 (depression).
Then, this substrate 10 is carried out singulation operation and rejects defective products, then film 12 is fitted in the lower surface 11a of this welding resisting layer 11.Then, chip 13 is arranged at the second surface 101b of this substrate body 101, and is electrically connected with this chip 13 and this substrate body 101 through multiple conductive projections 14.
As shown in Figure 1B, formation packing colloid 15 is on this film 12 and this substrate 10, to be coated with this substrate body 101, welding resisting layer 11, chip 13 and conductive projection 14 by this packing colloid 15.
Only, the shortcoming of the semiconductor structure 1 of above-mentioned prior art is: because this welding resisting layer 11 can form multiple protuberance at those electric connection pads 102, and at those electric connection pads 102 non-, form multiple recess 112 (depression), make to be formed with gap 121 between periphery and this film 12 of this substrate 10 (or welding resisting layer 11), and make the lower surface 11a of this welding resisting layer 11 become rough surface, so that it is difficult to fit tightly completely between the lower surface 11a of this welding resisting layer 11 and this film 12.
Therefore, in the mold process of this packing colloid 15, this packing colloid 15 penetrates into the perforate 111 of this welding resisting layer 11 easily by gap 121 and the recess 112 of this welding resisting layer 11, this packing colloid 15 is made to pollute the lower surface 102a of the electric connection pad 102 that those perforates 111 are exposed, cause follow-up planting when connecing such as soldered ball (figure does not illustrates) on those electric connection pads 102 respectively, those soldered balls easily come off on those electric connection pads 102, thus reduce the yield of product.
Therefore, how to overcome above-mentioned problem of the prior art, become the problem desiring most ardently solution at present in fact.
Summary of the invention
The present invention provides a kind of semiconductor structure and preparation method thereof, and it can prevent packing colloid such as from penetrating into electric connection pad, to improve the yield of product.
The semiconductor structure of the present invention includes: substrate, it has substrate body and multiple electric connection pads, wherein, this substrate body has relative first surface and second surface, and the first surface definition of this substrate body has electric connection district, and those electric connection pads are formed at the first surface of this substrate body and are positioned at this electric connection district；On insulating protective layer, its first surface being formed at this substrate body and those electric connection pads；And on barrier structure, its first surface being formed at this substrate body or this insulating protective layer, and this barrier structure is positioned at outside this electric connection district to surround those electric connection pads.
Again, the preparation method of the semiconductor structure of the present invention includes: provide a substrate with substrate body and multiple electric connection pads, this substrate body has relative first surface and second surface, and the first surface definition of this substrate body has electric connection district, and those electric connection pads are formed at the first surface of this substrate body and are positioned at this electric connection district；And form insulating protective layer on the first surface and those electric connection pads of this substrate body; and form barrier structure on the first surface of this substrate body or this insulating protective layer; wherein, to surround those electric connection pads outside this barrier structure is positioned at this electric connection district.
In above-mentioned semiconductor structure and preparation method thereof, this barrier structure can be formed on the periphery of the first surface of this substrate body or the insulating protective layer of this periphery.Or, this barrier structure can be formed between the periphery of the first surface of this substrate body and this electric connection district, and is separated by a spacing with this periphery.
In above-mentioned semiconductor structure and preparation method thereof, the material of this barrier structure can be conductive material, and be same or different from the material of those electric connection pads, and this barrier structure can be electrically connected to those electric connection pad at least one of which to be used as power supply or ground connection.Or, the material of this barrier structure can be non-conducting material or insulant, and is same or different from the material of this insulating protective layer.
In above-mentioned semiconductor structure and preparation method thereof, this insulating protective layer on this substrate and this barrier structure at least one of which can be fitted on bearing part, and this bearing part can be film, stripping film or the carrying tablet with adhesion layer.
In above-mentioned semiconductor structure and preparation method thereof, this insulating protective layer can be formed on those electric connection pads, and has multiple perforate to expose outside the lower surface of those electric connection pads respectively.
In above-mentioned semiconductor structure and preparation method thereof, semiconductor subassembly can be set on this substrate, and be electrically connected with this semiconductor subassembly and this substrate through multiple conductive components.
In above-mentioned semiconductor structure and preparation method thereof, packing colloid can be formed on this substrate to be coated with the side surface of this substrate body.
As from the foregoing; in the semiconductor structure of the present invention and preparation method thereof; mainly formation barrier structure is on the first surface (such as periphery) or insulating protective layer of substrate body, and surrounds the multiple electric connection pads being positioned at electric connection district by this barrier structure.
Thereby; this barrier structure can have the thickness (highly) of enough thickness (highly) or this insulating protective layer padded; with in such as the mold process of packing colloid; this packing colloid is by this insulating protective layer and the gap of this bearing part or recess (depression) to utilize this barrier structure to stop; this packing colloid is made not penetrate into those electric connection pads; thus avoid this packing colloid to pollute the surface of those electric connection pads; follow-up planting respectively on those electric connection pads connects such as soldered ball or carries out being electrically connected with operation, and then improves the yield of product.
And, the material of this barrier structure can be same as the material of those electric connection pads, and can concurrently form this barrier structure and be padded on the first surface of this substrate body with those electric connection, to reduce processing procedure and the reduction cost of this semiconductor structure.Also, this barrier structure can be electrically connected to those electric connection pad at least one of which to be used as power supply or ground connection, thus promote the electrical property efficiency of this semiconductor structure.
Additionally; the material of this barrier structure also can be same as the material of this insulating protective layer; and mode (such as mode of printing) that is identical or that repeat can be used to form this barrier structure on this insulating protective layer (or forming this insulating protective layer on this barrier structure); the thickness of this insulating protective layer or this barrier structure can be increased, and processing procedure can be simplified and reduce cost.
Accompanying drawing explanation
Figure 1A to Figure 1B is the cross-sectional schematic of semiconductor structure and the preparation method thereof illustrating prior art, and wherein, Figure 1A ' is that Figure 1A is in the elevational schematic view of line segment AA；
Fig. 2 A to Fig. 2 D is the cross-sectional schematic of the first embodiment illustrating the semiconductor structure of the present invention and preparation method thereof, and wherein, Fig. 2 A ' is that Fig. 2 A is in the elevational schematic view of line segment BB, Fig. 2 A " it is another embodiment of Fig. 2 A '；
Fig. 3 is the cross-sectional schematic of the second embodiment of the semiconductor structure illustrating the present invention；And
Fig. 4 is the cross-sectional schematic of the 3rd embodiment of the semiconductor structure illustrating the present invention.
Primary clustering symbol description
1,2,3,4 semiconductor structure
10,20 substrate
101,201 substrate body
101a, 201a first surface
101b, 201b second surface
102 electric connection pads
102a, 11a, 202a, 21a, 22a lower surface
11 welding resisting layers
111,211,231 perforate
112,212 recess
12 films
121 gaps
13 chips
14 conductive projections
15,28 packing colloid
201c side surface
201d periphery
202 first electric connection pads
203 second electric connection pads
204 are electrically connected with district
21 first insulating protective layers
22 barrier structures
23 second insulating protective layers
24 bearing parts
25 semiconductor subassemblies
251 weld pads
26 conductive components
27 primers
AA, BB line segment
D spacing.
Detailed description of the invention
By particular specific embodiment, embodiments of the present invention being described below, those skilled in the art can be understood further advantage and effect of the present invention easily by content disclosed in the present specification.
Notice, structure depicted in this specification institute accompanying drawings, ratio, size etc., all it is only used for coordinating the content disclosed in description, understanding and reading for those skilled in the art, it is not intended to limit the enforceable qualifications of the present invention, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, under not affecting effect that the present invention can be generated by and the purpose that can reach, all should still fall in the range of disclosed technology contents obtains and can contain.
Simultaneously, in this specification cited as " on ", D score, " one ", " first ", " second ", the term such as " surface " or " electric connection district ", it is merely convenient to understanding of narration, not for limiting the enforceable scope of the present invention, being altered or modified of its relativeness, changing under technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 D is the cross-sectional schematic of the first embodiment illustrating the semiconductor structure 2 of the present invention and preparation method thereof, and wherein, Fig. 2 A ' is that Fig. 2 A is in the elevational schematic view of line segment BB, Fig. 2 A " it is another embodiment of Fig. 2 A '.
As shown in Fig. 2 A and Fig. 2 B, first provide one to have substrate body 201, multiple first electric connection pad 202 and the substrate 20 of multiple second electric connection pads 203, and this substrate 20 can be circuit base plate, semiconductor substrate or intermediate plate etc..
This substrate body 201 has relative first surface 201a (such as lower surface) and second surface 201b (such as upper surface) and side surface 201c, and the first surface 201a definition of this substrate body 201 has electric connection district 204 (Huo Zhiqiu district).And those first electric connection pads 202 are formed at the first surface 201a of this substrate body 201 and are positioned at this electric connection district 204, those second electric connection pads 203 are formed at the second surface 201b of this substrate body 201.
Additionally; the first insulating protective layer 21 (such as welding resisting layer) can be formed on the first surface 201a and those first electric connection pads 202 of this substrate body 201; and this first insulating protective layer 21 can have lower surface 21a and the multiple perforates 211 being respectively formed in this lower surface 21a and multiple recesses 212 (depression), those perforates 211 expose outside the lower surface 202a of those the first electric connection pads 202 respectively.
Simultaneously, barrier structure 22 can be formed in the first surface 201a of this substrate body 201, and this barrier structure 22 is positioned at outside this electric connection district 204 to surround those the first electric connection pads 202, and the shape of this barrier structure 22 can be square, rectangle, circle, ellipse, regular shape or irregularly shaped.
In Fig. 2 A and Fig. 2 A ', this barrier structure 22 can be formed at the periphery 201d of the first surface 201a of this substrate body 201, and this first insulating protective layer 21 is more formed on this barrier structure 22 and exposes outside a side surface of this barrier structure 22.
And at Fig. 2 A " in, this barrier structure 22 also can be formed between the periphery 201d of the first surface 201a of this substrate body 201 and this electric connection district 204, and is separated by a space D with this periphery 201d.
The material of this barrier structure 22 can be conductive material, and may be the same or different in the material of those the first electric connection pads 202.Such as, the material of this barrier structure 22 is same as the material of those the first electric connection pads 202, and concurrently form this barrier structure 22 with those first electric connection pads 202 on the first surface 201a of this substrate body 201, the processing procedure of this semiconductor structure 2 can be reduced and reduce cost.Again, this barrier structure 22 also can be electrically connected to those the first electric connection pad 202 at least one of which, it is used as power supply (power) or ground connection (ground) for this barrier structure 22, thus promotes the electrical property efficiency of this semiconductor structure 2.
The material of this barrier structure 22 is alternatively non-conducting material or insulant, and may be the same or different in the material of this first insulating protective layer 21.Such as; the material of this barrier structure 22 is same as the material of this first insulating protective layer 21; and use mode (such as mode of printing) that is identical or that repeat to form this barrier structure 22 on this first insulating protective layer 21 (or forming this first insulating protective layer 21 on this barrier structure 22); this first insulating protective layer 21 or the thickness of this barrier structure 22 can be increased, and processing procedure can be simplified and reduce cost.
Additionally; can form the second insulating protective layer 23 (such as welding resisting layer) on second surface 201b and those second electric connection pads 203 of this substrate body 201, this second insulating protective layer 23 also can have multiple perforate 231 to expose outside the upper surface of those the second electric connection pads 203 respectively.
As shown in Figure 2 B; Fig. 2 A that it continues above-mentioned and Fig. 2 A '; and bearing part 24 of fitting is in the lower surface 21a of this first insulating protective layer 21, and the width of this bearing part 24 can be more than the width of this substrate body 201, to be extended to by this bearing part 24 outside the side surface 201c of this substrate body 201.This bearing part 24 can be film (such as one side film or double coated film), stripping film (releasefilm) or the carrying tablet etc. with adhesion layer, and the adhesion layer of this carrying tablet towards or this first insulating protective layer 21 of fitting.
In the present embodiment; this bearing part 24 can only fit in the lower surface 21a of this first insulating protective layer 21; and conforming in perforate 211 and the recess 212 of this first insulating protective layer 21 the most further so that the upper surface flush of this bearing part 24 is in the lower surface 21a of this first insulating protective layer 21.But in other embodiments, this bearing part 24 also can conform to perforate 211 and (the asking for an interview Fig. 4) in recess 212 of this first insulating protective layer 21 further.
As shown in Figure 2 C; arrange one and there is the semiconductor subassembly 25 of multiple weld pad 251 on this second insulating protective layer 23 (or second surface 201b of this substrate body 201), and be electrically connected with the weld pad 251 of this semiconductor subassembly 25 and the second electric connection pad 203 of this substrate 20 through multiple conductive components 26.This semiconductor subassembly 25 can be semiconductor chip or semiconductor package part etc., and those conductive components 26 can be conductive projection or bonding wire etc..
Additionally, primer 27 can form between this semiconductor subassembly 25 and this second insulating protective layer 23 (or second surface 201b of this substrate body 201), to be coated with those conductive components 26 (such as conductive projection) by this primer 27.
As shown in Figure 2 D; formation packing colloid 28 is in the upper surface of this substrate 20 with this bearing part 24, to be coated with the side surface 201c of this substrate body 201, the side surface of this first insulating protective layer 21, this second insulating protective layer 23, a side surface of this barrier structure 22, this semiconductor subassembly 25 and this primer 27 by this packing colloid 28.Thereby, the semiconductor structure 2 of the present invention can be formed.
The present invention also provides a kind of semiconductor structure 2 as shown in Figure 2 D, and this semiconductor structure 2 mainly includes substrate the 20, first insulating protective layer 21, barrier structure 22 and packing colloid 28.
This substrate 20 can be circuit base plate, semiconductor substrate or intermediate plate etc., and has substrate body 201, multiple first electric connection pads 202 and multiple second electric connection pads 203.
This substrate body 201 has relative first surface 201a (such as lower surface) and second surface 201b (such as upper surface) and side surface 201c, and the first surface 201a definition of this substrate body 201 has electric connection district 204 (Huo Zhiqiu district).And those first electric connection pads 202 are formed at the first surface 201a of this substrate body 201 and are positioned at this electric connection district 204, those second electric connection pads 203 are formed at the second surface 201b of this substrate body 201.
This first insulating protective layer 21 (such as welding resisting layer) is formed on first surface 201a and those first electric connection pads 202 of this substrate body 201; and this first insulating protective layer 21 can have lower surface 21a and the multiple perforates 211 being respectively formed in this lower surface 21a and multiple recesses 212, those perforates 211 expose outside the lower surface 202a of those the first electric connection pads 202 respectively.
This barrier structure 22 is formed at the first surface 201a of this substrate body 201, and this barrier structure 22 is positioned at outside this electric connection district 204 to surround those the first electric connection pads 202, and the shape of this barrier structure 22 can be square, rectangle, circle, ellipse, regular shape or irregularly shaped.
In the present embodiment, this barrier structure 22 can be formed at the periphery 201d of the first surface 201a of this substrate body 201, and this first insulating protective layer 21 is formed on this barrier structure 22 and exposes outside the side surface of this barrier structure 22.
But in other embodiments, this barrier structure 22 also can be formed between the periphery 201d of the first surface 201a of this substrate body 201 and this electric connection district 204, and is separated by a space D with this periphery 201d, asks for an interview Fig. 2 A ".
The material of this barrier structure 22 can be conductive material, and may be the same or different in the material of those the first electric connection pads 202.Such as, the material of this barrier structure 22 is same as the material of those the first electric connection pads 202, and concurrently form this barrier structure 22 with those first electric connection pads 202 on the first surface 201a of this substrate body 201, the processing procedure of this semiconductor structure 2 can be reduced and reduce cost.Also, this barrier structure 22 also can be electrically connected to those the first electric connection pad 202 at least one of which, it is used as power supply or ground connection for this barrier structure 22, thus promotes the electrical property efficiency of this semiconductor structure 2.
The material of this barrier structure 22 can be non-conducting material or insulant, and may be the same or different in the material of this first insulating protective layer 21.Such as; the material of this barrier structure 22 is same as the material of this first insulating protective layer 21; and use mode (such as mode of printing) that is identical or that repeat to form this barrier structure 22 on this first insulating protective layer 21 (or forming this first insulating protective layer 21 on this barrier structure 22); this first insulating protective layer 21 or the thickness of this barrier structure 22 can be increased, and processing procedure can be simplified and reduce cost.
This packing colloid 28 is formed at the upper surface of this substrate 20 and this bearing part 24, to be coated with the side surface 201c of this substrate body 201, the side surface of this first insulating protective layer 21, this second insulating protective layer 23 and a side surface of this barrier structure 22 by this packing colloid 28.
This semiconductor structure 2 can include bearing part 24; this bearing part 24 fits in the lower surface 21a of this first insulating protective layer 21; and the width of this bearing part 24 can be more than the width of this substrate body 201, this bearing part 24 is extended to outside the side surface 201c of this substrate body 201.This bearing part 24 can be film (such as one side film or double coated film), stripping film or the carrying tablet etc. with adhesion layer, and the adhesion layer of this carrying tablet towards or this first insulating protective layer 21 of fitting.
This semiconductor structure 2 can include the second insulating protective layer 23 (such as welding resisting layer); this second insulating protective layer 23 is formed on second surface 201b and those second electric connection pads 203 of this substrate body 201, and exposes outside the upper surface of those the second electric connection pads 203.
In the present embodiment; this bearing part 24 can only fit in the lower surface 21a of this first insulating protective layer 21; and conforming in perforate 211 and the recess 212 of this first insulating protective layer 21 the most further so that the upper surface flush of this bearing part 24 is in the lower surface 21a of this first insulating protective layer.
This semiconductor structure 2 can include a semiconductor subassembly 25 with multiple weld pad 251; this semiconductor subassembly 25 is arranged on this second insulating protective layer 23 (or second surface 201b of this substrate body 201), and is respectively and electrically connected to those second electric connection pads 203 of this substrate 20 through multiple conductive components 26.This semiconductor subassembly 25 can be semiconductor chip or semiconductor package part etc., and those conductive components 26 can be conductive projection or bonding wire etc..
This semiconductor structure 2 can include primer 27; this primer 27 is formed between this semiconductor subassembly 25 and this second insulating protective layer 23 (or second surface 201b of this substrate body 201), to be coated with those conductive components 26 (such as conductive projection) by this primer 27.It addition, this packing colloid 28 also can be coated with this semiconductor subassembly 25 and this primer 27.
The present invention reoffers a kind of semiconductor structure 3 as shown in Figure 3, and the cross-sectional schematic of the second embodiment that Fig. 3 is the semiconductor structure 3 illustrating the present invention.The semiconductor structure 3 of Fig. 3 is roughly the same with the semiconductor structure 2 of above-mentioned Fig. 2, therefore something in common is not repeated narration, and its Main Differences is as follows:
First insulating protective layer 21 of Fig. 3 is only formed on first surface 201a and first electric connection pad 202 of substrate body 201, and is not formed at the lower surface 22a of barrier structure 22.
The barrier structure 22 of Fig. 3 can be formed between the first surface 201a of this substrate body 201 and bearing part 24; and the lower surface 22a of this barrier structure 22 can be flush to the lower surface 21a of this first insulating protective layer 21, and the thickness (highly) of this barrier structure 22 can the thickness (highly) of barrier structure 22 more than Fig. 2 D.
Also, the packing colloid 28 of Fig. 3 can only be coated with a side surface of this barrier structure 22, and the side surface of this barrier structure 22 can be flush to the side surface 201c of this substrate body 201.
The present invention separately provides a kind of semiconductor structure 4 as shown in Figure 4, and the cross-sectional schematic of the 3rd embodiment that Fig. 4 is the semiconductor structure 4 illustrating the present invention.The semiconductor structure 4 of Fig. 4 is roughly the same with the semiconductor structure 2 of above-mentioned Fig. 2, therefore something in common is not repeated narration, and its Main Differences is as follows:
The barrier structure 22 of Fig. 4 is formed on the first insulating protective layer 21; that is this barrier structure 22 is formed between this first insulating protective layer 21 and this bearing part 24; and this barrier structure 22 can be located at the periphery 201d of first surface 201a of substrate body 201, bearing part 24 conform to the most further the perforate 211 of the first insulating protective layer 21 with in recess 212.
As from the foregoing; in the semiconductor structure of the present invention and preparation method thereof; mainly formation barrier structure is on the first surface (such as periphery) or insulating protective layer of substrate body, and surrounds the multiple electric connection pads being positioned at electric connection district by this barrier structure.
Thereby; this barrier structure can have the thickness (highly) of enough thickness (highly) or this insulating protective layer padded; with in such as the mold process of packing colloid; this packing colloid is by this insulating protective layer and the gap of this bearing part or recess (depression) to utilize this barrier structure to stop; this packing colloid is made not penetrate into those electric connection pads; thus avoid this packing colloid to pollute the surface of those electric connection pads; follow-up planting respectively on those electric connection pads connects such as soldered ball or carries out being electrically connected with operation, and then improves the yield of product.
And, the material of this barrier structure can be same as the material of those electric connection pads, and can concurrently form this barrier structure and be padded on the first surface of this substrate body with those electric connection, to reduce processing procedure and the reduction cost of this semiconductor structure.Also, this barrier structure can be electrically connected to those electric connection pad at least one of which to be used as power supply or ground connection, thus promote the electrical property efficiency of this semiconductor structure.
Additionally; the material of this barrier structure also can be same as the material of this insulating protective layer; and mode (such as mode of printing) that is identical or that repeat can be used to form this barrier structure on this insulating protective layer (or forming this insulating protective layer on this barrier structure); the thickness of this insulating protective layer or this barrier structure can be increased, and processing procedure can be simplified and reduce cost.
Above-described embodiment is only used for principle and effect thereof of the illustrative present invention, not for limiting the present invention.Above-described embodiment all can be modified by any those skilled in the art under the spirit and the scope of the present invention.Therefore the scope of the present invention, should be as listed by claims.
Claims (18)
1. a semiconductor structure, is characterized by, this semiconductor structure includes:
Substrate, it has substrate body and multiple electric connection pads, wherein, this substrate body has relative first surface and second surface, and the first surface definition of this substrate body has electric connection district, and those electric connection pads are formed at the first surface of this substrate body and are positioned at this electric connection district；
Insulating protective layer, it is formed at the first surface of this substrate body；And
On barrier structure, its first surface being formed at this substrate body or this insulating protective layer, and this barrier structure is positioned at outside this electric connection district to surround those electric connection pads.
Semiconductor structure the most according to claim 1, is characterized by, this barrier structure is formed on the periphery of the first surface of this substrate body or the insulating protective layer of this periphery.
Semiconductor structure the most according to claim 1, is characterized by, this barrier structure is formed between the periphery of the first surface of this substrate body and this electric connection district, and is separated by a spacing with this periphery.
Semiconductor structure the most according to claim 1, is characterized by, the material of this barrier structure is conductive material, and is same or different from the material of those electric connection pads.
Semiconductor structure the most according to claim 4, is characterized by, this barrier structure is electrically connected to those electric connection pad at least one of which to be used as power supply or ground connection.
Semiconductor structure the most according to claim 1, is characterized by, the material of this barrier structure is non-conducting material or insulant, and is same or different from the material of this insulating protective layer.
Semiconductor structure the most according to claim 1, is characterized by, this semiconductor structure further includes bearing part, and it fits in this insulating protective layer and this barrier structure at least one of which.
Semiconductor structure the most according to claim 7, is characterized by, this bearing part is film, stripping film or the carrying tablet with adhesion layer.
Semiconductor structure the most according to claim 1, is characterized by, this insulating protective layer is more formed on those electric connection pads, and has multiple perforate to expose outside the lower surface of those electric connection pads respectively.
Semiconductor structure the most according to claim 1, is characterized by, this semiconductor structure further includes semiconductor subassembly, and it is arranged on this substrate, and is electrically connected with this substrate through multiple conductive components.
11. semiconductor structures according to claim 1, is characterized by, this semiconductor structure further includes packing colloid, and it is formed on this substrate and is coated with the side surface of this substrate body.
The preparation method of 12. 1 kinds of semiconductor structures, is characterized by, this preparation method includes:
One substrate with substrate body and multiple electric connection pads is provided, wherein, this substrate body has relative first surface and second surface, and the first surface definition of this substrate body has electric connection district, and those electric connection pads are formed at the first surface of this substrate body and are positioned at this electric connection district；And
Forming insulating protective layer in the first surface of this substrate body, and form barrier structure on the first surface of this substrate body or this insulating protective layer, wherein, this barrier structure is positioned at outside this electric connection district to surround those electric connection pads.
The preparation method of 13. semiconductor structures according to claim 12, is characterized by, this barrier structure is formed on the periphery of the first surface of this substrate body or the insulating protective layer of this periphery.
The preparation method of 14. semiconductor structures according to claim 12, is characterized by, this barrier structure is formed between the periphery of the first surface of this substrate body and this electric connection district, and is separated by a spacing with this periphery.
The preparation method of 15. semiconductor structures according to claim 12, is characterized by, this preparation method further includes and this insulating protective layer on this substrate and this barrier structure at least one of which fitted on bearing part.
The preparation method of 16. semiconductor structures according to claim 12, is characterized by, this insulating protective layer is more formed on those electric connection pads, and has multiple perforate to expose outside the lower surface of those electric connection pads respectively.
The preparation method of 17. semiconductor structures according to claim 12, is characterized by, this preparation method further includes and arranges semiconductor subassembly on this substrate, and is electrically connected with this semiconductor subassembly and this substrate through multiple conductive components.
The preparation method of 18. semiconductor structures according to claim 12, is characterized by, this preparation method further includes and forms packing colloid and and be coated with the side surface of this substrate body on this substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| TW103145674A TW201624645A (en) | 2014-12-26 | 2014-12-26 | Semiconductor structure and fabrication method thereof |
| TW103145674 | 2014-12-26 |
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| CN105826287A true CN105826287A (en) | 2016-08-03 |
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| JPH10303336A (en) * | 1997-04-30 | 1998-11-13 | Nec Corp | Resin sealing-up structure for flip chip type semiconductor element |
| CN1388579A (en) * | 2002-06-05 | 2003-01-01 | 威盛电子股份有限公司 | High-density integrated circuit configuration structure and method |
| US20050082680A1 (en) * | 2003-09-04 | 2005-04-21 | Advanced Semiconductor Engineering, Inc. | Substrate with mesh |
| US20060091515A1 (en) * | 2004-11-03 | 2006-05-04 | Gwo-Liang Weng | Sensor chip packaging structure |
| CN101740538A (en) * | 2008-11-12 | 2010-06-16 | 三星电机株式会社 | Printed circuit board having flow preventing dam and manufacturing method thereof |
| US20140160688A1 (en) * | 2012-12-06 | 2014-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Package with Interposers |
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2014
- 2014-12-26 TW TW103145674A patent/TW201624645A/en unknown
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2015
- 2015-01-08 CN CN201510008201.0A patent/CN105826287A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10303336A (en) * | 1997-04-30 | 1998-11-13 | Nec Corp | Resin sealing-up structure for flip chip type semiconductor element |
| CN1388579A (en) * | 2002-06-05 | 2003-01-01 | 威盛电子股份有限公司 | High-density integrated circuit configuration structure and method |
| US20050082680A1 (en) * | 2003-09-04 | 2005-04-21 | Advanced Semiconductor Engineering, Inc. | Substrate with mesh |
| US20060091515A1 (en) * | 2004-11-03 | 2006-05-04 | Gwo-Liang Weng | Sensor chip packaging structure |
| CN101740538A (en) * | 2008-11-12 | 2010-06-16 | 三星电机株式会社 | Printed circuit board having flow preventing dam and manufacturing method thereof |
| US20140160688A1 (en) * | 2012-12-06 | 2014-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Package with Interposers |
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| TW201624645A (en) | 2016-07-01 |
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