TW201442002A - Method for driving electrophoretic display - Google Patents

Abstract

A method for driving electrophoretic display is employed to apply a driving voltage having a septic impulse waveform on a plurality of driving electrodes. The impulse waveform includes a data writing period and a data output period. The method includes: during the data writing period, controlling a data writing impulse to write efficient data according to a source clock impulse and remaining an output enabling impulse and a gate clock impulse being low, and during the data output period, controlling the output enabling impulse and the gate clock impulse to be high after a first time from entering the data output period, and outputting the efficient data after remaining the output enabling impulse and the gate clock impulse being high for a second time which results in displaying image by the electrophoretic display.

Description

Electrophoretic display driving method

The present invention relates to the field of electrophoretic display devices, and in particular, to a driving method for driving an electrophoretic display by a single chip microcomputer.

Currently, the electrophoretic display device must be driven by a dedicated controller, and the single-chip microcomputer system can only be used for driving TN LCD (twisted nematic liquid crystal display screen) or STN LCD (super twisted nematic liquid crystal display screen). The electrophoretic display device is matched with the single chip microcomputer system.

A conventional electrophoretic display device includes a display screen having a plurality of primitives. After each image element writes an image signal to the storage circuit via the primitive switching element, the pixel electrode is driven by a potential corresponding to the written image signal. A potential difference is generated between the primitive electrode and the common electrode. Thereby, display is performed by driving an electrophoretic element between the primitive electrode and the common electrode. 1 is a schematic diagram of pulse timing waveforms of an electrophoretic display device driven by a dedicated controller in the prior art, wherein SDCE_L represents a chip select signal pulse, SDCLK represents a source clock signal pulse, SDDO represents an image signal pulse, and SDLE represents a latch signal pulse. SDOE represents the output enable signal pulse and GDCLK represents the gate clock signal pulse. The pulse driving waveform is divided into a first time period P1, a second time period P2, and a third time period P3 according to an output timing of each signal pulse. During the driving process, in the first period P1, the controller keeps the chip select signal pulse SDCE_L at a high level, and controls the source clock signal pulse SDCLK to output a clock pulse signal with a specific timing after a delay of p1 from the initial time, and output data. The signal pulse SDDO is used to input an image data signal, and the control latch signal pulse SDLE and the gate clock signal pulse GDCLK are changed from a low level to a high level after a delay of p2 from the initial time, and the latch signal pulse SDLE is held. After the high level state duration p3, the low end state of the first time period P1 becomes low again to maintain the input state of the input interface without changing with the state change of the output terminal. The controller also maintains the gate clock signal GDCLK to a high level state to the end time of the first time period P1, and simultaneously controls the output enable signal pulse SDOE to become high after delaying the initial time p4 of the first time period P1. Flat state, ready to output image data, where p1 < p2+p3 < p4. In the second period P2, the controller controls the chip select signal pulse SDCE_L to change from a high level to a low level at an initial timing of the second period P2, so that the controller writes valid image data to the storage circuit to control The image data signal input by the data signal pulse SDDO during the second period P2 becomes a valid image data signal. At the same time, the controller maintains the gate clock signal pulse GDCLK and the output enable signal pulse SDLE high level, so that the controller outputs the valid image data written by the data signal pulse SDOE. In the third period P3, the controller chip select signal pulse SDCE_L changes from a low level to a high level to stop writing image data to the storage circuit, and maintain the source clock signal pulse SDCLK and the output enable signal pulse. After the time p5 is turned off, and the gate clock signal pulse GDCLK is held high level time p6 and then goes low, where p5>p6. Therefore, when the dedicated controller in the prior art drives the electrophoretic display device, the written valid data is output while the material signal pulse SDDO writes the valid data.

It can be seen that when the prior art electrophoretic display device is driven by a dedicated controller, since the processing speed of the dedicated controller is high, the driving waveform used can output the enabling signal while writing the effective image data. The pulse is also turned on at the same time to output the data. However, since the processing speed of the single-chip microcomputer is lower than that of the dedicated controller, when the single-chip microcomputer is driven according to the driving waveform of the prior art, when the electrophoretic display device refreshes the display content, the time of opening the driving electrode due to the original waveform is too long, resulting in the non-current driving line. The electrode is also unintentionally driven, so that the display content is unclear; and when the display data is filled by the single chip microcomputer, the driving time is lengthened due to data filling, and the electrophoretic display device is always in a working state, thereby wasting power.

In view of this, it is necessary to provide a driving method for driving an electrophoretic display by a single chip microcomputer, which can be directly driven by a single chip microcomputer to reduce the driving time of the electrophoretic display and improve the display effect.

The present invention provides an electrophoretic display driving method, in which a display primitive corresponds to a driving electrode, and a driving voltage having a pulse driving waveform is applied to a driving electrode of the electrophoretic display display primitive to realize display driving, and the pulse driving waveform includes a source. The pole clock signal pulse, the chip select signal pulse, the data signal pulse, the output enable signal pulse, and the gate clock signal pulse, the method includes:

The data signal pulse is controlled to write the valid image data according to the source clock signal pulse during the data registration period of the pulse driving waveform, and the output enable signal pulse and the gate clock signal pulse are kept at a low level. as well as

Controlling the output enable signal pulse and the gate clock signal pulse delaying the initial time of the data output period after the first time of the data output period of the pulse drive waveform to change from low level to high level and remain high The second time is the second time to output the written valid image data in the second time period, and the corresponding image is displayed by the electrophoretic display.

Compared with the prior art, the driving method of the electrophoretic display provided by the present invention simultaneously turns on the output enable signal pulse and the gate clock signal pulse after the completion of writing the image signal pulse in the storage circuit, and drives the primitive electrode to output the pre- Set the waveform. The time for opening the electrode is reduced, and the time during which the electrode is unintentionally driven is effectively avoided, thereby ensuring the display effect.

10. . . Electrophoretic display

11. . . Single chip microcomputer

12. . . Drive electrode

13. . . Display unit

SDCE_L. . . Chip select signal pulse

SDCLK. . . Source clock signal pulse

SDDO. . . Data signal pulse

SDLE. . . Latch signal pulse

SDOE. . . Output enable signal pulse

GDCLK. . . Gate clock signal pulse

P1, p2, p3, p4, p5, p6, t1, t2, t3, t4, t5. . . time

T1. . . First time period

T2. . . Second time period

T3. . . Third time period

T4. . . Fourth time period

S30, S31, S32, S33, S34. . . step

FIG. 1 is a schematic diagram of a pulse driving waveform of an electrophoretic display driven by a dedicated controller in the prior art.

2 is a schematic diagram of functional modules of an electrophoretic display according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a pulse driving waveform of an electrophoretic display driven by a single chip microcomputer according to an embodiment of the present invention.

4 is a flow chart of a driving method for driving an electrophoretic display by a single chip microcomputer according to an embodiment of the present invention.

The invention will be further described in detail below with reference to the accompanying drawings.

Please refer to FIG. 2 , which is a schematic diagram of a functional module of an electrophoretic display according to the present invention. The electrophoretic display 10 includes a single chip microcomputer 11 , a driving electrode 12 , and a display unit 13 . During the period, the display unit 13 includes a plurality of display primitives (not shown). The microcontroller 11 applies a driving voltage having a pulse waveform to the driving electrode 12, thereby driving the display elements of the display unit 13 to change correspondingly to display corresponding image.

Please refer to FIG. 3 , which is a schematic diagram of a pulse driving waveform of an electrophoretic display driven by a single chip microcomputer according to the present invention. The pulse driving waveform includes a chip select signal pulse SDCE_L, a source clock signal pulse SDCLK, a data signal pulse SDDO, a latch signal pulse SDLE, and an output enabler. The signal pulse SDOE and the gate clock signal pulse GDCLK.

Please refer to FIG. 4 , which is a flowchart of a driving method for driving an electrophoretic display by a single chip microcomputer according to the present invention. The driving method of the electrophoretic display uses the pulse driving waveform to drive a driving electrode corresponding to a display element of the electrophoretic display to realize display driving. The pulse drive waveform is divided into a first time period T1, a second time period T2, a third time period T4, and a fourth time period T4 according to an output timing of each signal pulse. The method comprises the following steps:

Step S30, in the first time period T1, the single chip outputs and holds the chip select signal pulse SDCE_L to a high level, and controls to output a source clock signal pulse SDCLK with a specific timing after delaying the t1 time after the chip select signal pulse SDCE_L is outputted. . In the present embodiment, the source clock signal pulse SDCLK is a periodic pulse signal having a specific timing. The single chip microcomputer further controls outputting the data signal pulse SDDO to input the image data signal in the first time period T1, and maintaining the latch signal pulse SDLE, the output enable signal pulse SDOE, and the gate clock signal pulse GDCLK as low power. level.

Since the chip select signal pulse SDCE_L continues to be high for the first time period T1, the single chip does not write valid image data to the storage circuit of the electrophoretic display at the first time T1, therefore, the data signal pulse SDDO is at the first time. The image data signal input by the segment T1 is an invalid image data signal. At this time, the electrophoretic display has no image output and display.

Step S31, in the second time period T2, the single chip microcomputer controls the chip select signal pulse SDCE_L to change from a high level to a low level at an initial moment of the second time period T2, and keeps outputting the source clock signal pulse SDCLK to continue control. The data signal pulse SDDO inputs an image data signal, and controls the data signal pulse SDDO to write valid image data according to the source clock signal pulse SDCLK during the second time period T2. At the same time, the MCU keeps the latch signal pulse SDLE, the output enable signal pulse SDOE, and the gate clock signal pulse GDCLK at a low level, so that the electrophoretic display does not output and update when writing valid image data to the storage circuit. Image data displayed on the electrophoretic display.

When the chip select signal pulse SDCE_L changes from a high level to a low level, the single chip microcomputer starts to write valid image data to the storage circuit, so the image data signal input by the data signal pulse SDDO in the second time period T2 is invalid. The image data signal becomes a valid image data signal. Therefore, in the second time period T2, the single chip microcomputer controls the data signal pulse SDDO to input the effective image data signal according to the source clock signal pulse SDCE_L, thereby realizing writing of the image data.

Step S32, in the third time period T3, the single chip control chip selection signal pulse SDCE_L changes from low level to high level at the initial time of the third time period T3, and the image data signal input by the control data signal pulse SDDO becomes invalid. The image data signal is turned off while the output source clock signal pulse SDCLK is held for a duration t2. Similarly, in the third period T3, the microcontroller keeps the latch signal pulse SDLE, the output enable signal pulse SDOE, and the gate clock signal pulse GDCLK at a low level.

When the chip select signal pulse SDCE_L changes from low level to high level, the single chip microcomputer stops writing valid image data to the storage circuit, so the image data signal input by the data signal pulse SDDO in the third time period T3 is The valid image data signal becomes an invalid image data signal. Therefore, in the third period T3, the microcontroller stops writing of image data.

Step S33, in the fourth time period T4, the single chip keeps the chip select signal pulse SDCE_L at a high level, and controls the output enable signal pulse SDOE and the gate clock signal pulse GDCLK to change from a low level at the same time after the delay t3 time. High level, and keep the enable signal pulse SDOE and the gate clock signal pulse GDCLK in a high state for t4 time, to control the effective image data output written by the data signal pulse SDDO during the t4 time period, so that the The electrophoretic display accordingly displays the corresponding image.

The microcontroller also controls the latch signal pulse SDLE to change from a low level to a high level at an initial timing of the fourth period T4 for maintaining the input of the chip select signal pulse SDCE_L, the source clock signal pulse SDCLK, and the data signal pulse SDDO. The state does not change with the state change of the output terminal, the input state is saved to the output, and the latch signal pulse SDLE is kept from the high level to the low level after the t5 time elapses, thereby releasing the chip select signal pulse SDCE_L The source clock signal pulse SDCLK and the data signal pulse SDDO are locked. In the present embodiment, t3>t5.

In the fourth time period T4, the single chip keeps the chip select signal pulse SDCE_L at a high level to ensure that the single chip no longer writes valid image data to the storage circuit, thereby keeping the image data signal input by the data signal pulse SDDO invalid. Image data signal.

Step S34, the MCU simultaneously controls the output enable signal pulse SDOE and the gate clock signal pulse GDCLK to change from the high level to the low level at the end time of the fourth time period T4, so as to stop outputting the valid image data, correspondingly The image data displayed on the ground electrophoresis display stops updating.

The single chip device applies a voltage signal having the driving waveform to the driving electrode of the electrophoretic display display primitive to complete display and update of the image data of the one frame of the electrophoretic display, and repeatedly applies a voltage signal having the driving waveform to the display of the electrophoretic display The driving electrode of the primitive completes the display and update of all image data of the electrophoretic display.

Because the electrophoretic display drives the driving electrode of a certain row of picture elements when displaying the next frame of image data, since the charged particles corresponding to the primitives in the electrophoretic display can maintain the original position when not driven by the voltage, that is, After the electric image, the image does not disappear, so the brightness of the image corresponding to the picture element that is not driven by other element driving electrodes is not attenuated. After the data signal pulse is again written into the valid image data at the position of the primitive at which the primitive driving electrode is driven, the written effective image data is output correspondingly, thereby enhancing the display effect of the electrophoretic display.

Using the driving method of the electrophoretic display described above, after the effective image data is written in the storage circuit, the output enable signal pulse SDOE and the gate clock signal pulse GDCLK are simultaneously turned on, the primitive electrode is driven, and the preset waveform is output. The output and display of the valid image data of the write is achieved. Thereby, the time for opening the electrode is reduced, the time during which the electrode is unintentionally driven is effectively avoided, and the display effect is ensured.

It is to be understood that those skilled in the art can make various other changes and modifications in accordance with the technical concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.

SDCE_L. . . Chip select signal pulse

SDCLK. . . Source clock signal pulse

SDDO. . . Data signal pulse

SDLE. . . Latch signal pulse

SDOE. . . Output enable signal pulse

GDCLR. . . Gate clock signal pulse

T1, t2, t3, t4, t5. . . time

T1. . . First time period

T2. . . Second time period

T3. . . Third time period

T4. . . Fourth time period

Claims (8)

An electrophoretic display driving method, wherein a display element of the electrophoretic display corresponds to a driving electrode, and a driving voltage having a pulse driving waveform is applied to a driving electrode of the electrophoretic display display primitive to realize display driving, wherein the pulse driving waveform includes a source The clock signal pulse, the chip select signal pulse, the data signal pulse, the output enable signal pulse, and the gate clock signal pulse are improved in that the method includes:
Controlling, by the data registration period of the pulse driving waveform, the data signal pulse to write valid image data according to the source clock signal pulse, and maintaining the output enable signal pulse and the gate clock signal pulse at a low level; and controlling the output enable signal pulse and the gate clock signal pulse to delay the initial time of the data output period after the first time of the data output period of the pulse driving waveform It is high level and remains high for a second time to output the written valid image data during the second time period, and the corresponding image is displayed by the electrophoretic display. The electrophoretic display driving method according to claim 1, wherein "the data signal pulse is controlled to write valid image data according to the source clock signal during a data registration period of the pulse driving waveform" include:
Maintaining the chip select signal pulse to a high level during a first period of the data registration period, and controlling outputting a source clock signal pulse having a specific timing after delaying the third time after the chip select signal pulse is outputted Controlling the output of the data signal pulse to input an image data signal, and maintaining the output enable signal pulse and the gate clock signal pulse at a low level;
Controlling, during a second time period of the data registration period, that the chip select signal pulse changes from a high level to a low level at an initial time of the second time period, and keeps outputting the source clock signal pulse. Continue controlling the data signal pulse to write valid image data according to the source clock signal pulse, and maintaining the output enable signal pulse and the gate clock signal pulse at a low level; and logging in the data The third time period of the time period controls the chip select signal pulse to change from a low level to a high level at an initial time of the third time period, and the image data signal input by the control data signal pulse becomes invalid. Like the data signal, the output of the source clock signal pulse is kept for a fourth time after the source clock signal pulse is turned off, and the output enable signal pulse and the gate clock signal pulse are kept at a low level. The electrophoretic display driving method of claim 2, wherein the pulse waveform further comprises a latching signal pulse, the method further comprising:
Holding the latch signal pulse at a low level during the first, second, and third time periods; and controlling the latch signal pulse to change from a low level at an initial time of a data output period of the pulse drive waveform It is high to maintain the state of the chip select signal pulse, the source clock signal pulse, and the data signal pulse without changing with the state of the output terminal. The electrophoretic display driving method according to claim 3, further comprising:
The latch signal pulse is kept from a high level to a low level after the fifth time period to release the locked state of the chip select signal pulse, the source clock signal pulse, and the data signal pulse. The electrophoretic display driving method according to claim 4, wherein the first time is greater than the fifth time. The electrophoretic display driving method according to claim 1, wherein the source clock signal pulse is a periodic pulse signal having a specific timing. The electrophoretic display driving method according to claim 1, wherein the method further comprises:
Controlling, at the end of the data output period of the pulse driving waveform, the output enable signal pulse and the gate clock signal pulse simultaneously changing from a high level to a low level to stop outputting the effective image data. The image displayed on the electrophoretic display stops updating. The electrophoretic display driving method according to claim 7, wherein the driving voltage having the pulse driving waveform is repeatedly applied to the driving electrodes of the electrophoretic display display primitives to realize display driving of all the images.