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TW201249975A - CMP slurry and polishing method of semiconductor substrate - Google Patents

CMP slurry and polishing method of semiconductor substrate Download PDF

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Publication number
TW201249975A
TW201249975A TW101115568A TW101115568A TW201249975A TW 201249975 A TW201249975 A TW 201249975A TW 101115568 A TW101115568 A TW 101115568A TW 101115568 A TW101115568 A TW 101115568A TW 201249975 A TW201249975 A TW 201249975A
Authority
TW
Taiwan
Prior art keywords
polishing
semiconductor substrate
main surface
substrate
cmp
Prior art date
Application number
TW101115568A
Other languages
Chinese (zh)
Inventor
Yutaka Nomura
Hiroshi Nakagawa
Hisanori Takusari
Masahiro Sakashita
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of TW201249975A publication Critical patent/TW201249975A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1409—Abrasive particles per se
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1454—Abrasive powders, suspensions and pastes for polishing
    • C09K3/1463—Aqueous liquid suspensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

CMP slurry and polishing method of semiconductor substrate including polishing steps of the invention are provided. The CMP slurry includes polishing grains containing ceria grains and silica grains, a compound (excluding azoles) which a first acid dissociation constant is equal to or less than 7, a basic compound and a persulfate. A range of pH of the CMP slurry is from 9.0 to 12.0. The polishing method of the semiconductor substrate includes polishing a semiconductor substrate 300 from back 1b side to expose a conductive component 7 on the back 1b side by using the CMP slurry so as to form a through via structure having TSVs 7a and 7b. The semiconductor substrate 300 includes a substrate body 1 where hollow parts 3a and 3b are formed only on an opening of a surface 1a, a conductive component 7 disposed in the hollow parts 3a and 3b and should become TSVs 7a and 7b, and insulating layers 5a and 5b disposed between the substrate body 1 and the conductive component 7 in the hollow parts 3a, and 3b.

Description

20124997^ 六、發明說明： 【發明所屬之技術領域】 本發明是有關於CMP研磨液及半導體基板的研磨方 法，特別是有關於適用於半導體基板的主面加工的CMP 研磨液及半導體基板的研磨方法。 【先前技術】 至今歷經長久時間’半導體元件（device)的高性能 化為根據元件微縮準則（scaHng rule)為基礎的微細化及 高積體化而成（例如參照下述非專利文獻1)。但是，近 年如此的方法(approach)已逐漸面臨極限，往系統全體（包 括設計或封裝）的高性能化以及方向性亦逐漸改變。 如此的系統全體的高性能化的手法已經過各種檢討， 例如’將 LSI (Large-scale Integrated Circuit :大規模積體 電路）晶片往縱方向（高度方向）高密度積層的三次元封 裝技術也是其中一種（例如參照下述非專利文獻2)。將 三次元封裝技術中特別被稱為TSV ( Through-silicon Via : 矽貫通介層窗）的LSI晶片透過貫通的配線（貫通電極） 而連接上下配置的LSI晶片的技術已受到注目。 形成TSV的手法已被多次提出，配線步驟中形成TSV 的手法或前步驟結束後從基板表面形成TSV的手法亦經 檢討。例如，具有TSV構造的半導體基板如下述所製造。 首先’於僅在表面（其中一方的主面）形成有開口的中空 部的半導體基板（例如矽基板）的該表面上，沿著中空部 的形狀形成用以絕緣TSV的絕緣層（例如矽氧化膜（二氧 4 201249975 4223lpif 化石夕膜））。接著，將身為TSV材料的導電構件（例如銅 層等的導電體層）配置於中空部内。繼之，使用研磨機 Μ*0從背面（另一方的主面）側磨削半導體基板， 直到絕緣層即將露{ij的程度㈣半導體基板薄層化後，藉 由研磨機的研磨將產生在半導縣板的#面的磨削傷（磨 削痕）消除。在此情況下，藉由從背面側對半導體基板進 行研磨而除去半導體基板的背面側的表層部，使絕緣層在 半導體基板的背面側顯現。然後，藉由從背面侧更加對半 導體基板進行研磨而除去絕緣層，使導電構件在半導體基 板的背面侧露出而形成TSV。為了得到如此的TSV，在用 以消除磨削傷的研磨中，必須研磨除去已在被研磨面露出 的半導體基板的背面側的表層部或絕緣層。 [先前技術文獻] [專利文獻] [專利文獻1]美國專利第4169337號說明書 [專利文獻2]日本專利特公昭57-58775號公報 [非專利文獻] [非專利文獻 1] IEEE J. Solid-State Circuits，vol. SC-9, pp. 256-268(1974).20124997^ VI. Description of the Invention: [Technical Field] The present invention relates to a polishing method for a CMP polishing liquid and a semiconductor substrate, and more particularly to polishing of a CMP polishing liquid and a semiconductor substrate which are applied to main surface processing of a semiconductor substrate. method. [Prior Art] The high performance of the semiconductor device has been made to be finer and more integrated based on the scaHng rule (see, for example, Non-Patent Document 1 below). However, in recent years, such approaches have gradually come to the limit, and the high performance and directionality of the entire system (including design or packaging) has gradually changed. Various methods for improving the performance of such a system have been reviewed. For example, a three-dimensional packaging technique in which a LSI (Large-scale Integrated Circuit) wafer is stacked in the vertical direction (height direction) is also included. One (see, for example, Non-Patent Document 2 below). In the ternary packaging technology, an LSI wafer in which a TSV (Through Through Silicon via) is passed through a through wiring (through electrode) to connect an LSI wafer arranged vertically is attracting attention. The method of forming the TSV has been repeatedly proposed, and the method of forming the TSV in the wiring step or the method of forming the TSV from the surface of the substrate after the completion of the previous step is also reviewed. For example, a semiconductor substrate having a TSV structure is manufactured as follows. First, on the surface of a semiconductor substrate (for example, a germanium substrate) in which only a hollow portion having an opening is formed on the surface (one of the main faces), an insulating layer for insulating the TSV is formed along the shape of the hollow portion (for example, ruthenium oxide) Membrane (dioxy 4 201249975 4223lpif fossil film)). Next, a conductive member (for example, a conductor layer such as a copper layer) which is a TSV material is placed in the hollow portion. Then, the semiconductor substrate is ground from the back side (the other main surface) side using a grinder Μ*0 until the insulating layer is about to be exposed to the extent of ij. (4) After the semiconductor substrate is thinned, the grinding by the grinder will be generated. The grinding damage (grinding marks) of the #面面 of the semi-conducting plate is eliminated. In this case, the surface layer portion on the back surface side of the semiconductor substrate is removed by polishing the semiconductor substrate from the back side, and the insulating layer is formed on the back side of the semiconductor substrate. Then, the insulating layer is removed by polishing the semiconductor substrate from the back side, and the conductive member is exposed on the back side of the semiconductor substrate to form a TSV. In order to obtain such a TSV, in the polishing for eliminating the abrasion, it is necessary to polish and remove the surface layer portion or the insulating layer on the back side of the semiconductor substrate which is exposed on the surface to be polished. [PRIOR ART DOCUMENT] [Patent Document 1] US Patent No. 4,169,337 [Patent Document 2] Japanese Patent Publication No. Sho 57-58775 [Non-Patent Document] [Non-Patent Document 1] IEEE J. Solid- State Circuits, vol. SC-9, pp. 256-268 (1974).

[非專利文獻 2] Technical Digest of International Electron Devices Meeting(IEEE, Piscataway, NJ, 2001), p.23.1.1. 順帶一提，在用以消除磨削傷的研磨中，有使用半導 體基板製造用的研磨液的情況’其中半導體基板製造用的 201249975 ipif 研磨液是將矽等的半導體基板的構成材料當作研磨對象。 作為半導體基板製造用的研磨液，例如可以列舉含有一次 粒子的粒徑為4 nm〜200 nm (較佳的是4 nm〜10〇 nm)的 範圍的膠體（colloidal)形態的矽氧與矽氧凝膠的任一種 以及水溶性胺的研磨液（例如參照上述專利文獻1)。 但是，如此的半導體基板製造用的研磨液因為是將石夕 荨的半導體基板的構成材料作為主要的研磨對象，所以在 使用該研磨液的情況下，絕緣層的研磨速度非常低。因此， 使用如此的半導體基板製造用的研磨液，即便對披覆導電 構件的絕緣層進行研磨，絕緣層會殘留而使導電構件難以 露出。在此情況下’為了使導電構件露出，需要額外地使 用絕緣層研磨用的研磨液對絕緣層進行研磨的步驟或藉由 濕式蝕刻（wet etching )、乾式蚀刻（dry etching)等手法 除去絕緣層的步驟，使用以得到貫通電極的步驟繁雜化。 【發明内容】 本發明為了解決前述問題，目的為提供一種能夠以優 異的研磨速度對半導體基板、絕緣層及導電構件進行研磨 的CMP研磨液以及使用該CMP研磨液的半導體基板的研 磨方法。 在半導體基板内部形成多個導電構件的情況下，從基 板的被研磨面的導電構件的深度因半導體基板内的導電構 件的位置或配置而互相不同。在此情況下，為了使半導體 基板内的全部導電構件在被研磨面露出，必須持續研磨直 到在自被研磨面最深的位置形成的導電構件露出為止，且 6 201249975 4223lpif 連同絕緣層或半導體基板對已露出的導電構件進行研磨。 因此’本㈣者們對於⑽研磨液，而考慮到必須以優 異的研磨速麟半導縣板、絕緣層及導電構件進行研磨。 本發明的CMP研磨液包括含飾氧粒子及石夕氧粒子的 研磨粒、第一酸解離常數為7以下的化合物（但是唑類除 外）、驗性化合物及過硫酸鹽，且該CMp研磨液的pH為 9.0〜12.0。 此外，酸解離常數（pKa)為從酸釋出氫離子的解離 反應的平衡常數Ka的負的常用對數（對數的倒數），在 使用具有多個pKa的化合物的情況下，將第一段的酸解離 常數稱為「第一酸解離常數（pKal)」。此外，本發明中， 第一酸解離常數為7以下的化合物亦可為具有單一 pKa的 化合物，在此情況下，將該單一的pKa稱為「pKal」。作 為前述pKal的值，例如可以參照化學手冊基礎篇π (修 訂5版，丸善（股份有限公司））。 根據本發明的CMP研磨液，能夠以優異的研磨速度 對半導體基板、絕緣層及導電構件進行。根據如此的本發 明’不用額外地設定使步驟繁雜化的用以使導電構件露出 的步驟，可以容易地形成貫通電極構造。 此外’根據本發明，在半導體基板内部形成多個應該 成為貫通電極的導電構件時，即便在從基板的被研磨面的 導電構件的深度互相不同的情況下，可以容易地形成具有 多個貫通電極的貫通電極構造。例如，根據本發明，使用 包括在自被研磨面較淺的位置形成的第1導電構件以及在 201249975 4223lpif 自被研磨面較深的位置形成的第2導電構件的半導體基 板’可以容易地形成具有多個貫通電極的貫通電極構造。 亦即，首先，使用本發明的CMp研磨液同時對彼覆第1 導電構件的絕緣層及半導體基板的表層部進行研磨，藉此 使第1導電構件在被研磨面露出而得到第1貫通電極。進 而’使用本發明的CMP研磨液同時對在被研磨面露出的 半導體基板的表層部、絕緣層及第1導電構件進行研磨， 藉此使第2導電構件在被研磨面露出而得到第2貫通電 極。藉此可以容易地形成具有多個貫通電極的貫通電極構 造。 第一酸解離常數為7以下的化合物較佳的是包括胺基 酸。胺基酸較佳的是α-胺基酸。在此情況下，能夠以更加 優異的研磨速度對半導體基板、絕緣層及導電構件進行研 磨。 第一酸解離常數為7以下的化合物亦可包括含羧基的 有機酸。即便在此情況下，能夠以更加優異的研磨速度對 半導體基板、絕緣層及導電構件進行研磨。 鹼性化合物較佳的是包括選自含氮鹼性化合物及無機 鹼性化合物的至少一種’更佳的是包括選自氫氧化鉀 (potassium hydroxide)、氫氧化鈉（s〇dium hydroxide)、 氫氧化四曱敍（tetramethylammonium hydroxide)及氫氧化 錄（ammonium hydroxide)的至少一種。在此情況下，能 夠以更加優異的研磨速度對半導體基板、絕緣層及導電構 件進行研磨。 8 201249975 4223 lpif 鹼性化合物的含有量較佳的是0.10質量％以上。在此 情況下，能夠以更加優異的研磨速度對半導體基板、絕緣 層及導電構件進行研磨。 過硫酸鹽較佳的是包括選自過硫酸鉀及過硫酸銨的至 少一種。在此情況下，在此情況下，能夠以更加優異的研 磨速度對半導體基板、絕緣層及導電構件進行研磨。 本發明的CMP研磨液亦可用於從另一方的主面側對 半導體基板（此半導體基板包括基板本體以及導電構件。 基板本體形成有僅在其中一方的主面上開口的中空部。導 電構件配置於中空部内且應該成為貫通電極）的基板本體 進行研磨，使導電構件在前述另一方的主面侧露出而形成 貫通電極構造。此外，本發明的CMp研磨液亦可用於從 其中-方的主面侧或另-方的主面側對半導體基板（此半 導體基板包括基板本體及貫通電極。基板本體形成有從其 中-方的主面貫通至另—方的主面的貫通孔。貫通電極配 置於貫通孔内）的基板本體進行研磨。 本發明的半導體基板的研磨方法亦可包括如下的研磨 步驟：使用前述CMP研磨液從另—方的主面側對半導體 基板（此半導縣板包減板树及導電構件。基板本體 形成有僅在其中-方的主面上開口的巾空部。導電構件配 置於中空㈣且肋成為貫通電極）的基 磨，使導電構件麵述另_方的μ鑛“形成 =極方法，容易地形成具有多個 9 201249975 4223 iplf 此外，本發明的半導體基板的研磨方法亦可包括如下 的研磨步驟：使用前述CMP研磨液從前述其中一方的主 面侧或前述另一方的主面側對半導體基板（此半導體基板 包括基板本體及貫通電極。基板本體形成有從其中一方的 主面貫通至另一方的主面的貫通孔，貫通電極配置於貫通 孔内）的基板本體進行研磨。如此的研磨方法中，使用能 夠以優異的研磨速度對半導體基板、絕緣層及導電構件進 行研磨的CMP研磨液，藉此可以一面良好地保持半導體 基板、絕緣層及貫通電極在被研磨面露出的狀態，一面調 整貫通電極的長度。藉此，在半導體基板内形成應該成為 第1貫通電極以及第2貫通電極的導電構件的情況下，可 以一面調整第1貫通電極的長度，一面形成第2貫通電極。 本發明的半導體基板的研磨方法在研磨步驟前亦可更 佳地包括從研磨步驟中被研磨的主面側對基板本體進行磨 削的步驟。 本發明的半導體基板的研磨方法中，較佳的是在研磨 步驟中使用蕭氏（shore) D硬度為30〜90的研磨布（研磨 塾（pad))對基板本體進行研磨。在此情況下，可以抑制 已在被研磨面露出的貫通電極被過度研磨，可以容易地降 低該被研磨面中半導體基板及貫通電極的深度差（高低 差）。 [發明的效果][Non-Patent Document 2] Technical Digest of International Electron Devices Meeting (IEEE, Piscataway, NJ, 2001), p. 23.1.1. Incidentally, in the polishing for eliminating the grinding damage, the use of a semiconductor substrate is used. In the case of the polishing liquid, the 201249975 ipif polishing liquid for manufacturing a semiconductor substrate is a constituent material of a semiconductor substrate such as tantalum. As the polishing liquid for producing a semiconductor substrate, for example, a colloidal form of helium oxygen and helium oxide having a primary particle diameter of 4 nm to 200 nm (preferably 4 nm to 10 nm) is exemplified. Any of the gels and the water-soluble amine polishing liquid (for example, refer to Patent Document 1 mentioned above). However, since the polishing liquid for producing a semiconductor substrate is a constituent material of the semiconductor substrate of the stone substrate, the polishing rate of the insulating layer is extremely low when the polishing liquid is used. Therefore, with such a polishing liquid for producing a semiconductor substrate, even if the insulating layer covering the conductive member is polished, the insulating layer remains and the conductive member is hardly exposed. In this case, in order to expose the conductive member, it is necessary to additionally polish the insulating layer using a polishing liquid for polishing the insulating layer or to remove the insulating by wet etching or dry etching. The step of layering is complicated by the step of using the through electrode. SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a CMP polishing liquid capable of polishing a semiconductor substrate, an insulating layer, and a conductive member at an excellent polishing rate, and a polishing method of a semiconductor substrate using the CMP polishing liquid. In the case where a plurality of conductive members are formed inside the semiconductor substrate, the depth of the conductive members from the polished surface of the substrate differs from each other due to the position or arrangement of the conductive members in the semiconductor substrate. In this case, in order to expose all the conductive members in the semiconductor substrate on the surface to be polished, it is necessary to continue grinding until the conductive members formed at the deepest position from the surface to be polished are exposed, and 6 201249975 4223lpif together with the insulating layer or the semiconductor substrate pair The exposed conductive member is ground. Therefore, in the case of (10) the polishing liquid, it is considered that the polishing must be performed by using the excellent grinding speed of the semi-leaf plate, the insulating layer and the conductive member. The CMP polishing liquid of the present invention comprises abrasive particles containing oxygen-containing particles and agglomerated oxygen particles, a compound having a first acid dissociation constant of 7 or less (except for azoles), an inspective compound, and a persulfate, and the CMp slurry The pH is 9.0 to 12.0. Further, the acid dissociation constant (pKa) is a negative common logarithm (reciprocal of the logarithm) of the equilibrium constant Ka of the dissociation reaction of the hydrogen ion released from the acid, and in the case of using a compound having a plurality of pKa, the first segment The acid dissociation constant is called the "first acid dissociation constant (pKal)". Further, in the present invention, the compound having a first acid dissociation constant of 7 or less may be a compound having a single pKa, and in this case, the single pKa is referred to as "pKal". As the value of the aforementioned pKal, for example, the chemistry manual basics π (Revision 5, Maruzen (Company)) can be referred to. According to the CMP polishing liquid of the present invention, the semiconductor substrate, the insulating layer and the conductive member can be formed at an excellent polishing rate. According to the present invention, the through electrode structure can be easily formed without additionally setting the step of exposing the conductive member to the step of making the step complicated. Further, according to the present invention, when a plurality of conductive members to be through electrodes are formed inside the semiconductor substrate, even when the depths of the conductive members from the polished surface of the substrate are different from each other, a plurality of through electrodes can be easily formed. Through-electrode structure. For example, according to the present invention, a semiconductor substrate 'including a first conductive member formed at a position shallower from the surface to be polished and a second conductive member formed at a position where the surface of the surface to be polished is deeper at 201249975 4223lp can be easily formed. A through electrode structure of a plurality of through electrodes. In other words, first, the insulating layer of the first conductive member and the surface layer portion of the semiconductor substrate are simultaneously polished by using the CMp polishing liquid of the present invention, whereby the first conductive member is exposed on the surface to be polished to obtain the first through electrode. . Further, the CMP polishing liquid of the present invention simultaneously polishes the surface layer portion, the insulating layer, and the first conductive member of the semiconductor substrate exposed on the surface to be polished, thereby exposing the second conductive member to the surface to be polished to obtain the second through-hole. electrode. Thereby, the through electrode structure having a plurality of through electrodes can be easily formed. The compound having a first acid dissociation constant of 7 or less preferably includes an amino acid. The amino acid is preferably an α-amino acid. In this case, the semiconductor substrate, the insulating layer, and the conductive member can be polished at a more excellent polishing rate. The compound having a first acid dissociation constant of 7 or less may also include a carboxyl group-containing organic acid. Even in this case, the semiconductor substrate, the insulating layer, and the conductive member can be polished at a more excellent polishing rate. The basic compound preferably includes at least one selected from the group consisting of a nitrogen-containing basic compound and an inorganic basic compound. More preferably, it includes a selected from the group consisting of potassium hydroxide, sodium hydroxide, and hydrogen. At least one of tetramethylammonium hydroxide and ammonium hydroxide. In this case, the semiconductor substrate, the insulating layer, and the conductive member can be polished at a more excellent polishing rate. 8 201249975 4223 The content of the lpif basic compound is preferably 0.10% by mass or more. In this case, the semiconductor substrate, the insulating layer, and the conductive member can be polished at a more excellent polishing rate. The persulfate salt preferably comprises at least one selected from the group consisting of potassium persulfate and ammonium persulfate. In this case, in this case, the semiconductor substrate, the insulating layer, and the conductive member can be polished at a more excellent polishing speed. The CMP polishing liquid of the present invention can also be used to face a semiconductor substrate from the other main surface side (this semiconductor substrate includes a substrate body and a conductive member. The substrate body is formed with a hollow portion that is opened only on one of the main surfaces. Conductive member arrangement The substrate body in the hollow portion and which should be the through electrode is polished, and the conductive member is exposed on the other main surface side to form a through electrode structure. Further, the CMp polishing liquid of the present invention may be used for the semiconductor substrate from the main surface side or the other main surface side of the main surface (the semiconductor substrate includes the substrate main body and the through electrode. The substrate main body is formed from the side thereof) The main surface penetrates to the through-hole of the other main surface, and the substrate body of the through-electrode is disposed in the through-hole is polished. The polishing method of the semiconductor substrate of the present invention may further include a polishing step of using the CMP polishing liquid to face the semiconductor substrate from the other main surface side (the semi-conductor plate-reducing plate and the conductive member are formed. Only the empty portion of the towel opening on the main surface of the square. The conductive member is disposed in the hollow (four) and the rib is the base electrode of the through electrode, and the conductive member is described as the other method. Forming a plurality of 9 201249975 4223 iplf Further, the polishing method of the semiconductor substrate of the present invention may further include a polishing step of using the CMP polishing liquid to face the semiconductor substrate from one of the main surface sides or the other main surface side (The semiconductor substrate includes a substrate body and a through electrode. The substrate body is formed with a through hole through which one of the main surfaces penetrates to the other main surface, and the through electrode is disposed in the through hole). The polishing method is performed. A CMP polishing liquid capable of polishing a semiconductor substrate, an insulating layer, and a conductive member at an excellent polishing rate is used. The length of the through electrode is adjusted while the semiconductor substrate, the insulating layer, and the through electrode are exposed to the surface to be polished, and the conductive member to be the first through electrode and the second through electrode is formed in the semiconductor substrate. In the case of the first through electrode, the second through electrode can be formed while adjusting the length of the first through electrode. The method of polishing the semiconductor substrate of the present invention may more preferably include the main surface side to be polished from the polishing step before the polishing step. The step of grinding the substrate body. In the polishing method of the semiconductor substrate of the present invention, it is preferable to use a polishing cloth (pad) to which the Shore D hardness is 30 to 90 in the polishing step. In this case, it is possible to suppress excessive penetration of the through electrode exposed on the surface to be polished, and it is possible to easily reduce the depth difference (height difference) between the semiconductor substrate and the through electrode in the surface to be polished. ]

本發明提供能夠以優異的研磨速度對半導體基板、絕 緣層及導電構件進行研磨的CMP研磨液以及使用該CMP 201249975 4223lpif 研磨液的半導體基板的研磨方法。根據如此的本發明，不 用額外地設定使步驟繁雜化的用以使導電構件露出的步 驟’可以容易地形成貫通電極構造。此外，根據本發明， 在半導體基板内形成多個應該成為貫通電極的導電構件 時’即便在從基板的被研磨面的導電構件的深度互相不同 的情況下，可以容易地形成具有多個貫通電極的貫通電極 構造。 【實施方式】 以下將詳細說明本發明的一實施形態的CMP研磨液 以及使用該CMP研磨液的半導體基板的研磨方法。 &lt;CMP研磨液&gt; 本實施形態的CMP研磨液包括研磨粒（abmsive grain)(研磨粒子）、第一酸解離常數（pKal)為7以下 的化合物（但是，唑類除外）、鹼性化合物以及氧 (研磨粒） _本實施形態的CMP研磨液至少包括作為研磨粒的鈽 氧（cena)粒子（氧化鈽粒子）以及矽氧（silica)粒子（二 氧化矽粒子）。在使用如此的研磨液研磨半導體基板（例如 矽基板）以及絕緣層（例如矽氧化膜）已露出的被研磨面 的情況下，可以考慮主要藉由矽氧粒子研磨半導體基板， 主要藉由鈽氧粒子研磨絕緣層，但是全體來看的話，藉由 兩者的相乘效果可得到良好的研磨速度。作為矽氧粒^， 較佳的是膠體矽氧粒子。 此外，視需要亦可併用其他研磨粒。作為可併用的其 201249975 他研磨粒，具體而言可列舉包括氧化鋁（alumina)、氧化 鈦（titania)或氧化锆（zirc〇nia)等無機材料的研磨粒； 包括有機聚合物等有機材料的研磨粒；包括有機材料及無 機材料的複合研磨粒等。 … 從在研磨液中的分散安定性良好且因CMp而發生的 研磨傷（scratch)的發生數少的觀點來看，鈽氧粒子的平 均粒徑（二次粒徑）較佳的是5〇〇 nm以下更佳的是 nm以下。從容易得到實用的研磨速度的觀點來看，鈽氧粒 子的平均粒控較佳的是1〇 nm以上，更佳的是％咖以 上，進一步更佳的是50 nm以上。 從容易充分地提高絕緣層（例如矽氧化膜）的研磨迷 广的觀點來看，鈽氧粒子的含有量在研磨液全質量基準中 触的是_質量仙上，更佳的是G.G5質量％以^^ 上步更,的是〇.1〇質量％以上，特佳的是〇2G質量％以 從可以谷易抑制研磨液中的粒子凝集的觀點來看，鈽 詈f子的含有量在研磨液全質量基準中較佳的是2.00質 質Si下更佳的*⑽質量％以下’進一步更佳的是0·80 從在研磨液中的分散安定性良好且因CMP而發 （scratch)的發生數少的觀點來看，矽氧粒子的平 ηηΐΐΓ (二次粒徑）較佳的是2〇〇nm以下，更佳的是100 為石下。特佳的是以平均粒徑200nm以下的膠體矽氧作 石夕氧t子’更特佳的是以平均粒徑100 nm以下的膠體 W為石夕氧粒子。從容易得到實用的研磨速度的觀點來 12 201249975 4223 lpif 看，矽氧粒子的平均粒徑較佳的是5nm以上， nm以上’進一步更佳的是9nm以上。 的疋7 、，二，充分地提高半導縣板（例如絲板）的研磨 、、又、觀點來看’⑪氧粒子的含有量在研磨液全質量 中較佳的是0.01質4%以上，更佳的是GG5 f量％以1， 進-步更佳岐G.1G質量％以上。從抑制研磨傷等的缺 發生且容^得到提高滿足含有量的研磨速度的效果的觀點 來看’梦氧粒子的含有量在研磨液全質量基準巾較佳的a 5.00質量％以下，更佳的是！ 〇〇質量％以下，進 = 的是0.50質量％以下。 /更佳 此外，可以藉由雷射繞射式粒度分布計（例如掘場 作所製造的LA-920)測量前述鈽氧粒子的平均粒徑。具體 而言’可以使用掘場製作所製造&amp; LA_92〇 (光源氣氮雷 射及鶴雷射）以如下的方式測量。首先，㈣相對於氮_ 氖雷射的測量時透料（H)變為65%〜75%崎氧粒子分 散液並將其作為測量樣品。然後將該測量樣品放1 LA-920 ’藉由將相對折射率設為丨⑼（氧化鈽的理論折射 率2.128/水的折射率來測量，可以得到作為算數平 均徑（mean size)的鈽氧粒子的平均粒徑（二次粒徑）。 此外，可以藉由動態光散射方式粒度分布計（例如 COULTER Electronics 公司製造，商品名 c〇ULTER N4 SD)測量前述矽氧粒子的平均粒徑。具體而言，量取矽氧 粒子的分散液，以進入動態光散射方式粒度分布計中必要 的散射光強度範®的方式，視需要财將分散液稀釋而調 13 201249975 HZZOipif ^品。接著，將該測量樣品放入動態光散射方式粒 散射光基準模式測量，藉此得到作為⑽的 矽氧拉子的平均粒徑（二次粒子徑）。 (第一酸解離常數為7以下的化合物） 本實施形態的CMP研磨液包括第一酸解 以下的化合物(但是嗤類除外卜所謂不符的 。坐類，意指環内具有含-個以上氮原子的多元素5員環的 化合物，例如可以列舉坐、3|1h i，从三哇 等的三。坐及其衍生物。 藉由使研磨液包括第一酸解離常數為7以下的化合 物’可以抑制CMP研磨液的ρΗ變超高且將其抑制在所希 望的pH (例如9.0〜12.0)，且可以增加作為半導體基板的 構成材料（矽等）的溶解劑而作用的鹼性化合物的含有量。 結果與不包括第一酸解離常數為7以下的化合物的研磨液 相較之下，可以大幅提高半導體基板的構成材料（矽等） 的研磨速度。該化合物的第一酸解離常數較佳的是5以 下，更佳的是4以下。 作為第一酸解離常數為7以下的化合物，從可以更增 加鹼性化合物的含有量的觀點來看，較佳的是包括選自胺 基酸以及具有羧基的有機酸（但是胺基酸除外）的至少一 種。此處「胺基酸」定義為具有胺基及羧基的兩官能基的 有機化合物。胺基酸中更佳的是α—胺基酸。 作為第一酸解離常數為7以下的胺基酸，例如可以列 舉甘胺酸（glycine)、組胺酸（histidine)(例如L_組胺 201249975 4223lpif 酸）、天冬胺酸（asPartic acid)、麵胺酸（glutamic acid)、 白胺酸（leucine )、絲胺酸（serine )、脯胺酸（proline ) 以及纈胺酸（valine)等’較佳的是選自甘胺酸及組胺酸的 至少一種。作為具有敌基且第一酸解離常數為7以下的有 機酸，例如可以列舉顏果酸（malic acid )、D比咬竣酸 (picolinic acid )、馬來酸（maleic acid )、丙二酸（malonic acid)、捧檬酸（citric acid)、葡萄糖酸（gluconic acid)、 乙醇酸（glycolic acid )、琥 J白酸（succinic acid )、乳酸（lactic acid)、己二酸（adipic acid)、戊二酸（glutaric acid)、 安息香酸（56!^0^^(^.(1)、苯二曱酸（？11仇31^^(^(1)、富 馬酸（fumaric acid )、草酸（oxalic acid )、酒石酸（tartaric acid)、於鹼酸（nicotinic acid)、杏仁酸（mandelic acid )、 醋酸、2-喧嚇曱酸（quinaldic acid )、酿酸（butyric acid )、 吉草酸（valeric acid )、柳酸（salicylic acid )、甘油酸（glyceric acid )及庚二酸（pimelic acid )等，其中較佳的是蘋果酸、 吡啶羧酸及馬來酸，更佳的是蘋果酸。第一酸解離常數為 7以下的化合物可以1種單獨使用，或者可以2種以上組 合使用。作為第一酸解離常數為7以下的化合物的組合， 例如可以使用甘胺酸及蘋果酸的組合。 從可以容易充分地得到研磨速度的提升效果的觀點來 看，第一酸解離常數為7以下的化合物的含有量在研磨液 全質量基準中較佳的是0.10質量％以上，更佳的是0.20質 量％以上，進一步更佳的是0.30質量％以上。在使用時以 水等的液狀媒介稀釋而使用的研磨液用貯藏液中，從容易 201249975. 抑制研磨粒難等缺點發生峨點來看，第—酸解離常數 為7以下的化合物的含有量在研磨液全質量基準 是3.〇β〇質量％以下，更佳的是1.00質量％以下，進一步更 佳的是0 · 7 0質量％以下。在使用多數個化合物作為第二酸 解離常數為7町的化合物的航下，較佳的是各化合物 的含有量的合計滿足上述範圍。 (驗性化合物） 、本實施形態的CMP研磨液包括作為半導體基板的構 成材料（料）的溶解劑而制的祕化合物，性化a 物較佳的是包括選自含驗性化合物及無機鹼性化合物二 至^種。作為含氮驗性化合物，並無制限制，但是較 佳的是選自氫氧化四㈣（tetmmethyIamm〇nium h—)及氫氧化銨（ammonium hydroxide)的至少一 種。作為無機鹼性化合物，可以列舉例如氫氧化鉀 (potassium hydroxide) ^ A( sodium hydroxide) » 較佳的是氫氧化鉀。 作為驗性化合物，從進—步提升導電構件的研磨速度 2點來看，健的是氫氧化銨。由於氫氧化鋪成導電 =的金料分（例如銅）及氨的錯合物且促進金屬成分 的各解，可以糊進-步提升導電構件的研磨速度。 鹼性化合物可以-種單獨使用，或者2種以上組合使 =。作為驗性化合物的組合’從能夠以更加優異的研磨速 半導縣板、輯層及導電構件顿財看，較佳 疋氫氧化卸及氫氧化銨的組合。 201249975 4223lpif 從容易得到實用的半導體基板的研磨速度的觀點來 看，鹼性化合物的含有量在研磨液全質量基準中較佳的是 0.10質量％以上’更佳的是0.20質量％以上，進一步更佳 的是0.30質量％以上。從可以容易抑制研磨粒中的矽氧粒 子的解聚合或陰離子強度的增加而產生的凝集等缺點發生 的觀點來看，鹼性化合物的含有量在研磨液全質量基準中 較佳的是5.00質量％以下，更佳的是3 〇〇質量％以下進 一步更佳的是1.00質量％以下。在使用多個化合物作為鹼 性化合物的情況下，較佳的是各化合物的含有量的合計滿 足上述範圍。 口 ' 從抑制導電構件過度溶解的觀點來看，與金屬成分（例 如銅）錯合的鹼性化合物（氫氧化銨等）的含有量較佳的 是0.50質量％以下。但是’藉由合併個與金屬成分錯合 的鹼性化合物以及與金屬成分難以錯合的鹼性化合物，即 便與金屬成分錯合的鹼性化合物的含有量超過〇 5〇質量 %，亦可抑制導電構件過度溶解且良好地研磨半 或絕緣層。 &amp; (氧化劑） 從高度維持半導體基板及絕緣層的研磨速度且提 電構件的研磨速度峨點來看，本實_態的⑽研磨 液的氧化齡括過硫_。作為過硫義，·可以列舉 過硫酸鉀、過硫酸錢及〇χ〇ΝΕ (註冊商標），較佳的 自硫酸銨的至少一種。在氧化劑為過硫酸鹽 (例如過氧化氫水溶液）以外的情況下，現階段原理尚不 17 2012499¾ 月月從子變黃或凝集沉降等的缺點。 氧化速度的觀_， 伽上，更佳的是〇/質量 上準=的是⑽質 質量％以上，難的是更佳的是0.1〇 枋曰〇/、，u 1 負篁/0以上，進一步特佳的是 0.25質1/。以上’極佳的是Q 3G質量％以上，進一步極佳 的是0.50質量％以上。從可以容易抑制研磨粒的凝集或導 電構件的腐鱗缺點發生的觀點來看，氧化劑的含有量在 研磨液全質量基準中較佳的是5.⑻質量％町，更佳的是 3.00質量％以下，進一步更佳的是1〇〇質量％以下。 (其他成分） 本實施形態的CMP研磨液，除了上述的成分以外， 在不損及上述研磨液的作用效果的範圍内，可以更加包括 如水、水以外的溶劑、水溶性高分子或防腐劑等一般添加 至研磨液的成分。 (pH) 從充分地提升半導體基板的構成材料（矽等）的研磨 速度的觀點來看，本實施形態的CMP研磨液的pH為9.0 以上，較佳的是9.5以上，更佳的是10·0以上。從隨著充 分地提升半導體基板的構成材料（矽等）的研磨速度而抑 制因研磨粒產生解聚合所導致的CMP研磨液的液狀安定 性降低（例如參照上述專利文獻2)的觀點來看，CMP研 磨液的pH為12.0以下’較佳的是11.5以下，更佳的是11.0 以下。CMP研磨液的pH例如可以藉由pKal為7以下的化 201249975 4223lpif 合物及鹼性化合物的CMP研磨液中的含有量來調整。 CMP研磨液的PH可以藉由pH計（例^，橫河電機 股份有限公司製造，Model pH81)來測量。在本實施形態 中’可以使用中性磷酸鹽PH緩衝液（ρϊϊ 6 86 及硼酸鹽ΡΗ標準液（ΡΗ 9.18 (25°C ))進行2點校正後， 將電極放入CMP研磨液，且採用經過2分以上而安定後 的值當作CMP研磨液（25°C )的pH。 (保存形態） 關於本實施形態的CMP研磨液，可以預先提高含有 成分的含有量’進而當作研磨液用貯藏液來保存。@在3此情 況下，使用CMP研磨液時，藉由水等稀釋研磨液用貯藏 液的CMP研磨液到本來的含有成分的含有量來使用即 可並且’關於本貫施形悲的CMP研磨液，可以將含有 成分分成些許液體的分液形態來保存，使用該些時再混合 使用。 &lt;半導體基板的研磨方法&gt; 本實施形態的CMP研磨液可以用於如下做法：同時 研磨在半導體基板的被研磨面露出的基板本體及絕緣層， 藉此使應該成為貫通電極的導電構件在被研磨面露出而形 成貫通電極構造’或者，研磨基板本體、絕緣層及露出第 1貫通電極的半導體基板的被研磨面，藉此使應該成為貫 通電極的導電構件在被研磨面露出而形成第2貝通電極， 並形成具有多個貫通電極的貫通電極構造。此外，關於本 實施形態的CMP研磨液，在磨削步驟中對具有應該成為 19 201249975 λ 土 °的導電構件的半導體基板的主面進行磨削 g 後，特別適用於研磨該主面的用途。 如下 .貫&amp;形.4的半導體基板的研磨方法的第1態樣包括 紅準備步驟：準備半導體基板，前述半導體基板包 其中一方 等電構件以及絕緣層。基板本體形成有僅在 二、主面上開口的中空部。導電構件配置於中空部 成為貫通電極。絕緣層至少配置於基板本體的另 一方的主面與中空部之間。The present invention provides a CMP polishing liquid capable of polishing a semiconductor substrate, an insulating layer and a conductive member at an excellent polishing rate, and a polishing method of a semiconductor substrate using the CMP 201249975 4223 lpif polishing liquid. According to the present invention as described above, the through electrode structure can be easily formed without additionally setting the step of exposing the conductive member to the step of exposing the conductive member. Further, according to the present invention, when a plurality of conductive members to be through electrodes are formed in a semiconductor substrate, even when the depths of the conductive members from the surface to be polished of the substrate are different from each other, a plurality of through electrodes can be easily formed. Through-electrode structure. [Embodiment] Hereinafter, a CMP polishing liquid according to an embodiment of the present invention and a polishing method of a semiconductor substrate using the CMP polishing liquid will be described in detail. &lt;CMP polishing liquid&gt; The CMP polishing liquid of the present embodiment includes abmsive grain (abrasive particles), a compound having a first acid dissociation constant (pKal) of 7 or less (except for azoles), and a basic compound. And Oxygen (abrasive particles) The CMP polishing liquid of the present embodiment includes at least cena particles (cerium oxide particles) and silica particles (cerium oxide particles) as abrasive grains. In the case of polishing a semiconductor substrate (for example, a tantalum substrate) and an exposed surface (for example, a tantalum oxide film) by using such a polishing liquid, it is conceivable to polish the semiconductor substrate mainly by the silicon oxide particles, mainly by oxygen. The particles are polished by the insulating layer, but when viewed as a whole, a good polishing rate can be obtained by the multiplication effect of the two. As the oxime particles, colloidal oxime particles are preferred. Further, other abrasive grains may be used in combination as needed. As the abrasive grains of 201249975 which can be used in combination, specifically, abrasive grains including inorganic materials such as alumina, titania or zirconia can be cited; organic materials such as organic polymers are included. Abrasive grains; composite abrasive grains including organic materials and inorganic materials, and the like. The average particle diameter (secondary particle diameter) of the xenon particles is preferably 5 观点 from the viewpoint that the dispersion stability in the polishing liquid is good and the number of occurrences of scratches due to CMp is small. More preferably, the thickness below 〇 nm is below nm. From the viewpoint of easily obtaining a practical polishing speed, the average particle size of the xenon particles is preferably 1 〇 nm or more, more preferably 5% or more, still more preferably 50 nm or more. From the viewpoint of easily increasing the polishing of the insulating layer (for example, the ruthenium oxide film), the content of the ruthenium oxide particles is _ mass on the whole mass basis of the polishing liquid, and more preferably G.G5. The mass % is more than ^1, and is more than 〇1% by mass, and particularly preferably 〇2G% by mass, from the viewpoint that it is possible to suppress aggregation of particles in the polishing liquid, the content of 钸詈f The amount is preferably 2.10% by mass or less in the total mass basis of the polishing liquid. More preferably, it is 0. 80. The dispersion stability in the polishing liquid is good and is caused by CMP ( From the viewpoint of the occurrence of a small number of scratches, the flat ηηΐΐΓ (secondary particle diameter) of the xenon particles is preferably 2 〇〇 nm or less, and more preferably 100 is under the stone. Particularly preferably, the colloidal oxygen having an average particle diameter of 200 nm or less is more preferably a colloidal oxide having an average particle diameter of 100 nm or less. From the viewpoint of easily obtaining a practical polishing rate, 12 201249975 4223 lpif, the average particle diameter of the oxygen-containing particles is preferably 5 nm or more, and nm or more is more preferably 9 nm or more.疋7, and 2, to substantially improve the polishing of the semi-conducting plate (for example, silk plate), and from the viewpoint, the content of the '11 oxygen particles is preferably 0.01% or more in the total mass of the polishing liquid. More preferably, the amount of GG5 f is 1 or more, and the step is better than G.1G mass% or more. The content of the dream oxygen particles is preferably 5.00 mass% or less, more preferably 5.00 mass% or less, more preferably in the total mass of the polishing liquid, from the viewpoint of suppressing the occurrence of scratches such as scratches and the effect of improving the polishing rate satisfying the content. Yes! 〇〇% by mass or less, and 0.5% by mass or less. / More preferably, the average particle diameter of the aforementioned xenon oxide particles can be measured by a laser diffraction type particle size distribution meter (e.g., LA-920 manufactured by a tunneling machine). Specifically, it can be measured in the following manner using Manufactured Field Manufacturing &amp; LA_92〇 (light source nitrogen-nitrogen laser and crane laser shot). First, (iv) the transmissive (H) becomes a 65% to 75% sulphur particle dispersion as a measurement sample when measured relative to the nitrogen 氖 氖 laser. Then, the measurement sample is placed at 1 LA-920' by measuring the relative refractive index to 丨(9) (the theoretical refractive index of yttrium oxide 2.128 / the refractive index of water, and the oxygen content as the arithmetic mean diameter can be obtained). The average particle diameter (secondary particle diameter) of the particles. Further, the average particle diameter of the above-mentioned xenon particles can be measured by a dynamic light scattering type particle size distribution meter (for example, manufactured by COULTER Electronics Co., Ltd., trade name c〇ULTER N4 SD). In other words, the dispersion of the cerium-oxygen particles is measured in such a manner as to enter the intensity of the scattered light intensity in the dynamic light scattering type particle size distribution meter, and the dispersion is diluted as needed to adjust the amount of the 201249975 HZZOipif product. The measurement sample is placed in a dynamic light scattering mode particle scattering light reference mode measurement, whereby an average particle diameter (secondary particle diameter) of the oxygen oxide puller (10) is obtained. (Compound having a first acid dissociation constant of 7 or less) The CMP polishing liquid of the embodiment includes the following compounds of the first acid hydrolysis (except for the steroids, which are not compatible with each other. The sitting type means a multi-element 5 member having more than one nitrogen atom in the ring. Examples of the compound include, for example, sitting, 3|1h i, from Sanwa, etc., and its derivatives. By allowing the polishing liquid to include a compound having a first acid dissociation constant of 7 or less, ρ CMP of the CMP slurry can be suppressed. It is super high and is suppressed to a desired pH (for example, 9.0 to 12.0), and the content of the basic compound which acts as a solvent for the constituent material of the semiconductor substrate (矽, etc.) can be increased. The polishing liquid of a compound having an acid dissociation constant of 7 or less can greatly increase the polishing rate of a constituent material (such as ruthenium) of a semiconductor substrate. The first acid dissociation constant of the compound is preferably 5 or less, more preferably The compound having a first acid dissociation constant of 7 or less is preferably an organic acid selected from the group consisting of an amino acid and a carboxyl group from the viewpoint of further increasing the content of the basic compound (but At least one of the amino acids except "amino acid" is defined as a difunctional organic compound having an amine group and a carboxyl group. More preferably, the amino acid is an a-amino acid. The amino acid having a dissociation constant of 7 or less may, for example, be a glycine, a histidine (for example, L_histamine 201249975 4223 lpif acid), aspartic acid (aspartic acid), or a face acid ( The glutamic acid), leucine, serine, proline, and valine are preferably selected from at least one of glycine and histidine. Examples of the organic acid having an enemy group and having a first acid dissociation constant of 7 or less include, for example, malic acid, D-picolinic acid, maleic acid, and malonic acid (for example). Malonic acid), citric acid, gluconic acid, glycolic acid, succinic acid, lactic acid, adipic acid, pentane Glutaric acid, benzoic acid (56!^0^^(^.(1), benzoic acid (? 11 Qiu 31^^(^(1), fumaric acid, oxalic acid, tartaric acid, nicotinic acid, mandelic acid, acetic acid, 2- Quenching quinaldic acid, butyric acid, valeric acid, salicylic acid, glyceric acid, and pimelic acid, among which preferred It is malic acid, pyridine carboxylic acid, and maleic acid, and more preferably malic acid. The compound having a first acid dissociation constant of 7 or less may be used alone or in combination of two or more. The first acid dissociation constant is For the combination of the following compounds, for example, a combination of glycine and malic acid can be used. From the viewpoint of easily obtaining the effect of improving the polishing rate, the content of the compound having a first acid dissociation constant of 7 or less is The liquid total mass standard is preferably 0.10% by mass or more, more preferably 0.20% by mass or more, still more preferably 0.30% by mass or more. The polishing liquid used for dilution with a liquid medium such as water is used. Storage In the case of the liquid, the content of the compound having a first acid dissociation constant of 7 or less is 3. 〇β〇 mass% or less, more preferably, from the point of the difficulty of suppressing the abrasive grains, etc., in the case of the easy-to-use 201249975. It is preferably 1.00% by mass or less, and still more preferably 0.70% by mass or less. In the case of using a plurality of compounds as a compound having a second acid dissociation constant of 7 cho, it is preferred that the content of each compound is contained. The CMP polishing liquid of the present embodiment includes a viscous compound which is a solvent of a constituent material (material) of a semiconductor substrate, and the a substance preferably includes one selected from the group consisting of The test compound and the inorganic basic compound are not limited, but are preferably selected from the group consisting of tetmmethyIamm〇nium h- and ammonium hydroxide. At least one of the inorganic basic compounds may, for example, be potassium hydroxide (sodium hydroxide), preferably potassium hydroxide. Further improvement of the polishing rate of the conductive member at 2 o'clock, the health is ammonium hydroxide. Since the hydroxide is deposited as a conductive metal fraction (such as copper) and a complex of ammonia and promotes the solution of the metal component, The polishing rate of the conductive member can be increased in a stepwise manner. The basic compound can be used alone or in combination of two or more. As a combination of the test compound, it is preferable to use a combination of hydrazine hydroxide and ammonium hydroxide from a more excellent polishing rate of the semi-conducting plate, the layer, and the conductive member. 201249975 4223lpif From the viewpoint of the polishing rate of the semiconductor substrate which is easy to obtain, the content of the basic compound is preferably 0.10% by mass or more based on the total mass of the polishing liquid, more preferably 0.20% by mass or more, and furthermore. Preferably, it is 0.30% by mass or more. The content of the basic compound is preferably 5.00 by mass in the total mass basis of the polishing liquid from the viewpoint that it is possible to easily suppress the occurrence of defects such as agglomeration of the deuterium oxide particles in the abrasive grains or an increase in the anion strength. % or less, more preferably 3 〇〇 mass% or less, further more preferably 1.00 mass% or less. In the case where a plurality of compounds are used as the basic compound, it is preferred that the total content of each compound is in the above range. The content of the basic compound (ammonium hydroxide or the like) which is in contact with the metal component (e.g., copper) is preferably 0.50% by mass or less from the viewpoint of suppressing excessive dissolution of the conductive member. However, by combining a basic compound which is in contact with a metal component and a basic compound which is difficult to be mixed with a metal component, even if the content of the basic compound which is in contact with the metal component exceeds 〇5〇 mass%, it can be suppressed. The conductive member is excessively dissolved and the semi- or insulating layer is well ground. &amp; (Oxidant) From the viewpoint of maintaining the polishing rate of the semiconductor substrate and the insulating layer at a high height and the polishing rate of the piezoelectric member, the oxidation age of the (10) polishing liquid in the actual state is over sulfur. As the persulfate, potassium persulfate, peroxydisulfate and hydrazine (registered trademark) may be mentioned, and at least one of ammonium sulfate is preferred. In the case where the oxidant is other than a persulfate (for example, an aqueous solution of hydrogen peroxide), the current principle is not yet a disadvantage of the yellowing or agglomeration of the particles from 2012 to 4,499,499. The oxidation rate is _, gamma, and more preferably 〇/mass is higher than (10) mass% or more, and it is more difficult to be 0.1 〇枋曰〇/, u 1 minus 篁 /0 or more, Further particularly good is 0.25 quality 1/. The above is excellent in Q 3G mass% or more, and further preferably 0.50 mass% or more. The content of the oxidizing agent is preferably 5. (8)% by mass, more preferably 3.00% by mass in terms of the total mass basis of the polishing liquid, from the viewpoint that it is possible to easily suppress the aggregation of the abrasive grains or the occurrence of defects in the rust scale of the conductive member. Hereinafter, it is more preferably 1% by mass or less. (Other components) The CMP polishing liquid of the present embodiment may further include a solvent other than water, water, a water-soluble polymer, a preservative, etc., in addition to the above-described components, insofar as the effect of the polishing liquid is not impaired. Generally added to the ingredients of the slurry. (pH) The pH of the CMP polishing liquid of the present embodiment is 9.0 or more, preferably 9.5 or more, and more preferably 10, from the viewpoint of sufficiently increasing the polishing rate of the constituent material (such as ruthenium) of the semiconductor substrate. 0 or more. From the viewpoint of suppressing the decrease in the liquid stability of the CMP polishing liquid due to the depolymerization of the abrasive grains, the polishing rate of the constituent material (such as ruthenium or the like) of the semiconductor substrate is suppressed (see, for example, Patent Document 2) The pH of the CMP polishing liquid is 12.0 or less. Preferably, it is 11.5 or less, and more preferably 11.0 or less. The pH of the CMP polishing liquid can be adjusted, for example, by the content of the 201249975 4223 lpif compound having a pKal of 7 or less and the CMP polishing liquid of the basic compound. The pH of the CMP slurry can be measured by a pH meter (manufactured by Yokogawa Electric Co., Ltd., Model pH 81). In the present embodiment, 'the neutral phosphate pH buffer (ρϊϊ 6 86 and the borate ΡΗ standard solution (ΡΗ 9.18 (25 ° C)) can be used for two-point calibration, and then the electrode is placed in the CMP slurry and used. The value of the CMP polishing liquid (25°C) is determined by the value of the CMP polishing liquid (25°C). The CMP polishing liquid of the present embodiment can be used as a polishing liquid in advance. In the case where the CMP polishing liquid is used, the CMP polishing liquid for the polishing liquid storage solution can be used by water or the like to the content of the original contained component, and the present invention can be used. The CMP slurry having a sorrowful shape can be stored in a liquid separation form in which the components are divided into a plurality of liquids, and can be used in combination when used. <The method for polishing a semiconductor substrate> The CMP polishing liquid of the present embodiment can be used in the following manner. At the same time, the substrate body and the insulating layer exposed on the surface to be polished of the semiconductor substrate are polished, whereby the conductive member to be the through electrode is exposed on the surface to be polished to form a through electrode structure. The substrate body, the insulating layer, and the surface to be polished of the semiconductor substrate on which the first through electrode is exposed, whereby the conductive member to be the through electrode is exposed on the surface to be polished to form the second pass-through electrode, and a plurality of through electrodes are formed. Further, the CMP polishing liquid of the present embodiment is particularly suitable for polishing the main surface of the semiconductor substrate having the conductive member which should be 19 201249975 λ soil in the grinding step after the grinding process is performed. The first aspect of the method for polishing a semiconductor substrate according to the following description includes a red preparation step of preparing a semiconductor substrate, wherein the semiconductor substrate includes one of the isoelectric members and the insulating layer. In the hollow portion that is open on the main surface, the conductive member is disposed in the hollow portion to be a through electrode, and the insulating layer is disposed at least between the other main surface of the substrate body and the hollow portion.

Ml (2)磨削步驟（薄層化步驟）：準備步驟後，以導電 不露出的方式從前述另一方的主面側磨削基板本體， 藉此對基板本體進行薄化。 (3)研磨步驟·，磨削步驟後，使用前述CMP研磨液 從則述另一方的主面側對基板本體及絕緣層進行研磨，使 導電構件在前述另—方的主面侧露出而形成貫通電極構 造。在研磨方法的第丨態樣的研磨步驟中，研磨除去在前 述另一方的主面側披覆導電構件的絕緣層及基板本體的表 層部，使導電構件在前述另一方的主面側露出而形成貫通 電極。 準備步驟中，例如，首先準備具有互相對向的表面（其 中一方的主面，第1主面）la及背面（另一方的主面，第 2主面）lb的矽基板等的基板本體1 ’其後在表面la上形 成元件2 (參照圖1中的（a))。接著，在基板本體i的 表面la藉由電漿钮刻法（plasma etching)等方法形成用 201249975 4223 lpif 以配置TSV(貫通電極）的多個中空部3a及中空部3b(來 照圖1中的（b))。例如，中空部3a及中空部3b的深度 互相不同，與中空部3a的底面相較下，中空部3b的底面 位於離背面lb較深的位置。繼之’在表面la上以順從中 空部3a及中空部3b形狀的方式形成用以絕緣TSV的絕緣 層（例如珍乳化膜或砍氣化膜）5 ’措此得到半導體基板 100 (參照圖1中的（C))。 接著，以填充中空部3a及中空部3b並覆蓋絕緣層5 的全面的方式，在絕緣層5上藉由藏鍍（sputtering)咬電 解電鍍（electrolytic plating)等方法積層導電構件（例如 銅層）7 (參照圖2中的（a))。繼之，從表面la側研磨 導電構件7及絕緣層5直到元件2露出，藉此得到半導體 基板200 (參照圖2中的（b))。 磨削步驟中，藉由研磨機從背面lb侧磨削基板本體！ 直到配置於中空部3a底面的絕緣層5a即將露出的程度， 藉此將基板本體1薄層化而得半導體基板300 (參照圖3 中的（a) ) ° 研磨步驟中，使用前述CMP研磨液從背面lb側研磨 基板本體1，藉以消除磨削步驟中研磨機在背面lb造成的 磨削傷並且形成多個TSV。例如，研磨步驟包括如下：第 1研磨步驟’在基板本體1的背面lb使中空部3a内的導 電構件7露出’藉此形成TSV 7a ;第2研磨步驟，在基板 本體1的背面lb使中空部3b内的導電構件7露出，藉此 形成TSV 7b。此外，第1研磨步驟及第2研磨步驟玎當作 21 201249975r 單一步驟連續進行，亦可當作不同步驟分別進行。 第1研磨步驟中身為研磨對象的半導體基板30〇為用 以形成TSV構造（貫通電極構造）的半導體基板，包括形 成有僅在表面la上開口的中空部3&amp;與中空部3b的基板本 體1、配置於中空部3a及中空部31)内且應該成為TSV 7a 與TSV 7b的導電構件7以及沿著中空部3a與中空部3b 的内壁而配置在基板本體1與導電構件7之間的絕緣層5a 與絕緣層5b。導電構件7的背面lb側的端部被絕緣層5a、 絕緣層5b及基板本體1的背面lb側的表層部所彼覆，且 導電構件7的表面la侧的端部在表面la露出。從背面lb 側研磨基板本體1 ’而在背面lb露出導電構件7，導電構 件7藉此成為TSV。 第1研磨步驟中，伴隨著研磨的進行而除去基板本體 1的背面lb侧的表層部’而在背面lb露出絕緣層5a。然 後’伴隨著更進一步地進行研磨而除去在背面露出的絕 緣層5a，而在背面lb露出導電構件7,藉此在基板本體i 形成貫通孔13a (參照圖3中的（b))。藉此可得到包括 TSV 7a的半導體基板4〇0 (前述TSV 7a從表面la到背面 lb在厚度方向上貫通基板本體1)。 第2研磨步驟中身為研磨對象的半導體基板4〇〇為$ 以進一步形成TSV 7b的半導體基板，包括形成有僅在表 面la上開口的中空部3b的基板本體1、配置於中空部％ 内且應該成為TSV的導電構件7以及沿著中空部3b的内 壁而配置在基板本體1與導電構件7之間的絕緣層％。 22 201249975 4223 lpif 第2研磨步驟中’伴隨著研磨的進行而除去基板本體 1的背面lb側的表層部’而在背面ib露出絕緣層5b。該 第2研磨步驟中，在背面lb露出的貫通孔13a内的絕緣層 5a及TSV 7a亦與基板本體1的背面lb側的表層部一起被 除去。然後，伴隨著更進一步地進行研磨而除去在背面lb 露出的絕緣層5b’而在背面lb露出導電構件7,藉此在基 板本體1形成貫通孔13b (參照圖3中的（c))。藉此可 得到包括多個TSV 7a及TSV 7b的半導體基板500 (前述 TSV7a及TSV7b從表面1&amp;到背面lb在厚度方向上貫通 基板本體1而將表面la與背面lb電氣連接）。 本實施形態的半導體基板的研磨方法的第2態樣包括 如下： (1) 準備步驟：準備半導體基板’與前述研磨方法的 第1態樣的準備步驟相同。 (2) 磨削步驟··準備步驟後，以露出導電構件的方式 從另一方的主面側磨削基板本體，藉此得到包括形成 有從前述其巾—方的主面貫通至前述另—方的主面的貫通 孔的基板本體及配置於貫通孔内的貫通電極的半導體基 板0 &quot;义、⑴研磨步驟：磨削步驟後，使用前述CMp研磨液 從前述其中-方的主面侧或前述另—方的主_對基板本 體、絕緣層及貫通電極進行研磨。在研財法的第2態樣 的磨削步驟中，在前述另—方主面側使導電構件露出^形 成貫通電極；而在研磨步驟巾，對在前述另—方的主面露 23 201249975 ipif 出的半導體基板、絕緣層及貫通電極進行研磨，藉此消除 磨削步驟中在前述另一方主面發生的磨削傷。 示 半導體基板的研磨方法的第2態樣的準備步驟中，與 第1遙樣同樣地準備半導體基板1 〇〇。接著，磨削步驟中/ ' 藉由研磨機從背面lb侧磨削基板本體1直到中空部3&amp;及 中空部3b内的導電構件7露出，而對基板本體i進行^層 化，藉此得到與半導體基板500 (參照圖3中的（c) ; ^ 樣地包括TSV 7a與TSV 7b的半導體基板。所得的半導體 基板為第2態樣中研磨步驟的研磨對象，且包括形成貫通 孔13a與貫通孔13b (前述貫通孔13a與貫通孔i3b從表 面la貫通至背面lb)的基板本體1以及配置於貫通孔 與貫通孔13b内的TSV 7a與TSV 7b。 研磨步驟中，與第1態樣的研磨步驟同樣地使用前述 CMP研磨液，從背面lb側對基板本體1進行研磨。藉此 可以消除磨削步驟中在背面lb發生的磨削傷。 本貫施形態的半導體基板的研磨方法的研磨步驟中， 較佳的是藉由一邊在研磨定盤的研磨布上供給CMp研磨 液，一邊將基板本體1的背面lb壓附在研磨布的狀態，使 研磨定盤及基板本體1相對地移動，從背面lb侧對基板本 體1進行研磨。在使用如此的研磨方法的情況下，可以顯 著提升前述CMP研磨液的研磨特性。 作為研磨步驟中所使用的研磨裝置，可以使用包括研 磨定盤及托座（holder)的一般研磨裝置：前述研磨定盤 連接可以變更旋轉數的馬達且可以貼付研磨布，前述托座 24 201249975 4223lpif 可以保持被研磨的基板。研料並無制關，可以使用 -般的不織布、發泡聚胺甲酸§旨（pGlyu她)及多 氟樹脂等。 研磨定盤的旋轉速度較佳的是以基板不飛出的方式進 行200 rpm ( 200 min])卩下的低旋轉。往基板的研磨布的 壓附壓力（研磨壓力）較佳的是7〇 hPa〜35〇 hpa ( 7 kpa〜35 kPa)。研磨期間較佳的是以幫浦等連續地供給研磨液到研 磨布。該供給量並無特別限制，但是較佳的是經常以研磨 液覆滿研磨布的表面。 研磨步驟亦可包括粗研磨步驟及精密研磨步驟。前述 粗研磨步驟在背面lb從背面lb側對有磨削傷的粗晶圓 (wafer)的基板本體1進行粗研磨。前述精密研磨步驟在 粗研磨步驟後，從背面lb側對基板本體1進行精密研磨。 例如’前述研磨方法的第1態樣中，可以將前述第1研磨 步驟當作粗研磨步驟進行後，將前述第2研磨步驟當作精 密研磨步驟進行。 前述精密研磨步驟中，較佳的是使用具有規定的蕭民 D硬度的研磨布，從背面lb侧對基板本體1進行研磨。研 磨布的蕭氏D硬度的下限較佳的是30以上，更佳的是4〇 以上。若蕭氏D硬度為30以上，則可以充分地抑制如下 狀態：研磨時研磨布過多地進入TSV部分，導致TSV成 為自被研磨面大大地凹陷的狀態（所謂碟型凹陷（dishing) 大的狀態）。藉此可以將上下積層的LSI晶片進一步良好 地連接。此外，研磨布的蕭氏D硬度的上限較佳的是9〇 25 201249975 HZ-Z-J ipif 以下，更佳的是80以下。若蕭氏D硬度為90以下，則可 以抑制因研磨造成的傷等的缺陷。 蕭氏D硬度為測量硬質橡膠等的硬度時經常使用的硬 度，且為對應JISK 6253的基準。蕭氏D硬度為使用蕭氏 D硬度計測量的值，蕭氏D硬度的測量中，例如可以使用Ml (2) Grinding step (thinning step): After the preparation step, the substrate body is ground from the other main surface side so that the conductive is not exposed, whereby the substrate body is thinned. (3) Polishing step: After the grinding step, the substrate body and the insulating layer are polished from the other main surface side by using the CMP polishing liquid, and the conductive member is exposed on the other main surface side. Through electrode structure. In the polishing step of the polishing method, the insulating layer covering the conductive member and the surface layer portion of the substrate body are covered by the other main surface side, and the conductive member is exposed on the other main surface side. A through electrode is formed. In the preparation step, for example, first, a substrate body 1 having a ruthenium substrate having a surface (one main surface, first main surface) la and a back surface (the other main surface, the second main surface) lb facing each other is prepared. Then, the element 2 is formed on the surface la (refer to (a) in Fig. 1). Next, on the surface 1a of the substrate body i, a plurality of hollow portions 3a and hollow portions 3b for arranging TSVs (through electrodes) are formed by a method such as plasma etching (201249975 4223 lpif) (see FIG. (b)). For example, the depths of the hollow portion 3a and the hollow portion 3b are different from each other, and the bottom surface of the hollow portion 3b is located deeper from the back surface lb than the bottom surface of the hollow portion 3a. Then, an insulating layer (for example, an emulsified film or a chopped gas film) for insulating the TSV is formed on the surface 1a so as to conform to the shape of the hollow portion 3a and the hollow portion 3b. The semiconductor substrate 100 is obtained by referring to FIG. (C)). Next, a conductive member (for example, a copper layer) is laminated on the insulating layer 5 by means of sputtering, electrolytic plating, or the like, by filling the hollow portion 3a and the hollow portion 3b and covering the insulating layer 5 in a comprehensive manner. 7 (Refer to (a) in Fig. 2). Then, the conductive member 7 and the insulating layer 5 are polished from the surface la side until the element 2 is exposed, whereby the semiconductor substrate 200 is obtained (see (b) in Fig. 2). In the grinding step, the substrate body is ground from the back side lb side by a grinder! The semiconductor substrate 300 is obtained by thinning the substrate body 1 to the extent that the insulating layer 5a disposed on the bottom surface of the hollow portion 3a is exposed (see (a) in FIG. 3). In the polishing step, the CMP polishing liquid is used. The substrate body 1 is ground from the back side lb side, thereby eliminating the grinding damage caused by the grinder on the back side lb in the grinding step and forming a plurality of TSVs. For example, the polishing step includes the following steps: a first polishing step 'exposing the conductive member 7 in the hollow portion 3a on the back surface 1b of the substrate body 1' to form the TSV 7a; and a second polishing step to hollow the rear surface 1b of the substrate body 1 The conductive member 7 in the portion 3b is exposed, whereby the TSV 7b is formed. Further, the first polishing step and the second polishing step are carried out continuously as a single step of 21 201249975r, and may be carried out separately as different steps. The semiconductor substrate 30 to be polished in the first polishing step is a semiconductor substrate for forming a TSV structure (through electrode structure), and includes a substrate body 1 in which a hollow portion 3 & and a hollow portion 3b which are opened only on the surface 1a are formed. The conductive member 7 disposed in the hollow portion 3a and the hollow portion 31) and serving as the TSV 7a and the TSV 7b and the insulation disposed between the substrate body 1 and the conductive member 7 along the inner walls of the hollow portion 3a and the hollow portion 3b Layer 5a and insulating layer 5b. The end portion on the back surface 1b side of the conductive member 7 is covered by the insulating layer 5a, the insulating layer 5b, and the surface layer portion on the back surface 1b side of the substrate body 1, and the end portion on the surface la side of the conductive member 7 is exposed on the surface 1a. The substrate body 1' is polished from the back side lb side and the conductive member 7 is exposed on the back side 1b, whereby the conductive member 7 becomes a TSV. In the first polishing step, the surface layer portion ' on the back surface 1b side of the substrate body 1 is removed as the polishing progresses, and the insulating layer 5a is exposed on the back surface 1b. Then, the insulating layer 7a exposed on the back surface is removed by further polishing, and the conductive member 7 is exposed on the back surface 1b, whereby the through hole 13a is formed in the substrate main body i (see (b) in Fig. 3). Thereby, the semiconductor substrate 4?0 including the TSV 7a (the TSV 7a penetrates the substrate body 1 in the thickness direction from the surface la to the back surface lb) can be obtained. In the second polishing step, the semiconductor substrate 4 to be polished is a semiconductor substrate on which the TSV 7b is further formed, and the substrate body 1 including the hollow portion 3b opened only on the surface 1a is disposed in the hollow portion It should be the conductive member 7 of the TSV and the insulating layer % disposed between the substrate body 1 and the conductive member 7 along the inner wall of the hollow portion 3b. 22 201249975 4223 lpif In the second polishing step, the surface layer portion on the back surface 1b side of the substrate body 1 is removed as the polishing progresses, and the insulating layer 5b is exposed on the back surface ib. In the second polishing step, the insulating layers 5a and TSV 7a in the through holes 13a exposed on the back surface 1b are also removed together with the surface layer portion on the back surface 1b side of the substrate body 1. Then, the insulating layer 5b' exposed on the back surface 1b is removed and the conductive member 7 is exposed on the back surface 1b, whereby the through hole 13b is formed in the substrate main body 1 (see (c) in Fig. 3). Thereby, the semiconductor substrate 500 including the plurality of TSVs 7a and TSVs 7b is obtained (the TSVs 7a and TSV7b are electrically connected to the substrate body 1 from the surface 1&amp; to the back surface 1b in the thickness direction, and the surface 1a and the back surface 1b are electrically connected). The second aspect of the method for polishing a semiconductor substrate of the present embodiment includes the following: (1) Preparation step: The preparation of the semiconductor substrate ' is the same as the preparation step of the first aspect of the polishing method. (2) After the grinding step and the preparation step, the substrate body is ground from the other main surface side so as to expose the conductive member, thereby obtaining the formation from the main surface of the towel to the other side. The substrate body of the through-hole of the main surface of the square and the semiconductor substrate of the through-electrode disposed in the through-hole 0 &quot; (1) polishing step: after the grinding step, the CMp polishing liquid is used from the main surface side of the square Or the other main _ pair of the substrate body, the insulating layer and the through electrode are polished. In the grinding step of the second aspect of the research method, the conductive member is exposed on the side of the other main surface to form a through electrode; and in the polishing step, the main surface of the other side is exposed 23 201249975 The semiconductor substrate, the insulating layer, and the through electrode of the ipif are polished, thereby eliminating the grinding damage occurring on the other main surface in the grinding step. In the preparation step of the second aspect of the method of polishing the semiconductor substrate, the semiconductor substrate 1 is prepared in the same manner as the first remote sample. Next, in the grinding step, 'the substrate body 1 is ground from the back surface 1b by the grinder until the conductive members 7 in the hollow portion 3 &amp; and the hollow portion 3b are exposed, and the substrate body i is layered, thereby obtaining Referring to the semiconductor substrate 500 (see (c) of FIG. 3, the semiconductor substrate including the TSV 7a and the TSV 7b is used. The obtained semiconductor substrate is the object of polishing in the polishing step in the second aspect, and includes the formation of the through hole 13a and The substrate body 1 having the through holes 13b (the through holes 13a and the through holes i3b penetrating from the front surface 1a to the back surface 1b) and the TSVs 7a and TSVs 7b disposed in the through holes and the through holes 13b. In the polishing step, the first aspect In the polishing step, the substrate body 1 is polished from the back surface 1b by using the CMP polishing liquid in the same manner. This eliminates the abrasion of the back surface 1b in the grinding step. In the polishing step, it is preferable that the back surface 1b of the substrate main body 1 is pressed against the polishing cloth while the CMp polishing liquid is supplied onto the polishing cloth of the polishing plate, so that the polishing platen and the substrate body 1 are opposed to each other. mobile, The substrate body 1 is polished on the back side lb side. In the case of using such a polishing method, the polishing characteristics of the CMP polishing liquid can be remarkably improved. As the polishing apparatus used in the polishing step, a polishing plate and a holder can be used. (holder) general polishing device: the polishing plate is connected to a motor that can change the number of rotations and can be attached to the polishing cloth, and the holder 24 201249975 4223lpif can hold the substrate to be polished. The material is not controlled, and the like can be used. Non-woven fabric, foamed polyurethane § (pGlyu her), polyfluororesin, etc. The rotation speed of the polishing plate is preferably a low rotation of 200 rpm (200 min) under the condition that the substrate does not fly out. The pressing pressure (grinding pressure) of the polishing cloth to the substrate is preferably 7 〇 hPa to 35 〇 hpa (7 kPa to 35 kPa). During the polishing, it is preferred to continuously supply the polishing liquid to the polishing cloth by a pump or the like. The amount of supply is not particularly limited, but it is preferred that the surface of the polishing cloth is often covered with a polishing liquid. The polishing step may also include a coarse grinding step and a precision grinding step. The grinding step is performed on the back surface 1b from the back surface 1b side to roughen the substrate body 1 having a rough wafer. The precision polishing step is performed after the rough polishing step, and the substrate body 1 is precisely ground from the back surface 1b side. For example, in the first aspect of the polishing method, the first polishing step may be performed as a rough polishing step, and the second polishing step may be performed as a precision polishing step. The substrate body 1 is polished from the back surface 1b by using a polishing cloth having a predetermined Xiaomin D hardness. The lower limit of the Shore D hardness of the polishing cloth is preferably 30 or more, and more preferably 4 inches or more. When the Shore D hardness is 30 or more, it is possible to sufficiently suppress the state in which the polishing cloth excessively enters the TSV portion during polishing, and the TSV is in a state of being largely recessed from the surface to be polished (so-called dishing large dishing) ). Thereby, the LSI wafers stacked one on another can be further connected well. Further, the upper limit of the Shore D hardness of the polishing cloth is preferably 9 〇 25 201249975 HZ-Z-J ipif or less, more preferably 80 or less. When the Shore D hardness is 90 or less, defects such as scratches due to polishing can be suppressed. The Shore D hardness is a hardness which is often used when measuring the hardness of a hard rubber or the like, and is a standard corresponding to JIS K 6253. The Shore D hardness is a value measured using a Shore D hardness meter. For the measurement of the Shore D hardness, for example, it can be used.

KOBUNSHIKEIKICO.，LTD.製造「ASKER 橡膠硬度計 D 型」。蕭氏D硬度的測量值中產生一般的η程度的測量誤 差’因此同一個測量進行5次後取平均值。此外，蕭氏d 硬度的上限從其定義而成為100。 本發明的半導體基板的研磨方法並不限定於上述的實 施形態，可以有各式各樣的變形態樣。例如，上述的實施 形態中，使用半導體基板100進行磨削步驟及研磨步驟， 但是亦可使用圖4中的（a)所示的半導體基板l〇〇a代替 半導體基板100。半導體基板100a中，與半導體基板1〇〇 同樣地形成元件2以及中空部3a與中空部3b，將用以對 TSV絕緣的絕緣層（例如矽氧化膜或矽氮化膜）15以順從 中空部3a及中空部3b形狀的方式形成在表面la上，藉此 在絕緣層15上以順從絕緣層15形狀的方式形成阻障金屬 (barrier metal)層（例如组（tantalum)層、氮化组層、 鈦（titanium)層、氮化欽層、鎢（tungsten)層、氮化鎢 層）25 〇 即便在使用如此的半導體基板l〇〇a的情況下，從背面 lb侧對半導體基板100a中的基板本體1進行磨削及研磨 後，除去基板本體1的背面lb侧的表層部、絕緣層15及 26 201249975 4223 lpif 阻障金屬層25 ’藉此可得到在背面lb側露出TSv7a&amp; TSV7b的半導體基板500a (參照圖4中的（b))。半導 體基板500a中，由於在TSV 7a、TSV 7b及絕緣層15之 間配置有阻障金屬層25，因此可以抑制TSV 7a及TSV 7b 的構成成分的Cu等往基板本體1擴散，並可以提升TSV 7a、TSV 7b與絕緣層15的密著性。 此外，上述的研磨方法的第1態樣的磨削步驟中，藉 由研磨機從背面lb侧磨削基板本體1直到絕緣層5即將露 出的程度，但是亦可藉由研磨機從背面丨b側磨削基板本體 1直到導電構件7即將露出的程度，而對基板本體1進行 ί專層化。在a亥情況下’在接續磨削步驟的研磨步驟中，從 背面lb侧研磨基板本體1而除去絕緣層5a，並使導電構 件7在背面lb露出，藉此可以得到TSV 7a。 此外，上述的研磨方法的第2態樣的磨削步驟中，從 背面lb侧磨削基板本體1直到中空部3a及中空部3b内的 導電構件7露出，但是亦可從背面lb側磨削基板本體i 直到中空部3a内的導電構件7露出後而中空部3b内的導 電構件7即將露出的程度。 並且’上述的實施形態中多個中空部的深度互相不 同，但是亦可多個中空部的深度皆為相同。此外，上述的 實施形態中形成包括多個TSV的TSV構造，但是亦可形 成包括單一 TSV的TSV構造。 [實例] 以下將藉由實例對本發明進一步地詳細說明，但是本 27 201249975 發明並不限定於該些實例。 [CMP研磨液的調配] 實施例1〜實施例10以及比較例丨〜比較例7的各匸· 研磨液中的各成分的含有量以成為表丨〜表3所示的量的方 式調整，並依以下順序調配。此外，鹼性化合物中的氫氧 化鉀及氫氧化氨為使用水溶液，並以成為研磨液令的規定 量的方式考慮了水溶液的濃度而添加。此外，研磨粒中的 石夕氧粒子（膠财餘子）及純粒子為使用水分散體， 並以成J研磨液中的規定量的方式考慮了水分散體的研磨 粒含有量而添加。進而，氧化劑中的過硫酸鹽為製作ι〇 質量％的水溶液，並以成為研磨液中的規定量的方 了水溶液的濃度而添加。 (實施例1〜實施例1〇) 在相當於研磨液全體的5G質量％的純水裡使表 2中的化合物A(第一酸解離常數為7以下 解後，添加規定量的鹼性化合物。 接著將石夕氧粒子（二次粒徑約25⑽的膠體石夕氧相 ::以::^口成為表“戈表以斤示的值的方式添加‘ 進而’將鈽氧粒子（鈽氧研磨粒分散液、二次粒徑：35(w 曰立化成工業股份有限公司製作、 8:9)二=:含有量成為表1或表2所示的二 加。充刀_拌混合物後，添加表i或表2中的氧化劑（这 )的10質量%水溶液並充分地_ 物。添加純水作為殘餘部分，調整至合計刚質量％。 28 201249975 4223lpif (比較例1 ) 在相當於研磨液全體的50質量％的純水裡 化合物A (甘胺酸及蘋果酸）溶解後，添加氫氧^的 充分地擾拌混合物後，將石夕氧粒子（二次粒徑約 的膠體视粒子）以研練含有量成絲3咐 二 式添加。進而，將錦氧粒子（錦氧研餘分散液、 徑：350 mn、日立化成工業股份有限公司製作商品名. GPX系列、pH 8〜9)以研練含有量絲表3所示的值的 方式添加。添加純水作為殘餘部分，調整至合 ， %。 負| (比較例2) 在相當於研磨液全體的50質量％的純水裡使表 化合物A(甘胺酸及蘋果酸）溶解後，添加氫氧化、 進而，將石夕氧粒子（二次粒徑約25咖的膠體石夕氣教 子）以研練含有量成為表3_的值㈣式添加 地f半混合物後，添加表3中的氧化劑（過硫酸銨）的；; 質董％水隸’充分賴拌混合物。添加純 分，調整至合計100質量％。 (比較例3) 在相當於研磨液全體的50質量％的純水裡使頻果酸 溶解後，添加氫氧化鉀。 充分地授拌混合物後，將石夕氧粒子（二次粒徑約^咖 的膠體魏粒子）以研錄含有量成為表3所示的值的方 式添加。進而，將聽粒子（魏研餘分散液、二 29 201249975 丨士 徑：350 nm、日立化成工業股份 ' GPX系列、pH8~9)以研磨粒含二2乍所商=: :式添加。添加純水作為殘餘部分， (比較例4) 在相當於研磨液全體的50質量％的純水裡添加氫氧 化钟。 充分地麟混合物後，將石夕氧粒子（二次粒徑約2 的膠體魏粒子）以研絲含有量成為約麻的值 式添加。進而，將鈽氧粒子（鈽氧研餘分散液、二次粒 徑.350 rnn、日立化成工業股份有限公司製作、商品名. GPX系列、pH8〜9)以研餘含有量成絲3所示的值的 方式添加。添加純水作為殘餘部分，調整至合計刚質量 %。 (比較例5) 在相當於研磨液全體的5 〇質量％的純水裡使表3中的 化合物A (1，2,4-三唑）溶解後，添加氫氧化鉀。 接著，將矽氧粒子（二次粒徑約25nm的膠體矽氧粒 子）以研磨粒含有量成為表3所示的值的方式添加。進而， 將鈽氧粒子（鈽氧研磨粒分散液、二次粒徑：35〇nm、曰 立化成工業股份有限公司製作、商品名：GPX系列、ρΉ 8〜9)以研磨粒含有量成為表3所示的值的方式添加。充 分地攪拌混合物後，添加表3中的氧化劑（過硫酸銨）的 10質里/〇水溶液，充分地授拌混合物。添加純水作為殘餘 201249975 4223lpif 部分，調整至合計100質量0/〇。 (比較例6) 在相當於研舰全體的50質量％的 化合物A (甘胺酸）溶解後，添加氫氧化卸。使表3中的 接著，將矽氧粒子（二次粒彳( 子）以研練含有量成絲3所氧粒 添加表3中的氧化劑（過硫酸錢）的ι〇 “ =後’ 添加純水作為殘餘部分，霞至== (比較例7) 質量％的純水裡使蘋果酸 在相當於研磨液全體的5〇 溶解後’添加氫氧化卸。 ㈣^ 物後，財氧好（二次粒㈣25咖 ，财練子）简餘対私絲3所科值的方 ，添加。氧粒子（鈽氧研磨粒分散液、二次粒 t 3/50 nm、曰立化成工業股份有限公司製作、商品名： GPX系列、pH 8〜9)以研磨粒含有量成絲3所示的值的 方式添加。充分地攪拌混合物後，添加表3中的氧化劑（過 硫酸銨）的1〇質量％水溶液，充分地解混合物。添加純 水作為殘餘部分，調整至合計100質量％。 [研磨粒的粒徑測量] 使用雷射繞射式粒度分布計（堀場製作所製造的 LA-920)測量鈽氧粒子的平均粒徑。此外，使用動態光散 射方式粒度分布計（COULTER Electronics公司製造，商 31 201249975 ΗΔΔΟΐρΐΐ 品名COULTERN4SD)測量石夕氧粒子的平均粒徑。 [pH的測量] 、使用橫河電機股份有限公司製造的「M〇delpH81」測 量前述所調配的各CMP研磨液（25。〇的pH。CMp研磨 液的pH的測量結果如表i〜表3所示。 [半導體基板的研磨1] 在將剛調配好（意指調配後30分以内，以下相同。） 的貫施例1〜實施例10以及比較例1〜比較例7的CMP研 磨液一邊供給至研磨定盤的研磨布上，一邊將半導體基板 (研磨晶圓）的被研磨面壓附在研磨布的狀態下，使研磨 定盤對著半導體基板相對地旋轉，藉此對半導體基板的被 研磨面進行研磨。研磨條件的詳細如下所述。 (研磨條件1) 研磨晶圓：300 mm石夕晶圓、在300 mm石夕晶圓上成膜 矽氧化膜（膜厚1 μιη)的晶圓、在300 mm矽晶圓上成膜 銅膜（膜厚1.4 μιη)的晶圓、在300 mm矽晶圓上成膜氮 化组膜（膜厚0.25μηι)的晶圓。 研磨機：荏原製造所製造，商品名F-REX 研磨定盤旋轉數：123 min·1 托座旋轉數：117 min_i 研磨壓力：21 kPa 研磨液供給量：250ml/min 研磨布：IC1000 (NITTA HAAS 製造） 研磨時間：5分（300 mm矽晶圓）、30秒（成膜矽 32 201249975 4223 lpif 氧化膜的晶圓、成膜峨的晶圓以及成錢化㈣晶圓） 使用商口口名 C8125-11 (Hamamatsu Photonics K.K.製 造）測量石夕晶圓的厚度以及在石夕晶圓上成膜的各覆膜的厚 度，從研磨前後的厚度差以及研磨時間求出研磨速度。將 對應於各基板的研磨速度以表丨〜表3各自表示。此外，表 中研磨速度攔的各記號如下所示。KOBUNSHIKEIKICO., LTD. manufactures "ASKER Rubber Hardness Tester Type D". A measurement error of a general η degree is generated in the measured value of the D hardness of the Shore', so that the same measurement is performed 5 times and then averaged. In addition, the upper limit of the d hardness is defined as 100. The polishing method of the semiconductor substrate of the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, the semiconductor substrate 100 is used for the grinding step and the polishing step. However, the semiconductor substrate 100a shown in (a) of Fig. 4 may be used instead of the semiconductor substrate 100. In the semiconductor substrate 100a, the element 2 and the hollow portion 3a and the hollow portion 3b are formed in the same manner as the semiconductor substrate 1a, and an insulating layer (for example, a tantalum oxide film or a tantalum nitride film) 15 for insulating the TSV is compliant with the hollow portion. The shape of 3a and the hollow portion 3b is formed on the surface 1a, whereby a barrier metal layer (for example, a tantalum layer or a nitride layer) is formed on the insulating layer 15 in conformity with the shape of the insulating layer 15. , a titanium layer, a nitride layer, a tungsten layer, a tungsten nitride layer, 25 〇, even in the case of using such a semiconductor substrate 10a, from the back surface 1b side to the semiconductor substrate 100a After the substrate body 1 is ground and polished, the surface layer portion on the back surface 1b side of the substrate body 1 and the insulating layer 15 and 26 201249975 4223 lpif barrier metal layer 25' are removed, whereby the semiconductor in which TSv7a &amp; TSV7b is exposed on the back surface 1b side can be obtained. Substrate 500a (refer to (b) of FIG. 4). In the semiconductor substrate 500a, since the barrier metal layer 25 is disposed between the TSV 7a, the TSV 7b, and the insulating layer 15, it is possible to suppress diffusion of Cu or the like of the constituent components of the TSV 7a and the TSV 7b to the substrate body 1, and to enhance the TSV. Adhesion of 7a, TSV 7b and insulating layer 15. Further, in the grinding step of the first aspect of the polishing method described above, the substrate body 1 is ground from the back surface 1b by the polishing machine until the insulating layer 5 is about to be exposed, but it may be rubbed from the back side by a grinder. The substrate body 1 is side-ground to the extent that the conductive member 7 is about to be exposed, and the substrate body 1 is layered. In the case of a-hai, in the polishing step of the subsequent grinding step, the substrate body 1 is polished from the back surface 1b to remove the insulating layer 5a, and the conductive member 7 is exposed on the back surface 1b, whereby the TSV 7a can be obtained. Further, in the grinding step of the second aspect of the polishing method described above, the substrate body 1 is ground from the back surface 1b until the conductive member 7 in the hollow portion 3a and the hollow portion 3b is exposed, but it may be ground from the back surface lb side. The substrate body i is exposed to the extent that the conductive member 7 in the hollow portion 3b is exposed immediately after the conductive member 7 in the hollow portion 3a is exposed. Further, in the above-described embodiment, the depths of the plurality of hollow portions are different from each other, but the depths of the plurality of hollow portions may be the same. Further, in the above embodiment, the TSV structure including a plurality of TSVs is formed, but a TSV structure including a single TSV may be formed. [Examples] Hereinafter, the present invention will be further described in detail by way of examples, but the invention is not limited to the examples. [Preparation of CMP polishing liquid] The content of each component in each of the polishing liquids of Examples 1 to 10 and Comparative Example 丨 to Comparative Example 7 was adjusted so as to be in the amounts shown in Tables 丨 to 3, And in the following order. Further, potassium hydroxide and ammonium hydroxide in the basic compound are added in an aqueous solution in consideration of the concentration of the aqueous solution in a predetermined amount. In addition, the Shigyo oxygen particles (gels) and the pure particles in the abrasive grains are added in consideration of the abrasive grain content of the aqueous dispersion so as to be a predetermined amount in the J polishing liquid. Further, the persulfate in the oxidizing agent is an aqueous solution of 〇 mass%, and is added as a predetermined amount of the aqueous solution in the polishing liquid. (Example 1 to Example 1) The compound A in Table 2 was obtained in a pure water corresponding to 5 G% by mass of the entire polishing liquid (the first acid dissociation constant was 7 or less, and a predetermined amount of a basic compound was added) Next, the Xiushi oxygen particles (the secondary particle diameter of about 25 (10) colloidal oxygen phase:::: ^ mouth into the table "Gao table in the form of the value of the kg added 'and then' will be oxygen particles (钸 oxygen Abrasive dispersion, secondary particle size: 35 (w 曰立化化工业股份有限公司, 8:9) 2 =: The content is the two additions shown in Table 1 or Table 2. After filling the mixture, A 10% by mass aqueous solution of the oxidizing agent (this) in Table i or Table 2 was added and sufficiently hydrated, and pure water was added as a residual portion to adjust to a total mass %. 28 201249975 4223lpif (Comparative Example 1) In the equivalent of the polishing liquid After dissolving the compound A (glycine and malic acid) in 50% by mass of pure water, the mixture is sufficiently scrambled with the addition of hydrogen and oxygen, and the particles are as follows (the secondary particle size is about colloidal particles). In addition, the addition of the amount of silk into a three-dimensional formula is added. Path: 350 mn, manufactured by Hitachi Chemical Co., Ltd. GPX series, pH 8 to 9), added in such a manner as to contain the value shown in Table 3. Add pure water as a residual and adjust to %. Negative (Comparative Example 2) After dissolving the surface compound A (glycine and malic acid) in 50% by mass of pure water corresponding to the entire polishing liquid, hydrogen peroxide was added thereto, and further, the asthenes were added. The colloidal stone sulphate of the secondary particle size of about 25 ga) is added to the semi-mixture of the value (4) of the formula 3_, and the oxidizing agent (ammonium persulfate) in Table 3 is added; The water was added to the mixture, and the mixture was adjusted to a total of 100% by mass. (Comparative Example 3) After dissolving the frequency-reducing acid in 50% by mass of pure water corresponding to the entire polishing liquid, potassium hydroxide was added. After the mixture was sufficiently mixed, the Shiki oxygen particles (colloidal Wei particles having a secondary particle size of about 5%) were added so that the content of the particles was as shown in Table 3. Further, the particles were dispersed (Wei Yanyu was dispersed). Liquid, two 29 201249975 gentleman's diameter: 350 nm, Hitachi Chemical Industry The 'GPX series, pH 8~9' is added in the form of a granule containing 2 乍 of the abrasive grains =: :: Adding pure water as a residual, (Comparative Example 4) In 50% by mass of pure water equivalent to the entire polishing liquid After adding a hydrazine gas, the cerium oxide particles (colloidal Wei particles having a secondary particle size of about 2) are added in a value of about 1 gram of the ray content. Further, the cerium oxide particles (the cerium oxide particles) The residue of the residue, the secondary particle size of .350 rnn, manufactured by Hitachi Chemical Co., Ltd., and the product name. GPX series, pH 8 to 9) are added so as to contain the value indicated by the amount of silk 3. As a residual, it was adjusted to the total mass %. (Comparative Example 5) After dissolving Compound A (1,2,4-triazole) in Table 3 in 5 〇 mass% of pure water corresponding to the entire polishing liquid, potassium hydroxide was added. Next, the cerium oxide particles (colloidal cerium particles having a secondary particle diameter of about 25 nm) were added so that the amount of the abrasive particles became the values shown in Table 3. Furthermore, the amount of the abrasive particles is shown in the table of the cerium oxide particles (the cerium oxide particle dispersion, the secondary particle diameter: 35 〇 nm, manufactured by 曰立化成工业股份有限公司, trade name: GPX series, ρΉ 8 to 9). The way the value shown in 3 is added. After the mixture was thoroughly stirred, a 10 mass aqueous solution of oxidizing agent (ammonium persulfate) in Table 3 was added to sufficiently mix the mixture. Add pure water as the residual 201249975 4223lpif section and adjust to a total of 100 masses/〇. (Comparative Example 6) After dissolving 50% by mass of the compound A (glycine) corresponding to the entire research ship, hydrogenation was added. In the following Table 3, the cerium oxide particles (secondary granules (sub) were added to the oxidizing agent (persulfate money) in Table 3 by adding the amount of the oxygen particles to the oxidizing agent (persulfate). Water as a residual, Xia to == (Comparative Example 7) In the pure water of % by mass, the malic acid is dissolved in the 5 〇 corresponding to the whole of the polishing liquid, and then the hydroxide is added. (4) After the product, the oxygen is good (2) Sub-grain (four) 25 coffee, financial training) Jane 対 対 3 3 3 3 3 , , 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧 氧The product name: GPX series, pH 8 to 9) is added so that the amount of the abrasive content is the value shown by the filament 3. After the mixture is sufficiently stirred, 1 〇 mass% of the oxidizing agent (ammonium persulfate) in Table 3 is added. In the aqueous solution, the mixture was sufficiently dehydrated, and pure water was added as a residual portion, and adjusted to a total of 100% by mass. [Measurement of Particle Size of Abrasive Particles] Measurement of helium oxygen using a laser diffraction type particle size distribution meter (LA-920 manufactured by Horiba, Ltd.) The average particle diameter of the particles. In addition, a dynamic light scattering method particle size distribution meter is used ( Manufactured by COULTER Electronics Co., Ltd. 31 201249975 ΗΔΔΟΐρΐΐ Product name COULTERN4SD) The average particle diameter of the spectroscopy oxygen particles is measured. [Measurement of pH] Measured by using "M〇delpH81" manufactured by Yokogawa Electric Co., Ltd. Liquid (25. pH of 〇. The measurement results of the pH of the CMp slurry are shown in Table i to Table 3. [Finishing of the semiconductor substrate 1] It is just finely prepared (it means that within 30 minutes after the mixing, the following is the same.) The CMP polishing liquids of the first embodiment to the tenth embodiment and the comparative examples 1 to 7 are supplied onto the polishing cloth of the polishing platen, and the surface to be polished of the semiconductor substrate (polishing wafer) is pressed against the polishing cloth. In the state where the polishing platen is relatively rotated against the semiconductor substrate, the surface to be polished of the semiconductor substrate is polished. The details of the polishing conditions are as follows. (Polishing condition 1) Grinding wafer: 300 mm Shi Xijing A wafer with a tantalum oxide film (film thickness: 1 μm) formed on a 300 mm Shi Xi wafer, and a copper film (with a film thickness of 1.4 μm) on a 300 mm germanium wafer, at 300 mm Film forming nitride layer on wafer Wafer with a film thickness of 0.25 μm. Grinding machine: manufactured by Ebara Manufacturing Co., Ltd., trade name F-REX Grinding plate rotation number: 123 min·1 Number of rotations: 117 min_i Grinding pressure: 21 kPa Supply of polishing liquid: 250ml/min Abrasive cloth: IC1000 (manufactured by NITTA HAAS) Grinding time: 5 minutes (300 mm 矽 wafer), 30 seconds (film formation 2012 32 201249975 4223 lpif oxide film wafer, film-forming wafer and money (4) Wafer) The thickness of the Shihwa wafer and the thickness of each film formed on the Shihwa wafer were measured using the trade name C8125-11 (manufactured by Hamamatsu Photonics KK), the difference in thickness from before and after polishing, and grinding. Time to determine the grinding speed. The polishing rates corresponding to the respective substrates are shown in Tables - Table 3, respectively. In addition, the symbols of the grinding speed stop in the table are as follows.

Si : 300 mm矽晶圓的研磨速度Si : 300 mm wafer polishing speed

Si〇2 :在300 mm矽晶圓上成膜的矽氧化膜的研磨速 度Si〇2: grinding speed of tantalum oxide film formed on a 300 mm germanium wafer

Cu .在300 mm紗晶圓上成膜的銅膜的研磨速度 TaN :在300 mm矽晶圓上成膜的氮化钽膜的研磨速 度 表1] 實施例1 實施例2 實施例3 雜例4 说1 ς 硏離 硏膽麵 矽氧 铈氧 矽氧丨飾氣 砂氧|鋪氣 矽氣 含有量(質量％) 0.25 0.10 0.25 1 0.25 _ 0.25 1 0.50 0.25 025 抑取 化飾A 化雜_ 甘s 安酸 甘胺酸 [甘騰 甘B 麵 甘Β $敌 含有量(質量%) 0.50 0.50 0.50 0.50 η cn 鹼性化合物 化雜種類 氫氧化鉀 纖倾 氫氣#•拥 氫氣化紳 含有：質量%) 0.37 0.37 - 0.37 0.37 0Τ7 氧娜 化挪獅 過硫酸敍 綱臟 過硫酸銘 過硫酸銨 過硫酸銨 含有量(質量%) 0.25 0.25 0.25 0.10 〇 50 PH 10.6 10.4 10.3 10.6 inn 硏磨I度 (nm/min) Si 850 820 870 830 IV/.v QQ〇 SA 250 480 一 520 510 490 Cu 320 300 290 120 560 TaN 15 20 17 12 35 33 2012499754223 lpif [表2] S施例6 Η施例7 實施例8 實施例9 讎例10 硏離 硏®粒種類 矽氧 姉氣 矽氧 姉氧 矽氧 姉氣 矽氧 鈽氧 矽氣 鈽氣 含有s(質量％) 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 化潍A 化合物種類 甘胺酸 組肢酸 — 甘胺酸 甘胺酸 含有s(質量％) 0.50 0.50 — 0.50 0.50 化合物種類 — — 縣酸 — 蘋果酸 含有a(質:a%) — — 0.50 — 0.01 鹸性化合物 化合物種類 氫氧化鉀 mm 氫氧化鉀 化鉀 a氧化銨 氫氧化鉀 含有ffi(質量％) 0.37 0.37 0.51 0.37 0.10 0.37 H細 化飾種類 過硫酸鉀 雕纖 過硫酸銨 臟酿 過Μ銨 含有體量9W 0.25 0.25 0,25 0.25 0.25 pH 10.6 10.5 10.3 11.5 10.6 硏藤s度 (nm/min) Si 830 830 990 950 840 Si〇2 470 520 590 510 570 Cu 120 290 210 600 240 TaN 15 350 400 25 370 [表3] 比較例1 比較例2 比較例3 比較例4 比較例5 比較例6 比较例7 硏磨粒 矽氣 矽氧 - 矽鈕 鈽铤 矽鈕 tm 矽餌 姉氣 矽铤 - 矽氧 姉鈕 含有sens%) 0.25 025 025 - 0.25 0.25 0.25 025 0.25 0.25 0.25 - 0.25 0.25 化合物A 化雜麵 甘胺酸 甘肢酸 - — 1,2,4-三唑 甘胺酸 - 含有sens%) 0.50 050 - - 0.50 0.50 — 化細觀 勘果酸 蘋果酸 较果酸 — — — 窃果酸 含有《(过量％) 0.01 0.01 0.01 一 - - 0.50 化挪觀 S纽化鉀 氫鈦化鉀 显氣化紳 銥β化狎 化紳 氫级化鉀 E氣化鉀 含有SOlfi%) 0.37 0.37 0.02 0.37 0.37 0.37 0.37 α化劑 化合物獅 - 過硫酸按 - - 過硫酸銨 過硫酸銨 過硫酸铵 台有stua%) - 0.25 - 一 0.25 025 0.25 pH 10.7 10.3 10.8 13.2 10.6 10.2 5.2 硏磨速度 (nm/min) Si 980 880 380 820 870 970 340 Si〇! 490 18 480 450 430 11 460 Cu 98 280 85 45 55 330 280 TaN 350 340 320 60 380 18 200 實施例1〜實施例10的CMP研磨液中的任一矽晶圓的 研磨速度為800 nm/min以上，例如，可知得到了用以消除 磨削後的磨削痕的充分的研磨速度。此外，任一矽氧化膜 的研磨速度亦為250 nm/min以上，例如，可知可得到充分 的研磨速度而使矽氧化膜所彼覆的電極露出。 此外，從實施例1〜實施例3的評估結果來看，可知藉 34 201249975 4223lpif 由鈽*氧粒子的対制增減而可以控财氧化膜的研磨速 度。藉此，例如可以使用具有TSV的尺寸或圖帛密度以及 石夕氧化膜的厚度等相異的各式各樣的種類的TSV構造的 半導體基板的背面研磨而使矽氧化膜所彼覆的電極露出。 實施例1〜實施例丨〇的C M P研磨液中的任一銅膜的研 磨速度為120 nm/min以上，因此可知能夠以充分的研磨速 度進行研磨。此外，從實施例2、實施例4以及實施例5 的評估結果來看，可知藉由氧化劑的含有量的增減，可以 控制銅膜的研磨速度。例如，藉此可依所希望的大小控制 半導體基㈣背财的貫通電㈣及基板本體的深度差。 從實施例7的評估結果來看，在使用組胺酸作為第一 酸解離常數為7以下的化合物的情況下，氮化组膜的研磨 速度為350 nm/min，因此可知可以高速對氮化鈕膜進行研 磨丄藉此，例如，作為抑制銅的擴散或提升銅與矽氧化膜 的岔著性的目的，即便在使用如氮化鈕膜的阻障金屬層的 情況下，可以除去氮化鈕膜而使銅露出。 ^從實施例8的評估結果來看，即便在使用蘋果酸作為 第酸解離常數為7以下的化合物的情況下，可知可與胺 基酸同樣地對矽晶圓以及矽氧化膜進行研磨。進而，氮化 鈕膜的研磨速度為400 nm/min，因此可知可以高速對氮化 鈕膜進行研磨。藉此，例如，作為抑制銅的擴散或提升銅 與石夕氧化膜的遂著性的目的，即便在使用如氮化组膜的阻 障金屬層的情況下，可以除去氮化鈕膜而使銅露出。 從貫施例9的評估結果來看，含有作為鹼性化合物的 35 201249975 4223lpif 氫氧化銨的CMP研綠與僅含有料驗性化合物的氮氧 化钟（KOH)的CMP研磨液相較下，可知可以顯著地提 升銅膜的研磨速度。 從實施例10的評估結果來看，含有 ，酸的蘋果酸磨液與不含該有機酸的實“卜 實施例6以及實施例9的CMP研磨液相較下，可知可以 高速對氮化钽膜進行研磨。藉此，例如，即便在使用如氮 化组膜的阻障金屬層的情況下，可以除去氮化鈕膜而使銅 露出。 比較例1中，矽晶圓的研磨速度為高速，另一方面， 銅膜的研磨速度較慢。認為CMP研磨液裡不含氧化劑， 因此較難進行銅膜的研磨。 比較例2中，矽晶圓的研磨速度為高速，另一方面， 石夕氧化膜的研磨速度為18 nm/min而較慢。認為CMP研磨 液裡不含錦氧粒子，因此較難進行石夕氧化膜的研磨。 比較例3中’矽氧化膜的研磨速度良好，但是與比較 例1相同’ CMP研磨液裡不含氧化劑，因此銅膜的研磨速 度較慢。 比較例4中，CMP研磨液含有氫氧化鉀0.37質量％， 因此矽晶圓的研磨速度良好，但是CMP研磨液的pH為 13.2，非常地高。在如此強的鹼區域下會產生矽氧的解聚 合，CMP研磨液的pH或研磨速度容易變動，因而不佳。 此外，比較例4中，CMP研磨液裡不含氧化劑，因此銅膜 的研磨速度較慢。 36 201249975 4223lpif 比較例5中’石夕晶圓的研磨速度以及石夕氧化膜的研磨 速度為高速，但是儘管CMP研磨液含有氧化劑，銅膜的 研磨速度與實施例1〜實施例10比較下仍較慢。認為主要 疋因為作為銅膜的良好的防餘劑而令人皆知的β坐類的 1，2,4-三唾，所以銅膜被過度地防餘而難以進行研磨。 比較例6中，矽晶圓的研磨速度為970 nm/min的高 速’但是石夕氧化膜的研磨速度為11 nm/min而較慢，氮化 组膜的研磨速度為18 nm/min而較慢。 比較例7中，CMP研磨液含有氫氧化鉀0.37質量％ , 但是CMP研磨液的pH為5.2而較低，脫離了矽的溶解區 域’因此石夕晶圓的研磨速度為340 nm/min而較低。 [半導體基板的研磨2] 在將剛調配好的實施例2的CMP研磨液一邊供給至 研磨定盤的研磨布上，一邊將半導體基板（研磨晶圓）的 被研磨面壓附在研磨布的狀態下，使研磨定盤對著半導體 基板相對地旋轉’猎此對半導體基板的被研磨面進行研 磨。研磨條件的詳細如下所述。 (研磨條件2) 研磨晶圓：將已形成TSV的矽晶圓PT-007 ( Philtech hie.製造）固定在支撐板，背面磨削至60 μιη左右進行薄 層化後’以2 cm角度進行切割（dicing)的矽晶圓。 研磨裝置：Nano Factor Co.，Ltd.製造，FACT-200 型 研磨布：ICl〇〇〇(NITTAHAAS製造）（蕭氏D硬度： 59) 37 201249975 4223 lpif 研磨定盤旋轉數：80 rpm 托座旋轉數：無驅動裝置（自由旋轉） 研磨壓力：33.83 kPa 研磨液供給罝.16ml/min 研磨時間：50分 圖5為以FE-SEM觀察研磨後的被研磨面的照片。藉 由研磨除去絕緣層的;g夕氧化膜，可知成為電極的鋼會露 出。因為銅在電極表面露出，認為可以使用於上下積層的 LSI晶片的連接。 圖6為以接觸式深度（c〇ntact Depth )計測量存在於 研磨後的被研磨面的TSV的形狀的結果。可知直徑40 μιη 的TSV為從半導體基板的主面突出〇〇8 μιη左右的形狀， 且半導體基板與TSV的高低差小。 藉由使用CMP研磨液的研磨可得上述的形狀，認為 是因為組合了含有規定成分的CMP研磨液與蕭氏D硬度 為30〜90的較硬質的研磨布而使效果變大。 【圖式簡單說明】 圖1為表示本發明的一實施形態的研磨方法的步驟的 模式剖面圖。 圖2為表示本發明的一實施形態的研磨方法的步驟的 模式剖面圖。 圖3為表示本發明的一實施形態的研磨方法的步驟的 模式剖面圖。 圖4為表示本發明的另一實施形態的研磨方法的步驟 38 201249975 4223lpif 的模式剖面圖。 圖5為表示研磨後的被研磨面的SEM照片。 圖6為表示研磨後的被研磨面中的T S V形狀的測量結 果。 【主要元件符號說明】 1 :基板本體 la:表面（其中一方的主面） lb :背面（另一方的主面） 2 :元件 3a、3b :中空部 5、5a、5b、15 :絕緣層 7:導電構件 7a、7b : TSV (貫通電極） 13a、13b :貫通孔 25 :阻障金屬層 100、100a、200、300、400、500、500a :半導體基板 39Cu. Polishing speed of copper film formed on 300 mm yarn wafer TaN: polishing rate of tantalum nitride film formed on 300 mm 矽 wafer Table 1] Example 1 Example 2 Example 3 4 says 1 ς 硏 硏 硏 硏 矽 矽 矽 矽 矽 铈 丨 丨 丨 | | | | | 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25甘s 安酸甘胺酸 [Gangtangan B Β Β 敌 敌 敌 敌 敌 敌 敌 敌 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性 碱性%) 0.37 0.37 - 0.37 0.37 0Τ7 Oxygenated lion sulphate sulphate sulphate persulfate ammonium persulfate ammonium persulfate content (% by mass) 0.25 0.25 0.25 0.10 〇50 PH 10.6 10.4 10.3 10.6 inn honing I degree ( Nm/min) Si 850 820 870 830 IV/.v QQ〇SA 250 480 520 510 490 Cu 320 300 290 120 560 TaN 15 20 17 12 35 33 2012499754223 lpif [Table 2] S Example 6 7 Example 7 Implementation Example 8 Example 9 Example 10 硏 硏 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒 粒Helium contains s (% by mass) 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 潍 A compound type glycine acid limb acid - glycine acid glycine contains s (% by mass) 0.50 0.50 — 0.50 0.50 Compound type— — 酸酸— Malic acid contains a (mass: a%) — — 0.50 — 0.01 鹸 compound compound type potassium hydroxide mm potassium potassium hydroxide a ammonium oxide potassium hydroxide containing ffi (% by mass) 0.37 0.37 0.51 0.37 0.10 0.37 H refining type potassium persulfate engraving fiber ammonium persulfate dirty brewing ammonium sulphate content 9W 0.25 0.25 0,25 0.25 0.25 pH 10.6 10.5 10.3 11.5 10.6 硏 s degree (nm / min) Si 830 830 990 950 840 Si〇2 470 520 590 510 570 Cu 120 290 210 600 240 TaN 15 350 400 25 370 [Table 3] Comparative Example 1 Comparative Example 2 Comparative Example 3 Comparative Example 4 Comparative Example 5 Comparative Example 6 Comparative Example 7 honing particle 矽Gas 矽 - - 矽 button t button tm 矽 矽 姊 矽铤 - 矽 姊 button contains sens%) 0.25 025 025 - 0.25 0.25 0.25 025 0.25 0.25 0.25 - 0.25 0.25 Compound A — 1,2,4-triazole glycine - Contains sens%) 0.50 050 - - 0.50 0.50 - cleavage of fruit acid malic acid compared to fruit acid - 窃 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸 酸Potassium gasification 绅铱β 狎 绅 绅 绅 绅 绅 E E E E E 0.3 0.3 0.3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 - - - - - - - - - - - Ammonium has stua%) - 0.25 - 0.25 025 0.25 pH 10.7 10.3 10.8 13.2 10.6 10.2 5.2 Honing speed (nm/min) Si 980 880 380 820 870 970 340 Si〇! 490 18 480 450 430 11 460 Cu 98 280 85 45 55 330 280 TaN 350 340 320 60 380 18 200 The polishing rate of any one of the CMP polishing liquids of Examples 1 to 10 is 800 nm/min or more, for example, it is known that the grinding is eliminated. Full grinding speed of the ground marks after shaving. Further, the polishing rate of any of the tantalum oxide films is also 250 nm/min or more. For example, it can be seen that a sufficient polishing rate can be obtained to expose the electrodes of the tantalum oxide film. Further, from the evaluation results of the first to third embodiments, it can be seen that the polishing rate of the oxide film can be controlled by the increase or decrease of the 钸* oxygen particles by 34 201249975 4223lpif. For this reason, for example, an electrode coated with a back surface of a semiconductor substrate having various types of TSV structures having different sizes, such as the size of the TSV, the thickness of the ruthenium oxide film, and the thickness of the iridium oxide film, can be used. Exposed. In any of the C M P polishing liquids of Examples 1 to 丨〇, the polishing rate of the copper film was 120 nm/min or more. Therefore, it was found that the polishing can be performed at a sufficient polishing rate. Further, from the evaluation results of Example 2, Example 4, and Example 5, it is understood that the polishing rate of the copper film can be controlled by increasing or decreasing the content of the oxidizing agent. For example, it is possible to control the penetration of the semiconductor base (4) and the depth difference of the substrate body in accordance with the desired size. From the evaluation results of Example 7, when the histidine acid was used as the compound having the first acid dissociation constant of 7 or less, the polishing rate of the nitrided film was 350 nm/min, and thus it was found that the nitriding can be performed at a high speed. The button film is polished, for example, as a purpose of suppressing diffusion of copper or enhancing the adhesion of copper and tantalum oxide film, even in the case of using a barrier metal layer such as a nitride film, nitriding can be removed. The button film is used to expose the copper. From the evaluation results of Example 8, even when malic acid was used as the compound having the acid dissociation constant of 7 or less, it was found that the tantalum wafer and the tantalum oxide film can be polished in the same manner as the amino acid. Further, since the polishing rate of the nitride film was 400 nm/min, it was found that the nitride film can be polished at a high speed. Thereby, for example, as a purpose of suppressing the diffusion of copper or enhancing the adhesion of the copper oxide film, even in the case of using a barrier metal layer such as a nitride film, the nitride film can be removed. Copper is exposed. From the results of the evaluation of Example 9, the CMP green liquid containing 35 201249975 4223 lpif ammonium hydroxide as a basic compound is lower than the CMP polishing liquid phase of a nitrogen oxide clock (KOH) containing only the test compound. The polishing speed of the copper film can be significantly improved. From the evaluation results of Example 10, it can be seen that the acid-containing malic acid grinding liquid is lower than the CMP polishing liquid phase of Example 6 and Example 9 which does not contain the organic acid. The film is polished, whereby, for example, even in the case of using a barrier metal layer such as a nitride film, the nitride film can be removed to expose the copper. In Comparative Example 1, the polishing speed of the germanium wafer is high. On the other hand, the polishing rate of the copper film is slow. It is considered that the CMP polishing liquid does not contain an oxidizing agent, so it is difficult to polish the copper film. In Comparative Example 2, the polishing rate of the germanium wafer is high, and on the other hand, the stone The etching rate of the oxidized film is slow at 18 nm/min. It is considered that the CMP polishing liquid does not contain the cerium oxide particles, so it is difficult to polish the shi oxidized film. In the comparative example 3, the polishing rate of the bismuth oxide film is good. However, in the same manner as in Comparative Example 1, the CMP polishing liquid contained no oxidizing agent, so the polishing rate of the copper film was slow. In Comparative Example 4, the CMP polishing liquid contained 0.37 mass% of potassium hydroxide, so the polishing rate of the germanium wafer was good, but The pH of the CMP slurry is 1 3.2, very high. Under such a strong alkali region, depolymerization of helium is generated, and the pH or polishing rate of the CMP slurry is easily changed, which is not preferable. Further, in Comparative Example 4, the CMP slurry contains no oxidizing agent. Therefore, the polishing rate of the copper film is slow. 36 201249975 4223lpif In the comparative example 5, the polishing rate of the stone wafer and the polishing rate of the stone oxide film are high, but although the CMP polishing liquid contains an oxidizing agent, the polishing rate of the copper film is The comparison between Example 1 and Example 10 is still slow. It is considered that the main film is 1,2,4-three saliva, which is known as a good anti-surplus agent for copper film, so the copper film is excessive. In the comparative example 6, the polishing rate of the tantalum wafer was 970 nm/min, but the polishing rate of the Shihua oxide film was 11 nm/min, and the polishing of the nitrided film was slow. The speed is 18 nm/min and slower. In Comparative Example 7, the CMP slurry contains 0.37 mass% of potassium hydroxide, but the pH of the CMP slurry is 5.2 and lower, and it is separated from the dissolved region of the crucible. The grinding speed is 340 nm/min and lower. Polishing of the bulk substrate 2] The state in which the polished surface of the semiconductor substrate (polishing wafer) is pressed against the polishing cloth while the CMP polishing liquid of the second embodiment is supplied to the polishing cloth of the polishing platen Next, the polishing plate is relatively rotated against the semiconductor substrate, and the surface to be polished of the semiconductor substrate is polished. The polishing conditions are as follows. (Polishing condition 2) Polishing the wafer: Twinning of the TSV has been formed Round PT-007 (manufactured by Philtech Hie.) was fixed on a support plate, and the back surface was ground to about 60 μm to be thinned and then diced at a 2 cm angle. Grinding device: manufactured by Nano Factor Co., Ltd., FACT-200 type abrasive cloth: ICl〇〇〇 (manufactured by NITTAHAAS) (Shore D hardness: 59) 37 201249975 4223 lpif Grinding plate rotation number: 80 rpm Number: No drive (free rotation) Grinding pressure: 33.83 kPa Grinding solution supply 罝.16 ml/min Grinding time: 50 minutes Fig. 5 is a photograph of the polished surface after polishing by FE-SEM observation. By removing the insulating layer by polishing, it is known that the steel which becomes an electrode is exposed. Since copper is exposed on the surface of the electrode, it is considered that it can be used for the connection of the LSI wafer which is laminated on the upper and lower layers. Fig. 6 is a graph showing the results of measuring the shape of the TSV present on the surface to be polished after grinding by a contact depth (c〇ntact Depth). It can be seen that the TSV having a diameter of 40 μm protrudes from the main surface of the semiconductor substrate by about 8 μm, and the difference between the height of the semiconductor substrate and the TSV is small. The above shape can be obtained by polishing using a CMP polishing liquid, and it is considered that the effect is enhanced by combining a CMP polishing liquid containing a predetermined component and a relatively hard abrasive cloth having a Shore D hardness of 30 to 90. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing the steps of a polishing method according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view showing the steps of a polishing method according to an embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing the steps of a polishing method according to an embodiment of the present invention. Fig. 4 is a schematic cross-sectional view showing the step 38 201249975 4223lpif of the polishing method according to another embodiment of the present invention. Fig. 5 is a SEM photograph showing a surface to be polished after polishing. Fig. 6 is a graph showing the measurement results of the T S V shape in the surface to be polished after polishing. [Description of main component symbols] 1 : Substrate body la: surface (one of the main faces) lb : Back surface (the other main surface) 2 : Components 3a, 3b: Hollow portions 5, 5a, 5b, 15 : Insulation layer 7 : Conductive members 7a, 7b: TSV (through electrodes) 13a, 13b: through holes 25: barrier metal layers 100, 100a, 200, 300, 400, 500, 500a: semiconductor substrate 39

Claims (1)

201249975 42ZJlpif 七、申請專利範圍： 1. 一種CMP研磨液，包括： 含鈽氧粒子以及矽氧粒子的研磨粒； 第一酸解離常數為7以下的化合物（但是唑類除外）； 鹼性化合物；以及 過硫酸鹽， 其中CMP研磨液的pH為9.0〜丨2.0。 2. 如申請專利範圍第1項所述的CMP研磨液，其中 所述第一酸解離常數為7以下的化合物包括胺基酸。 3. 如申請專利範圍第2項所述的CMP研磨液，其中 所述胺基酸為α·胺基酸。 4. 如申請專利範圍第丨項至第3項中任一項所述的 CMP研磨液，其中所述第一酸解離常數為7以下的化合物 包括含羧基的有機酸。 5. 如申請專利範圍第1項至第4項中任一項所述的 CMP研磨液，其中所述驗性化合物包括選自含氮驗性化合 物以及無機驗性化合物的至少一種。 6. 如申請專利範圍第5項所述的CMP研磨液，其中 所述鹼性化合物包括選自氩氧化鉀、氫氧化鈉、氫氧化四 甲銨以及氫氧化銨的至少一種。 7. 如申請專利範圍第1項至第6項中任一項所述的 CMP研磨液，其中所述鹼性化合物的含有量為〇.1〇質量％ 以上° 8. 如申請專利範圍第1項至第7項中任一項所述的 201249975 4223 lpif CMP研磨液，其中所述過硫酸鹽包括選自過硫酸鉀以及過 硫酸銨的至少一種。 9. 如申請專利範圍第1項至第8項中任一項所述的 CMP研磨液’驗自另—方的主面侧對半導體基板的基板 本體進行研磨，使導電構件在所述另一方的主面侧露出而 形成貫通電極構造，其中 所述半導體基板包括： 所述基板本體，形成有僅在其中一方的主面上開口的 中空部；以及 所述導電構件，配置於所述中空部内且應該成為貫通 電極。 10. 如申請專利範圍第1項至第8項中任一項所述的 CMP研磨液，用於從其中一方的主面側或者另一方的主面 側對半導體基板的基板本體進行研磨，其中 所述半導體基板包括： 所述基板本體，形成有從所述其中—方的主面貫通至 所述另一方的主面的貫通孔；以及 貫通電極’配置於所述貫通孔内。 11. 一種半導體基板的研磨方法，包括： 提供半導體基板，所述半導體基板包括： 基板本體，形成有僅在其中一方的主面上開口的 中空部；以及 導電構件，配置於所述中空部内且應該成為貫通 電極；以及 201249975 使用申請專利範圍第l項至第8項中任一項所述的 CMP研磨液從另一方的主面側對所述半導體基板的所述 基板本體進行研磨，使所述導電構件在所述另二方的主面 侧露出而形成貫通電極構造。 12. —種半導體基板的研磨方法，包括：提供半導體 基板，所述半導體基板包括： 基板本體，形成有從其中一方的主面貫通立另 方的主面的貫通孔；以及 貫通電極，配置於所述貫通孔内；以及 使用申請專利範圍第1項至第8項中任一項所述的 CMP研磨液從所述其中一方的主面側或者所述另一方的 主面侧對所述半導體基板的所述基板本體進行研磨。 13. 如申請專利範圍第11項或第12項所述的研磨方 法，更包括磨削步驟： 在所述研磨步驟之前，從所述研磨步驟中被研磨的主 面侧對所述基板本體進行磨削。 14. 如申請專利範圍第η項至第13項中任一項所述 的研磨方法，其中 在所述研磨步驟中，使用蕭氏D硬度為30〜90的研磨 布對所述基板本體進行研磨。 42201249975 42ZJlpif VII. Patent application scope: 1. A CMP polishing liquid comprising: abrasive particles containing xenon particles and xenon particles; a compound having a first acid dissociation constant of 7 or less (except for azoles); a basic compound; And persulfate, wherein the pH of the CMP slurry is 9.0 to 丨2.0. 2. The CMP slurry according to claim 1, wherein the compound having a first acid dissociation constant of 7 or less comprises an amino acid. 3. The CMP slurry according to claim 2, wherein the amino acid is an α-amino acid. 4. The CMP slurry according to any one of claims 3 to 3, wherein the compound having a first acid dissociation constant of 7 or less includes a carboxyl group-containing organic acid. 5. The CMP slurry according to any one of claims 1 to 4, wherein the test compound comprises at least one selected from the group consisting of nitrogen-containing test compounds and inorganic test compounds. 6. The CMP slurry according to claim 5, wherein the basic compound comprises at least one selected from the group consisting of argon oxyhydroxide, sodium hydroxide, tetramethylammonium hydroxide, and ammonium hydroxide. 7. The CMP slurry according to any one of the preceding claims, wherein the basic compound is contained in an amount of 0.1% by mass or more. The 201249975 4223 lpif CMP slurry according to any one of item 7, wherein the persulfate comprises at least one selected from the group consisting of potassium persulfate and ammonium persulfate. 9. The CMP slurry according to any one of claims 1 to 8, wherein the substrate body of the semiconductor substrate is ground from the other main surface side, and the conductive member is on the other side. The main surface side is exposed to form a through electrode structure, wherein the semiconductor substrate includes: the substrate body is formed with a hollow portion opened only on one of the main faces; and the conductive member is disposed in the hollow portion It should be a through electrode. The CMP polishing liquid according to any one of claims 1 to 8, wherein the substrate body of the semiconductor substrate is ground from one of the main surface sides or the other main surface side, wherein The semiconductor substrate includes: the substrate body having a through hole penetrating from the main surface of the one of the main surfaces to the other main surface; and the through electrode 'disposed in the through hole. 11. A method of polishing a semiconductor substrate, comprising: providing a semiconductor substrate, the semiconductor substrate comprising: a substrate body having a hollow portion opened only on one of the main faces; and a conductive member disposed in the hollow portion And the CMP polishing liquid according to any one of the first to eighth aspects of the invention, wherein the substrate body of the semiconductor substrate is polished from the other main surface side to make the substrate The conductive member is exposed on the other main surface side to form a through electrode structure. 12. A method of polishing a semiconductor substrate, comprising: providing a semiconductor substrate, the semiconductor substrate comprising: a substrate body having a through hole formed to penetrate from a main surface of one of the main surfaces; and a through electrode disposed at And the CMP polishing liquid according to any one of the first to eighth aspects of the invention, wherein the semiconductor is applied to the semiconductor from the one main surface side or the other main surface side The substrate body of the substrate is ground. 13. The grinding method according to claim 11 or 12, further comprising a grinding step: before the grinding step, performing the substrate body from the main surface side to be ground in the grinding step Grinding. The polishing method according to any one of the above-mentioned claims, wherein the substrate body is ground using a polishing cloth having a Shore D hardness of 30 to 90 in the grinding step. . 42
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