200908218 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體的製造方法，特別是關於具有接觸 窗之半導體的製造方法。 【先前技術】 習知製作半導體接觸窗時，通常會以硼磷矽酸玻璃(BPSG) 作為填充層間介電層的材料。一般而言，硼鱗矽酸玻璃的填充能 力最佳只能達到外觀比值(aspect ratio) 6的溝渠。所謂外觀比值係 指溝渠之深度與橫截面寬度的比值。隨著半導體尺寸的縮小及元 件密度的增加，溝渠外觀比值也隨之增加，硼磷矽酸玻璃逐漸出 現填充能力不足的問題。 圖1A至圖1B係顯示習知半導體接觸窗的製程。如圖丨八所 示’提供一基板10 ’其内部已形成各種元件，如閘極U。基板 10上鋪有圖案化犧牲層12，係覆蓋基板1〇之預定接觸區域。硼 磷矽酸玻璃介電層13係毯覆式地鋪設在基板1〇及圖案化犧牲層 12上方。然而，如上述，由於删磷石夕酸玻璃的填充能力不佳，爛 磷矽酸玻璃介電層13内便形成一孔洞14。孔洞14在後續進行硼 磷矽酸玻璃介電層13平坦化時，便會成為如圖1B所示的凹口 15。形成像凹口 15這樣的結構對後續的製程是相當不利的。圖 1C係顯不將犧牲層12去除之後，填入金屬導電材料於接觸窗16 的示意圖。如圖ic所示，金屬導電材料也會填入凹口 15中，進 而導致位τό線間產生短路現象。由此可知，單純糊刪石夕酸玻 璃來製作半導體翻窗製程之介電質已經不能符合實際需求。所 以，需要有一種改良方法來解決習知的問題。 4NTC/06035TW ； 2006-0017-TW 5 200908218 【發明内容】 本發明於一方面係提出一種接觸窗製程之填補孔洞的方 法’ ^含提供具有-歡接觸區基板；形成___圖案化犧牲 層覆蓋預定接酿域’醜化犧牲層定義—溝渠；碱―第一介 電層覆蓋溝渠，第-介電勒部可能具有—孔洞；去除第一介電 層之邛为，形成一第二介電層覆蓋第一介電層以避免該孔洞露 出；及去除酵化犧牲層以形成—接㈣暴露基板之該預定接觸 區域。 本發明於另一方面係提出一種接觸窗製程之填補孔洞的方 法’ ^含提供具有-預定接觸區域的—基板；形成—圖案化犧牲 層覆蓋巧接觸區域，圖案化犧牲層定義—溝渠；形成一第一介 電層覆蓋溝驗_化犧牲層，第—介電層内部可能具有一孔 洞；研磨第-介電層；形成—第二介覆難—介電層及圖案 化犧牲層以避免該孔洞露出；去除第二介電層之—部分以露出圖 案，犧牲層；絲_化犧牲層以形成—接觸窗暴露絲板之該 預疋接觸區域。 【實施方式】 以下將參考所附圖式示範本發明之較佳實施例。所附圖式中 用相同狀件符號。應注意為清楚呈現本發明，所 兀件並非按照實物之比例繪製，而且為避免模糊本 以下說明亦省略習知之零組件、相關材料、及其相200908218 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method of fabricating a semiconductor, and more particularly to a method of fabricating a semiconductor having a contact window. [Prior Art] When a semiconductor contact window is conventionally produced, borophosphoric acid glass (BPSG) is usually used as a material for filling the interlayer dielectric layer. In general, the filling ability of borosilicate glass is best achieved only in the aspect ratio of 6 trenches. The apparent ratio refers to the ratio of the depth of the trench to the width of the cross section. As the size of the semiconductor shrinks and the density of the element increases, the ratio of the appearance of the trench increases, and the borophosphoric acid glass gradually suffers from insufficient filling ability. 1A-1B are diagrams showing a process of a conventional semiconductor contact window. As shown in Fig. 8 'providing a substrate 10', various components such as a gate U have been formed inside. A patterned sacrificial layer 12 is disposed on the substrate 10 to cover a predetermined contact area of the substrate 1A. A borophosphoric acid glass dielectric layer 13 is blanket-laid over the substrate 1 and the patterned sacrificial layer 12. However, as described above, since the filling ability of the dephosphoric acid glass is not good, a hole 14 is formed in the dielectric layer 13 of the rotten phosphoric acid glass. The hole 14 becomes a notch 15 as shown in Fig. 1B when the borophosphosilicate glass dielectric layer 13 is subsequently planarized. Forming a structure like the recess 15 is quite disadvantageous for subsequent processes. Fig. 1C is a schematic view showing the filling of the metal conductive material in the contact window 16 after the sacrificial layer 12 is removed. As shown in Figure ic, the metal conductive material is also filled into the recess 15, which in turn causes a short circuit between the lines of the position τό. It can be seen from this that the dielectric material of the semiconductor window turning process can not meet the actual demand. Therefore, there is a need for an improved method to solve the conventional problems. 4NTC/06035TW; 2006-0017-TW 5 200908218 SUMMARY OF THE INVENTION The present invention is directed to a method for filling a hole in a contact window process, which comprises providing a substrate having a contact area; forming a ___ patterned sacrificial layer Covering the predetermined brewing domain 'the definition of the sacrificial sacrificial layer—the ditch; the alkali-first dielectric layer covering the ditch, the first-dielectric portion may have a hole; the first dielectric layer is removed to form a second dielectric The layer covers the first dielectric layer to prevent the hole from being exposed; and the fermented sacrificial layer is removed to form the fourth contact substrate to expose the predetermined contact area. In another aspect, the present invention provides a method for filling a hole in a contact window process, comprising: providing a substrate having a predetermined contact area; forming a patterned sacrificial layer covering the contact area, and patterning the sacrificial layer defining the trench; forming A first dielectric layer covers the trench layer, and the first dielectric layer may have a hole therein; the first dielectric layer is ground; the second dielectric layer and the patterned sacrificial layer are formed to avoid The hole is exposed; a portion of the second dielectric layer is removed to expose the pattern, a sacrificial layer; and a sacrificial layer is formed to form a contact window that exposes the pre-contact region of the wire. [Embodiment] Hereinafter, preferred embodiments of the present invention will be exemplified with reference to the accompanying drawings. The same symbols are used in the drawings. It should be noted that in order to clearly illustrate the present invention, the components are not drawn to the actual scale, and in order to avoid obscuring the present description, the conventional components, related materials, and their phases are omitted.
4NTC/06035TW ； 2006-00i7-TW 200908218 圖2至圖9係本發明之一具體實施彳列的製程流程剖面圖。如 圖2所不’提供一基板20,其表面上可有一共形的氮化襯層21， 並具有一預定接觸區域2〇a。基板20可為於半導體元件製程中 需要製作接觸的任何基板。預定接觸區域2〇可以為基板2〇内的 閘極接觸㊄域、位元線接觸g域，或其他於其他*㈤冑程階段的 各種接觸區域。® 2細包含複數個_結構22的基板2〇來示 範說明本發明。 然後，如圖3所示，形成一犧牲層3!於基板2〇上。犧牲層 的材料較佳為多晶秒’可使用化學氣相沉積法來形成，其厚度 較佳係耕基板2G之職_ 7_埃 :硬遮罩層μ於犧_旧。硬_ 32 矽，可使用化學氣相沉積法來形成，其厚度約在5至 nm ° = ον 然後，如圖4所示，利用習知之微 Z 4/於硬遮m再嗎化二二幕圖: 性蝕Μ。若使賤切為硬辟層32的材料，選擇 層32可使㈣知的乾式_，其_射包^ 开^如^及祕等。_之後再糊魏光阻層41移除，以 ==瞧硬遮罩層51。_化硬遮罩= 如圖5及81 6所不’以圖案化硬遮罩層5〗為n =擇性地去除犧牲層3卜以暴露出基板2 為罩幕， 案化犧牲層61覆蓋預定接觸區域20A。若使用多曰刀_而形成圖 便用夕日日矽作為犧牲4NTC/06035TW; 2006-00i7-TW 200908218 FIG. 2 to FIG. 9 are cross-sectional views showing a process flow of one embodiment of the present invention. A substrate 20 is provided as shown in Fig. 2, which may have a conformal nitride liner 21 on its surface and has a predetermined contact area 2〇a. The substrate 20 can be any substrate that requires contact in the fabrication of the semiconductor device. The predetermined contact area 2〇 may be a gate contact five domains in the substrate 2〇, a bit line contact g domain, or other contact areas in other *(5) process stages. The ® 2 finely includes a plurality of substrates 2 of the structure 22 to illustrate the present invention. Then, as shown in FIG. 3, a sacrificial layer 3 is formed on the substrate 2A. The material of the sacrificial layer is preferably polycrystalline seconds. It can be formed by chemical vapor deposition. The thickness of the sacrificial layer is preferably ___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Hard _ 32 矽, can be formed by chemical vapor deposition, its thickness is about 5 to nm ° = ον Then, as shown in Figure 4, using the conventional micro Z 4 / in the hard mask m Figure: Sexual erosion. If the tantalum is cut into the material of the hard layer 32, the selection layer 32 can make the (four) known dry type _, and its _ shot package ^ ^ ^ and secret. After that, the paste photoresist layer 41 is removed to form a mask layer 51 with ==. _ hard mask = as shown in Figures 5 and 81, the pattern of the hard mask layer 5 is n = selective removal of the sacrificial layer 3 to expose the substrate 2 as a mask, covered with a sacrificial layer 61 The contact area 20A is predetermined. If you use a multi-blade _ to form a map, use the eve as a sacrifice
4NTC/06035TW ； 2006-0017-TW 200908218 層31的材料’’要選擇性地去除犧牲層31可使用習知的乾式蝕 刻’其钱刻劑可包含HBr、He及氧氣等。完成選擇性地去除犧 牲層31的步驟之後，可將圖案化硬遮罩層51去除。若圖案化硬 遮罩層51的材料為氮化矽，可利用經加熱之麟酸以濕式蝕刻來 剝除圖案化硬遮罩層51。請注意，完成選擇性地去除犧牲層31 的步驟之後，圖案化犧牲層61將定義一溝渠62，如圖ό所示。 然後，參考圖7，其顯示將圖案化硬遮罩層51去除之後， 再毯覆式地沉積一第一介電層71覆蓋基板2〇之暴露部分及圖案 化犧牲層61，並填充溝渠62。可採用硼磷矽酸玻璃作為第一介 電層71之材料，實施方式可利用化學氣相沉積來完成，所需厚 度約在基板20之表面以上1,000埃左右。反應的前驅物可選自4NTC/06035TW; 2006-0017-TW 200908218 The material of the layer 31' can selectively remove the sacrificial layer 31 using conventional dry etching. The money engraving agent can contain HBr, He, oxygen, and the like. After the step of selectively removing the sacrificial layer 31 is completed, the patterned hard mask layer 51 can be removed. If the material of the patterned hard mask layer 51 is tantalum nitride, the patterned hard mask layer 51 can be stripped by wet etching using heated cinnamic acid. Note that after the step of selectively removing the sacrificial layer 31, the patterned sacrificial layer 61 will define a trench 62, as shown in FIG. Then, referring to FIG. 7, after the patterned hard mask layer 51 is removed, a first dielectric layer 71 is blanket-covered to cover the exposed portion of the substrate 2 and the patterned sacrificial layer 61, and the trench 62 is filled. . Boron phosphate glass can be used as the material of the first dielectric layer 71. Embodiments can be accomplished by chemical vapor deposition at a thickness of about 1,000 angstroms above the surface of the substrate 20. The precursor of the reaction can be selected from
SiH4、PH3、〇2、〇3、b2H6、TEOS、ΤΕΒ (三乙基棚酸鹽， iEthyl-Bome)、ΤΜΡ (三甲基磷酸鹽，Tri_Methyl_phQsphate) ，。硼磷矽酸玻璃沉積完成後，通常需要再進行一道熱流步驟以 平坦化㈣赠_誠自。刪魏玻_減溫度取決於立 玻璃轉移溫度，通常低於WC。在此躯意，完祕覆如積 第-介電層71之後’第-介電層71内會彳艮容驗生如圖中所示 的孔洞74及75。 圖8係顯示以化學機械研磨的方式平坦化第一介電層71至 所需要之高度後所形成的結構。經研磨後’有些孔洞(如孔洞7句 會消除’但有些孔洞(如孔洞75)會變成如圖中所示之凹0 81。可 以習知的顧，例如掃描式電子_觀察是否有凹洞81產 生。如果有，則可形成-第二介電層91來填補凹口 8卜如下所 述。 4NTC/06035TW ； 2006-0017-TW 8 200908218 圖9係顯示毯覆式地沉積第二介電層％的步驟。第二介電 層91的材料可選自任何一種旋塗式介電材料，例如聚石夕氮烷 (Polysilazane)等旋塗式玻璃旋，或是在低溫狀況下以適當的前驅 例如SiH4等來進行反應以生成液態々航合物(silidc acid)。 旋塗完成後可先經過—道熱烘烤步驟，來蒸除缝式玻璃中所含 之有機溶劑。熱烘烤的溫度一般在3〇〇〇c至4〇〇。(：的範圍内，可 將基板20置放在-触板上進行。有機溶辦除錢，再將基 板20送進熱爐管中進行固化步驟，固化溫度較佳在8〇〇t：以下。 固化時可視需要提供氧或氳於熱爐管中。在此應注意，雖然第二 介電層91的形成是為了填補凹口 81。然而，當進行量產時，如 果要檢測母塊基板20是否有產生凹口 81，才決定是否要形成第 二介電層91，將耗費相當多的時間。因此，進行量產時，較佳的 作法係在平坦化第一介電層71之後就直接形成第二介電層91於 第一介電層71的表面上，之前所述檢測是否有凹口 81產生的步 驟可以省略。換言之，為了製程的便利性，不論是否有凹口 81 產生，都可進行第二介電層91的形成步驟。 如圖10所示’固化完成後，再移除第二介電層91的一部分 以露出圖案化犧牲層61。此步驟可以化學機械研磨或蝕刻方式來 執行。在完成上述之各步驟後，第一介電層71或圖案化犧牲層 61在基板20以上之厚度較佳約在4〇〇〇埃至6〇〇〇埃範圍之間。 應注意凹口 81内已被第二介電層91所填補。然而，如果沒有任 何凹口 81產生，此步驟將使第二介電層9完全移除。 接著，如圖11所示去除殘留圖案化犧牲層61以形成—接觸 窗110。接觸窗110暴露預定接觸區域20A。去除殘留圖案化犧 4NTC/06035TW ； 2006-0017-TW 9 200908218 f層6!的方法’可藉由乾式钱刻，使用相對於第一 歹留圖案化犧牲層61有高選擇性的反應氣體來進行:二71對 曰1其去除的方法可触乾式關吏於、^雷 71，對氮化襯層21有高選擇性的反應氣體來進行十於第-介電層 明之僅林㈣德佳實關耐，並_崎定本發 之等效改㈣料，均聽含在下述之申請厚度圍成 4NTC/06035TW ； 2006-0017-TW 10 200908218 【圖式簡單說明】 圖1A至1C為習知接觸窗之製作過程中半導體結構的剖面圖。 圖2至圖11為本發明之一具體實施例之製程流程中半導體結構 的剖面圖。 【主要元件符號說明】 10,20基板 11，22閘極 12圖案化犧牲層 . 13硼磷矽酸玻璃介電層 14孔洞 15凹口 16接觸窗 20A預定接觸區域 21氮化襯層 31犧牲層 32硬遮罩層 41圖案化光阻層 51圖案化硬遮罩層 61圖案化犧牲層 62溝渠 71第一介電層 74,75孔洞 81凹口 91第二介電層 110接觸窗 4NTC/06035TW ； 2006-0017-TW 11SiH4, PH3, 〇2, 〇3, b2H6, TEOS, ΤΕΒ (triethyl phthalate, iEthyl-Bome), ΤΜΡ (trimethyl phosphate, Tri_Methyl_phQsphate). After the deposition of borophosphoric acid glass is completed, it is usually necessary to carry out a further heat flow step to planarize (4) gift _ Cheng self. Deleting the Wei glass _ minus temperature depends on the vertical glass transfer temperature, usually lower than WC. In this concept, the holes 74 and 75 shown in the figure will be accommodated in the first dielectric layer 71 after the completion of the dielectric layer 71. Fig. 8 is a view showing a structure formed by planarizing the first dielectric layer 71 to a desired height by chemical mechanical polishing. After grinding, 'some holes (such as holes 7 will be eliminated) but some holes (such as holes 75) will become concave 0 81 as shown in the figure. Can be known, such as scanning electrons _ observe whether there are holes 81. If present, a second dielectric layer 91 can be formed to fill the recess 8 as described below. 4NTC/06035TW; 2006-0017-TW 8 200908218 FIG. 9 shows a blanket deposition of a second dielectric Step of layer %. The material of the second dielectric layer 91 may be selected from any of spin-on dielectric materials, such as spin-on glass spins such as polysilazane, or in a low temperature condition. A precursor such as SiH4 or the like is reacted to form a liquid silidic acid. After the spin coating is completed, the organic solvent contained in the slit glass may be distilled off by a hot baking step. The temperature is generally in the range of 3 〇〇〇 c to 4 〇〇. (In the range of :, the substrate 20 can be placed on the - contact plate. The organic solution is removed, and the substrate 20 is sent to the hot furnace tube for curing. Step, the curing temperature is preferably below 8 〇〇 t: below. When curing, it is possible to provide oxygen or simmer in the furnace. It should be noted here that although the second dielectric layer 91 is formed to fill the recess 81, however, when mass production is performed, if it is to be detected whether or not the mother substrate 20 has a notch 81, it is determined whether or not it is necessary. Forming the second dielectric layer 91 will take a considerable amount of time. Therefore, in mass production, it is preferred to form the second dielectric layer 91 directly after planarizing the first dielectric layer 71. On the surface of the electric layer 71, the step of detecting whether or not the notch 81 is generated may be omitted. In other words, for the convenience of the process, the step of forming the second dielectric layer 91 may be performed regardless of whether or not the notch 81 is generated. After the curing is completed, a portion of the second dielectric layer 91 is removed to expose the patterned sacrificial layer 61. This step may be performed by chemical mechanical polishing or etching. After completing the above steps, The thickness of the first dielectric layer 71 or the patterned sacrificial layer 61 above the substrate 20 is preferably between about 4 Å and 6 Å. It should be noted that the second dielectric layer has been formed in the recess 81. Filled in 91. However, if there are no notches 81 is generated, this step will completely remove the second dielectric layer 9. Next, the residual patterned sacrificial layer 61 is removed as shown in Fig. 11 to form a contact window 110. The contact window 110 exposes the predetermined contact region 20A. The residual pattern is removed. The method of '4NTC/06035TW; 2006-0017-TW 9 200908218 f layer 6!' can be carried out by dry-cutting, using a reaction gas having a high selectivity with respect to the first retention patterned sacrificial layer 61: 71 pairs of 曰1 its removal method can be dry-closed, ^ Ray 71, the nitrided liner 21 has a highly selective reaction gas to carry out the ten-first-dielectric layer of the only forest (four) Dejia Shiguan And _ 崎 本 本 本 之 之 之 之 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2006 2006 2006 2006 2006 2006 2006 2006 A cross-sectional view of the semiconductor structure during fabrication. 2 through 11 are cross-sectional views showing a semiconductor structure in a process flow of an embodiment of the present invention. [Main component symbol description] 10, 20 substrate 11, 22 gate 12 patterned sacrificial layer. 13 borophosphosilicate glass dielectric layer 14 hole 15 recess 16 contact window 20A predetermined contact region 21 nitride liner 31 sacrificial layer 32 hard mask layer 41 patterned photoresist layer 51 patterned hard mask layer 61 patterned sacrificial layer 62 trench 71 first dielectric layer 74, 75 hole 81 recess 91 second dielectric layer 110 contact window 4NTC/06035TW ; 2006-0017-TW 11